Switch - PLX Technology
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PCI Express Features ‣ Maximum payload size 256B ‣ Support for polarity reversal ‣ EEPROM support ‣ Interrupts transferred between ports • Message signal interrupt propagates to PCI-X interrupt • PCI-X interrupt propagates to message signal interrupt ‣ Power management: • Link power management states: L0, L0s, L1, L2/L3 Ready, L2, L3 • Device power management states: D0, D3 HOT ‣ RAS features • Hot Plug master & slave • TLP Digest support: • Poison bit and End to end CRC PEX 8114 © PLX Aug 2007 54
PCI-X/PCI Bus Features ‣ PCI-X r1.0b and PCI r 3.0 compliant • PCI-X operation up to 133 MHz • 64-bit/32-bit PCI operation up to 66 MHz • 64-bit addressing as master and slave • Memory and I/O data transfers • Up to 8 outstanding split PCI-X transactions ‣ PCI Power Management r1.1 compliant PEX 8114 • Supports D0, D3 HOT ‣ Arbiter supports 4 external masters • Arbiter can be disabled to allow external arbiter © PLX Aug 2007 55
- Page 3 and 4: PLX Interconnect Products ‣ PLX i
- Page 5 and 6: PCI Express in Servers Bridge GE CP
- Page 7 and 8: PCI Express in Peripherals & Consum
- Page 9 and 10: PCI Express in Embedded FPGA FPGA B
- Page 11 and 12: PLX: Switch Market Leading Supplier
- Page 13 and 14: Port Flexibility ‣ Flexible • P
- Page 15 and 16: Crosslink & Moveable Upstream Port
- Page 17 and 18: Cut-Thru ‣ Cut-Thru Architecture
- Page 19 and 20: Port Arbitration ‣ Allows priorit
- Page 21 and 22: Non-Blocking Internal Architecture
- Page 23 and 24: Spread Spectrum Clock Support T Hos
- Page 25 and 26: VAUX/WAKE#/Beacon WAKE#/Beacon Supp
- Page 27 and 28: Additional Key Features ‣ Quality
- Page 29 and 30: 48 Lane Switch ‣ PEX 8548 • Ind
- Page 31 and 32: Storage Servers CPU Chip Set Memory
- Page 33 and 34: 32 Lane Port Configurations PEX 853
- Page 35 and 36: 24 Lane Port Configurations PEX 852
- Page 37 and 38: 16 Lane Port Configurations x4 PEX
- Page 39 and 40: 12 Lane Port Configurations x4 PEX
- Page 41 and 42: 8 Lane Port Configurations PEX 8508
- Page 43 and 44: 5 Lane Port Configurations x1 PEX 8
- Page 45 and 46: Bridge Road Map - PCI, PCI-X, PCIe
- Page 47 and 48: PEX 8111 Overview ‣ Proven Intero
- Page 49 and 50: Example on Motherboard PCI Slots PC
- Page 51 and 52: PCI Features ‣ PCI r3.0 compliant
- Page 53: PCIe to PCI-X Bridge Example 4 4 PE
- Page 57 and 58: AdvancedTCA with AMC PCI - X PCI-X
- Page 59 and 60: Local Bus Bridge Road Map Local/PCI
- Page 61 and 62: System Controller Card EEPROM SRAM
- Page 63: End of Presentation Thank You www.p
PCI-X/PCI Bus Features<br />
‣ PCI-X r1.0b and PCI r 3.0 compliant<br />
• PCI-X operation up to 133 MHz<br />
• 64-bit/32-bit PCI operation up to 66 MHz<br />
• 64-bit addressing as master and slave<br />
• Memory and I/O data transfers<br />
• Up to 8 outstanding split PCI-X<br />
transactions<br />
‣ PCI Power Management r1.1 compliant<br />
PEX 8114<br />
• Supports D0, D3 HOT<br />
‣ Arbiter supports 4 external masters<br />
• Arbiter can be disabled to allow external<br />
arbiter<br />
© <strong>PLX</strong> Aug 2007 55
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