Switch - PLX Technology
Switch - PLX Technology Switch - PLX Technology
24 Lane Switches ‣ PEX 8524 • Non-Transparent switch • Redundant Systems, Dual-Host, Fail-over Systems ‣ PEX 8525 • Performance optimized switch with industry’s lowest latency - 115ns • Servers, Storage, Graphics, Peer-to-Peer Communication Feature PEX 8524 PEX 8525 Lanes 24 24 Ports 6 5 Latency > 200ns 115ns (x8 to x8) Non-Transparency Yes No Hot-Plug Ports 6 3 Maximum Payload Size 256 B 1 KB Availability In Production Now In Production Now Package 31 x 31 mm 2 31 x 31 mm 2 Typical Power 3.9 W 2.6 W © PLX Aug 2007 34
24 Lane Port Configurations PEX 8524 PEX 8525 x4 x8 x8 x8 x4 PEX 8524 PEX 8524 PEX 8525 PEX 8525 x4 x4 x4 x4 x8 x8 x4x4x4x4 x8 x8 x8 x8 x8 x4 PEX 8524 x2 PEX 8524 PEX 8525 PEX 8525 x4 x4 x4 x4 x4 x4 x4x2 x8 x4 x4 x4x4x4x4 ‣ Many other configurations possible ‣ Higher lane-width port will auto-negotiation down © PLX Aug 2007 35
- Page 1 and 2: PLX Technology PCI Express Products
- Page 3 and 4: PLX Interconnect Products ‣ PLX i
- Page 5 and 6: PCI Express in Servers Bridge GE CP
- Page 7 and 8: PCI Express in Peripherals & Consum
- Page 9 and 10: PCI Express in Embedded FPGA FPGA B
- Page 11 and 12: PLX: Switch Market Leading Supplier
- Page 13 and 14: Port Flexibility ‣ Flexible • P
- Page 15 and 16: Crosslink & Moveable Upstream Port
- Page 17 and 18: Cut-Thru ‣ Cut-Thru Architecture
- Page 19 and 20: Port Arbitration ‣ Allows priorit
- Page 21 and 22: Non-Blocking Internal Architecture
- Page 23 and 24: Spread Spectrum Clock Support T Hos
- Page 25 and 26: VAUX/WAKE#/Beacon WAKE#/Beacon Supp
- Page 27 and 28: Additional Key Features ‣ Quality
- Page 29 and 30: 48 Lane Switch ‣ PEX 8548 • Ind
- Page 31 and 32: Storage Servers CPU Chip Set Memory
- Page 33: 32 Lane Port Configurations PEX 853
- Page 37 and 38: 16 Lane Port Configurations x4 PEX
- Page 39 and 40: 12 Lane Port Configurations x4 PEX
- Page 41 and 42: 8 Lane Port Configurations PEX 8508
- Page 43 and 44: 5 Lane Port Configurations x1 PEX 8
- Page 45 and 46: Bridge Road Map - PCI, PCI-X, PCIe
- Page 47 and 48: PEX 8111 Overview ‣ Proven Intero
- Page 49 and 50: Example on Motherboard PCI Slots PC
- Page 51 and 52: PCI Features ‣ PCI r3.0 compliant
- Page 53 and 54: PCIe to PCI-X Bridge Example 4 4 PE
- Page 55 and 56: PCI-X/PCI Bus Features ‣ PCI-X r1
- Page 57 and 58: AdvancedTCA with AMC PCI - X PCI-X
- Page 59 and 60: Local Bus Bridge Road Map Local/PCI
- Page 61 and 62: System Controller Card EEPROM SRAM
- Page 63: End of Presentation Thank You www.p
24 Lane Port Configurations<br />
PEX 8524<br />
PEX 8525<br />
x4<br />
x8<br />
x8<br />
x8<br />
x4<br />
PEX 8524<br />
PEX 8524<br />
PEX 8525<br />
PEX 8525<br />
x4 x4 x4 x4<br />
x8<br />
x8<br />
x4x4x4x4<br />
x8<br />
x8<br />
x8<br />
x8<br />
x8<br />
x4<br />
PEX 8524<br />
x2<br />
PEX 8524<br />
PEX 8525<br />
PEX 8525<br />
x4 x4 x4 x4<br />
x4 x4 x4x2<br />
x8<br />
x4<br />
x4<br />
x4x4x4x4<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 35
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