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Reliability & Serviceability ‣ Performance Monitoring • Allows users to monitor device and system performance on a per port basis: • TLP throughput & Queue depths • Blocking, stalling, over-subscription detection ‣ Internal Testability Features • JTAG support • BIST for internal memories • Lane/Port status indicators ‣ Debug Features • PRBS generator for bit error rate characterization • SerDes loopback mode (four levels) • Error Injection © <strong>PLX</strong> Aug 2007 26
Additional Key Features ‣ Quality of Service • Up to Two Virtual Channels ‣ Lane and polarity reversal supported on all ports ‣ Up to 32 General Purpose Output Pins ‣ FATAL_ERR# and INTA# support ‣ Error Handler • PCI Express Advanced error reporting • Poison-bit & end-to-end CRC ‣ Industrial Temp Support ‣ SerDes power control • Off, low, typical and high • Turn off unused SerDes blocks © <strong>PLX</strong> Aug 2007 27
Page 1 and 2: PLX Technology PCI Express Products
Page 3 and 4: PLX Interconnect Products ‣ PLX i
Page 5 and 6: PCI Express in Servers Bridge GE CP
Page 7 and 8: PCI Express in Peripherals & Consum
Page 9 and 10: PCI Express in Embedded FPGA FPGA B
Page 11 and 12: PLX: Switch Market Leading Supplier
Page 13 and 14: Port Flexibility ‣ Flexible • P
Page 15 and 16: Crosslink & Moveable Upstream Port
Page 17 and 18: Cut-Thru ‣ Cut-Thru Architecture
Page 19 and 20: Port Arbitration ‣ Allows priorit
Page 21 and 22: Non-Blocking Internal Architecture
Page 23 and 24: Spread Spectrum Clock Support T Hos
Page 25: VAUX/WAKE#/Beacon WAKE#/Beacon Supp
Page 29 and 30: 48 Lane Switch ‣ PEX 8548 • Ind
Page 31 and 32: Storage Servers CPU Chip Set Memory
Page 33 and 34: 32 Lane Port Configurations PEX 853
Page 37 and 38: 16 Lane Port Configurations x4 PEX
Page 39 and 40: 12 Lane Port Configurations x4 PEX
Page 43 and 44: 5 Lane Port Configurations x1 PEX 8
Page 45 and 46: Bridge Road Map - PCI, PCI-X, PCIe
Page 47 and 48: PEX 8111 Overview ‣ Proven Intero
Page 49 and 50: Example on Motherboard PCI Slots PC
Page 51 and 52: PCI Features ‣ PCI r3.0 compliant
Page 53 and 54: PCIe to PCI-X Bridge Example 4 4 PE
Page 55 and 56: PCI-X/PCI Bus Features ‣ PCI-X r1
Page 57 and 58: AdvancedTCA with AMC PCI - X PCI-X
Page 59 and 60: Local Bus Bridge Road Map Local/PCI
Page 61 and 62: System Controller Card EEPROM SRAM
Page 63: End of Presentation Thank You www.p

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