Switch - PLX Technology
Switch - PLX Technology Switch - PLX Technology
PLX Switches with Hot-Plug PLX PCIe Switch PCIe hot-plug control registers PCIe Switch w/o Hot Plug Controller No PCIe hot-plug control registers Voltage Cont. Clk Voltage Cont. CPLD $5 Clk Power HPPERST Clock Power HPPERST Clock ‣ PLX PCIe Switches ‣ Other PCIe Switches • Internal Hot-Plug Controllers • Require External CPLD $! • Provide PCIe Hot-Plug Registers • May not provide PCIe Hot-Plug and 9 Hot-Plug signals Registers Software burden! • Minimal External Circuitry Needed • Additional External Circuitry Needed • Available on 2 to 8 ports © PLX Aug 2007 16
Cut-Thru ‣ Cut-Thru Architecture – reduced latency • Moves packet to Egress port after reading packet header • Increased performance with bursty traffic ‣ Store & Forward Architecture • Moves packet to Egress port after reading entire packet 1001011000110110 Ingress Port Cut-Thru Path Egress Port 1001011000110110 Payload Header PCIe Switch Payload Header 1001011000110110 Ingress Port Egress Port 100101100011 0110 Payload Header Store & Forward Path Payload Header © PLX Aug 2007 17
- Page 1 and 2: PLX Technology PCI Express Products
- Page 3 and 4: PLX Interconnect Products ‣ PLX i
- Page 5 and 6: PCI Express in Servers Bridge GE CP
- Page 7 and 8: PCI Express in Peripherals & Consum
- Page 9 and 10: PCI Express in Embedded FPGA FPGA B
- Page 11 and 12: PLX: Switch Market Leading Supplier
- Page 13 and 14: Port Flexibility ‣ Flexible • P
- Page 15: Crosslink & Moveable Upstream Port
- Page 19 and 20: Port Arbitration ‣ Allows priorit
- Page 21 and 22: Non-Blocking Internal Architecture
- Page 23 and 24: Spread Spectrum Clock Support T Hos
- Page 25 and 26: VAUX/WAKE#/Beacon WAKE#/Beacon Supp
- Page 27 and 28: Additional Key Features ‣ Quality
- Page 29 and 30: 48 Lane Switch ‣ PEX 8548 • Ind
- Page 31 and 32: Storage Servers CPU Chip Set Memory
- Page 33 and 34: 32 Lane Port Configurations PEX 853
- Page 35 and 36: 24 Lane Port Configurations PEX 852
- Page 37 and 38: 16 Lane Port Configurations x4 PEX
- Page 39 and 40: 12 Lane Port Configurations x4 PEX
- Page 41 and 42: 8 Lane Port Configurations PEX 8508
- Page 43 and 44: 5 Lane Port Configurations x1 PEX 8
- Page 45 and 46: Bridge Road Map - PCI, PCI-X, PCIe
- Page 47 and 48: PEX 8111 Overview ‣ Proven Intero
- Page 49 and 50: Example on Motherboard PCI Slots PC
- Page 51 and 52: PCI Features ‣ PCI r3.0 compliant
- Page 53 and 54: PCIe to PCI-X Bridge Example 4 4 PE
- Page 55 and 56: PCI-X/PCI Bus Features ‣ PCI-X r1
- Page 57 and 58: AdvancedTCA with AMC PCI - X PCI-X
- Page 59 and 60: Local Bus Bridge Road Map Local/PCI
- Page 61 and 62: System Controller Card EEPROM SRAM
- Page 63: End of Presentation Thank You www.p
<strong>PLX</strong> <strong>Switch</strong>es with Hot-Plug<br />
<strong>PLX</strong> PCIe<br />
<strong>Switch</strong><br />
PCIe hot-plug<br />
control registers<br />
PCIe <strong>Switch</strong><br />
w/o Hot Plug<br />
Controller<br />
No PCIe hot-plug<br />
control registers<br />
Voltage<br />
Cont.<br />
Clk<br />
Voltage<br />
Cont.<br />
CPLD<br />
$5<br />
Clk<br />
Power<br />
HPPERST<br />
Clock<br />
Power<br />
HPPERST<br />
Clock<br />
‣ <strong>PLX</strong> PCIe <strong>Switch</strong>es<br />
‣ Other PCIe <strong>Switch</strong>es<br />
• Internal Hot-Plug Controllers • Require External CPLD $!<br />
• Provide PCIe Hot-Plug Registers<br />
• May not provide PCIe Hot-Plug<br />
and 9 Hot-Plug signals<br />
Registers Software burden!<br />
• Minimal External Circuitry Needed<br />
• Additional External Circuitry Needed<br />
• Available on 2 to 8 ports<br />
© <strong>PLX</strong> Aug 2007 16
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