Switch - PLX Technology
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<strong>PLX</strong> <strong>Technology</strong><br />
PCI Express Products<br />
Q3CY07
Corporate Overview<br />
‣ Public U.S. Company<br />
• Founded in 1986<br />
• IPO in 1999<br />
• NASDAQ: <strong>PLX</strong>T<br />
‣ Headquarters in Sunnyvale, CA<br />
• 160 Employees<br />
• Sales & Technical Support Worldwide<br />
• Fabless Semiconductor Business Model<br />
‣ Over 1000 customers worldwide<br />
© <strong>PLX</strong> Aug 2007 2
<strong>PLX</strong> Interconnect Products<br />
‣ <strong>PLX</strong> is the World Leader in I/O Interconnect Products<br />
‣ Our broad product line of devices can bridge popular I/O<br />
standards including PCI Express®<br />
Local<br />
Bus<br />
Bridges<br />
Conceptual Drawing, not every possible option available currently from <strong>PLX</strong><br />
© <strong>PLX</strong> Aug 2007 3
PCI Express® Focus = Leadership<br />
‣ Market Leader<br />
• Engaged with most leading server, storage, & communication companies<br />
• Only public semiconductor company focused 100% on PCI Express<br />
<strong>Switch</strong>es and Bridges<br />
‣ Broadest Offering of<br />
PCI Express Bridges & <strong>Switch</strong>es<br />
‣ Over 1,000,000 units shipped<br />
‣ Objective:<br />
• Remain #1 Supplier<br />
of PCI Express<br />
<strong>Switch</strong>es and Bridges<br />
in the Industry<br />
<strong>Switch</strong>es<br />
Bridges<br />
More On<br />
Leadership<br />
More On<br />
Leadership<br />
© <strong>PLX</strong> Aug 2007 4
PCI Express in Servers<br />
Bridge<br />
GE<br />
CPU<br />
GE<br />
<strong>Switch</strong><br />
Chip Set<br />
Memory<br />
Adapter & Riser Cards<br />
<strong>Switch</strong><br />
Stand-alone<br />
alone<br />
<strong>Switch</strong><br />
I/O<br />
I/O<br />
Rack-<br />
mount<br />
Blade<br />
I/O<br />
Bridge<br />
I/O<br />
Server<br />
Motherboard<br />
© <strong>PLX</strong> Aug 2007 5
PCI Express in Storage Systems<br />
CPU<br />
CPU<br />
Storage<br />
SAN<br />
NAS<br />
Chip Set<br />
Memory<br />
Chip Set<br />
Memory<br />
FC<br />
FC<br />
<strong>Switch</strong><br />
<strong>Switch</strong><br />
NT<br />
I/O<br />
NT<br />
<strong>Switch</strong><br />
I/O<br />
I/O<br />
I/O<br />
SAS<br />
SAS<br />
<strong>Switch</strong><br />
Bridge<br />
I/O<br />
Bridge<br />
I/O<br />
High Availability Storage System<br />
© <strong>PLX</strong> Aug 2007 6
PCI Express in Peripherals & Consumer<br />
GPU<br />
Bridge<br />
GPU<br />
GPU<br />
<strong>Switch</strong><br />
Graphics - Reverse Bridge<br />
Graphics – More Monitors<br />
or Higher Resolution<br />
TV<br />
Tuner<br />
Bridge<br />
Mobile<br />
TV<br />
PCI Express TV Tuner<br />
Computer Peripheral<br />
and Consumer Electronics<br />
Printer<br />
Wireless LAN<br />
Graphics/<br />
Video<br />
© <strong>PLX</strong> Aug 2007 7
PCI Express in Communications<br />
DSLAM<br />
Base Station<br />
Controller<br />
Wireless<br />
LAN Gateway<br />
Enterprise Storage<br />
Co-Processor-<br />
Security/DSP<br />
<strong>Switch</strong><br />
NT<br />
NPU/ASIC<br />
VoIP<br />
Gateway<br />
Remote Access<br />
Concentrator<br />
Router/<strong>Switch</strong><br />
Local<br />
Processor<br />
Framer<br />
PHY<br />
Line Card 1<br />
Communications<br />
Line Card n<br />
<strong>Switch</strong><br />
Control<br />
Processor<br />
Memory<br />
Supervisory or Controller Card<br />
© <strong>PLX</strong> Aug 2007 8
PCI Express in Embedded<br />
FPGA<br />
FPGA<br />
Bridge<br />
Bridge<br />
Memory<br />
CPU<br />
Imaging/Graphics<br />
Printer<br />
Medical<br />
Industrial<br />
Embedded<br />
<strong>Switch</strong><br />
FPGA<br />
Bridge<br />
Industrial Control &<br />
Instrumentation<br />
I/O<br />
I/O<br />
Host<br />
CPU<br />
Bridge<br />
PCIe<br />
ASIC<br />
Embedded Host System<br />
© <strong>PLX</strong> Aug 2007 9
48<br />
32<br />
24<br />
16<br />
12<br />
8<br />
<strong>PLX</strong>: <strong>Switch</strong> Market Leading Supplier<br />
‣ First to Market PCIe 1.0 devices in 2004<br />
• Three Generations of <strong>PLX</strong> Architecture Introduced<br />
• Constantly improving through experience<br />
• Shipped Hundreds of Thousands<br />
• Sampling broad customer base<br />
• PCIe 2.0 well into development<br />
‣ Broadest <strong>Switch</strong> Portfolio<br />
• 13 Devices Available Today<br />
• 5 to 48 Lanes<br />
• 3 to 9 Ports<br />
• More in Development Today<br />
• Many more planned<br />
© <strong>PLX</strong> Aug 2007 11
Optimized for Different Applications<br />
‣ Fan-out for Servers & HBAs<br />
• Cost Optimized<br />
• Industry best performance & latency<br />
• 110ns Latency<br />
• Smallest Packages in the Industry<br />
‣ Peer-to-Peer for Backplanes<br />
• No CPU intervention required<br />
‣ Non-Transparency for Host/Address Domain Isolation<br />
• Dual Host and Failover<br />
‣ High Port Count<br />
• For Control Planes needing lots of connectivity<br />
© <strong>PLX</strong> Aug 2007 12
Port Flexibility<br />
‣ Flexible<br />
• Ports configurable as x1, x2, x4, x8, x16<br />
• Customize to meet your design’s needs<br />
• Auto-negotiation of port width supported<br />
• Will negotiate down to x8, x4, x2, or x1<br />
‣ Versatile<br />
• Any port can be upstream<br />
• Movable upstream port<br />
• Cross-link capability<br />
• Dual-host support<br />
4 x2 ports<br />
2 x4 ports<br />
1 x8 port<br />
PCIe<br />
<strong>Switch</strong><br />
© <strong>PLX</strong> Aug 2007 13
Dual-Host & Failover Options<br />
‣ Two methods of implementing Failover Systems<br />
• Non-Transparent Port<br />
• Crosslink & Moveable Upstream Port Primary<br />
Host<br />
Secondary<br />
Host<br />
‣ Crosslink & Moveable Upstream Port<br />
• Utilized when user has full control of<br />
system software (OS)<br />
and enumeration process<br />
<strong>Switch</strong><br />
‣ Non-Transparent Port<br />
• Utilized when user has no or limited control of system<br />
software (OS) and/or enumeration process<br />
© <strong>PLX</strong> Aug 2007 14
Crosslink & Moveable Upstream Port<br />
CPU 1<br />
CPU 2<br />
Chip Set<br />
Memory<br />
Chip Set<br />
Memory<br />
Upstream<br />
End<br />
Point<br />
<strong>Switch</strong><br />
Downstream<br />
Crosslink<br />
<strong>Switch</strong><br />
End<br />
Point<br />
End<br />
Point<br />
End<br />
Point<br />
End<br />
Point<br />
‣ Crosslink allows 2 downstream ports to link up<br />
‣ Crosslink and moveable upstream functions can be used to provide<br />
dual host or fail-over capability<br />
© <strong>PLX</strong> Aug 2007 15
<strong>PLX</strong> <strong>Switch</strong>es with Hot-Plug<br />
<strong>PLX</strong> PCIe<br />
<strong>Switch</strong><br />
PCIe hot-plug<br />
control registers<br />
PCIe <strong>Switch</strong><br />
w/o Hot Plug<br />
Controller<br />
No PCIe hot-plug<br />
control registers<br />
Voltage<br />
Cont.<br />
Clk<br />
Voltage<br />
Cont.<br />
CPLD<br />
$5<br />
Clk<br />
Power<br />
HPPERST<br />
Clock<br />
Power<br />
HPPERST<br />
Clock<br />
‣ <strong>PLX</strong> PCIe <strong>Switch</strong>es<br />
‣ Other PCIe <strong>Switch</strong>es<br />
• Internal Hot-Plug Controllers • Require External CPLD $!<br />
• Provide PCIe Hot-Plug Registers<br />
• May not provide PCIe Hot-Plug<br />
and 9 Hot-Plug signals<br />
Registers Software burden!<br />
• Minimal External Circuitry Needed<br />
• Additional External Circuitry Needed<br />
• Available on 2 to 8 ports<br />
© <strong>PLX</strong> Aug 2007 16
Cut-Thru<br />
‣ Cut-Thru Architecture – reduced latency<br />
• Moves packet to Egress port after reading packet header<br />
• Increased performance with bursty traffic<br />
‣ Store & Forward Architecture<br />
• Moves packet to Egress port after reading entire packet<br />
1001011000110110<br />
Ingress<br />
Port<br />
Cut-Thru Path<br />
Egress<br />
Port<br />
1001011000110110<br />
Payload<br />
Header<br />
PCIe <strong>Switch</strong><br />
Payload<br />
Header<br />
1001011000110110<br />
Ingress<br />
Port<br />
Egress<br />
Port<br />
100101100011<br />
0110<br />
Payload<br />
Header<br />
Store & Forward Path<br />
Payload<br />
Header<br />
© <strong>PLX</strong> Aug 2007 17
True Peer-to-Peer Support<br />
Root<br />
Complex<br />
Root<br />
Complex<br />
End<br />
Point<br />
<strong>Switch</strong><br />
End<br />
Point<br />
End<br />
Point<br />
Other PCIe<br />
<strong>Switch</strong>es<br />
End<br />
Point<br />
End<br />
End<br />
Point<br />
Point<br />
‣ <strong>PLX</strong> PCIe <strong>Switch</strong>es<br />
• Simultaneous Transactions<br />
• No host involvement<br />
• Reduced latency<br />
• Enhanced CPU Performance<br />
• Optimized Peer-to-Peer<br />
Bandwidth/Performance<br />
End<br />
End<br />
Point<br />
Point<br />
‣ Other PCIe <strong>Switch</strong>es<br />
• Claim Peer-to-Peer…but…<br />
• No Simultaneous Transactions<br />
• May require host-support<br />
• Added latency<br />
• Reduced CPU Performance<br />
• Bandwidth/Performance impact<br />
for Peer-to-Peer traffic<br />
© <strong>PLX</strong> Aug 2007 18
Port Arbitration<br />
‣ Allows priority assignment to specific ports<br />
• Round Robin or Weighted Round Robin schemes can be used<br />
Egress Port<br />
<strong>Switch</strong><br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
010101000011110101011<br />
Packet<br />
Queue<br />
User assigns priority or weight for<br />
ports<br />
Example:<br />
Green port weight = 2<br />
Yellow and Gray weight = 1<br />
Port arbiter serves green port twice<br />
the rate of other ports<br />
Ingress Ports<br />
© <strong>PLX</strong> Aug 2007 19
Device Configuration<br />
‣ Register Configuration via:<br />
• I 2 C – Two wire protocol<br />
defined by Philips<br />
• Out of band device<br />
configuration<br />
• EEPROM – Serial Load<br />
• Configures device prior to<br />
BIOS access<br />
• In Band – Memory<br />
mapped via PCIe link<br />
• In band device<br />
configuration by host<br />
‣ Hardware Strapping<br />
• Using Pull-up/Pull-down<br />
resistors<br />
Signal Strapping<br />
<strong>Switch</strong><br />
I 2 C<br />
CSRs<br />
EEPROM<br />
PCIe<br />
Upstream Link<br />
Multiple Ways to Configure <strong>PLX</strong> <strong>Switch</strong>es<br />
© <strong>PLX</strong> Aug 2007 20
Non-Blocking Internal Architecture<br />
‣ Allows traffic between ports at full line rates<br />
‣ Flexible buffer allocation<br />
• Prevents head of line blocking<br />
<strong>Switch</strong><br />
© <strong>PLX</strong> Aug 2007 21
Spread Spectrum Clock Support<br />
‣ SSC Systems Supports Single Clock Domain<br />
• Reduces EMI<br />
‣ Supports Two clock domains<br />
• SSC Domain<br />
• Modulated clock input<br />
• Constant clock domain<br />
• Constant clock input<br />
‣ Advantages for having Two clock domains<br />
• Removes requirement for single source clock<br />
• Important for Modular Systems<br />
Host 1<br />
SSC Domain 1<br />
Host 2<br />
SSC Domain 2<br />
© <strong>PLX</strong> Aug 2007 22
Spread Spectrum Clock Support<br />
T<br />
Host 1<br />
SSC Domain 1<br />
OSC<br />
SSC Clock<br />
Buffer<br />
CPU<br />
Bridge<br />
Constant Clock<br />
Domain (Non-SSC)<br />
CPU<br />
Bridge<br />
Host 2<br />
SSC Domain 2<br />
OSC<br />
SSC Clock<br />
Buffer<br />
I/O<br />
I/O<br />
I/O<br />
<strong>Switch</strong> NT <strong>Switch</strong><br />
T<br />
NT<br />
I/O<br />
I/O<br />
OSC<br />
OSC<br />
I/O<br />
Constant Clock Input<br />
© <strong>PLX</strong> Aug 2007 23
Power Management<br />
‣ Supports all required PCIe Link & Device Power Management States<br />
‣ Additional Power Management Support<br />
• WAKE#<br />
• Out of band mechanism used by endpoints to inform host of power<br />
state change<br />
• Beacon<br />
• In-band mechanism used by PCIe devices to<br />
inform host of power state change<br />
• VAUX<br />
• Auxiliary voltage supply for Beacon internal circuit<br />
‣ VAUX/WAKE#/Beacon support<br />
• WAKE# - Input Signal to <strong>Switch</strong><br />
• <strong>Switch</strong> generates in-band Beacon sequence<br />
to host when WAKE# is active<br />
© <strong>PLX</strong> Aug 2007 24
VAUX/WAKE#/Beacon<br />
WAKE#/Beacon Support<br />
present in <strong>Switch</strong><br />
WAKE#/Beacon Support<br />
not present in <strong>Switch</strong><br />
CPU<br />
CPU<br />
Chipset<br />
Chipset<br />
WAKE#<br />
I/O<br />
Beacon<br />
I/O<br />
I/O<br />
<strong>Switch</strong><br />
<strong>Switch</strong><br />
VAUX<br />
<strong>Switch</strong><br />
I/O<br />
I/O<br />
I/O<br />
WAKE#<br />
© <strong>PLX</strong> Aug 2007 25
Reliability & Serviceability<br />
‣ Performance Monitoring<br />
• Allows users to monitor device and system performance on<br />
a per port basis:<br />
• TLP throughput & Queue depths<br />
• Blocking, stalling, over-subscription detection<br />
‣ Internal Testability Features<br />
• JTAG support<br />
• BIST for internal memories<br />
• Lane/Port status indicators<br />
‣ Debug Features<br />
• PRBS generator for bit error rate characterization<br />
• SerDes loopback mode (four levels)<br />
• Error Injection<br />
© <strong>PLX</strong> Aug 2007 26
Additional Key Features<br />
‣ Quality of Service<br />
• Up to Two Virtual Channels<br />
‣ Lane and polarity reversal supported on all ports<br />
‣ Up to 32 General Purpose Output Pins<br />
‣ FATAL_ERR# and INTA# support<br />
‣ Error Handler<br />
• PCI Express Advanced error reporting<br />
• Poison-bit & end-to-end CRC<br />
‣ Industrial Temp Support<br />
‣ SerDes power control<br />
• Off, low, typical and high<br />
• Turn off unused SerDes blocks<br />
© <strong>PLX</strong> Aug 2007 27
PCI Express <strong>Switch</strong>es<br />
Device Information<br />
PCIe Gen 1 (2.5GT/s)
48 Lane <strong>Switch</strong><br />
‣ PEX 8548<br />
• Industry’s first 48 lanes and 9 ports PCIe switches<br />
• Servers, ATCA Blades, Fan-out, Peer-to-Peer Communication,<br />
Graphics<br />
Feature PEX 8548<br />
Lanes 48<br />
Ports 9<br />
Latency 110ns (x16 to x16)<br />
Non-Transparency<br />
No<br />
Hot-Plug Ports 3<br />
Maximum Payload Size<br />
1 KB<br />
Availability<br />
In Production Now<br />
Package 37.5 x 37.5 mm 2<br />
Typical Power<br />
4.9 W<br />
© <strong>PLX</strong> Aug 2007 29
48 Lane Port Configurations<br />
x8<br />
x8<br />
PEX 8548<br />
x8<br />
x8<br />
x16<br />
PEX 8548<br />
PEX 8548<br />
x8<br />
x4<br />
x8<br />
PEX 8548<br />
x8<br />
x4<br />
x8<br />
x16<br />
PEX 8548<br />
x16<br />
x4 x4 x4 x4<br />
x16<br />
x16<br />
x4 x4 x4 x4<br />
x4<br />
x4<br />
x8<br />
x8<br />
PEX 8548<br />
x8<br />
x8<br />
x8<br />
PEX 8548<br />
x8<br />
x8<br />
x8<br />
x16<br />
PEX 8548<br />
x8<br />
x8<br />
x16<br />
PEX 8548<br />
x8<br />
x8<br />
x8<br />
x8<br />
x4<br />
x4 x8<br />
x4 x4 x4 x4<br />
x4<br />
x8<br />
x4<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 30
Storage Servers<br />
CPU<br />
Chip Set<br />
Memory<br />
x16<br />
End<br />
Point<br />
x8 PEX 8548<br />
x8 or x4 ports<br />
Bridge<br />
Bridge<br />
<strong>Switch</strong><br />
© <strong>PLX</strong> Aug 2007 31
32 Lane <strong>Switch</strong>es<br />
‣ PEX 8532<br />
• Non-Transparent switch<br />
• Redundant Systems, Dual-Host, Fail-over Systems<br />
‣ PEX 8533<br />
• Performance optimized switch with industry’s lowest latency - 115ns<br />
• Servers, Storage, Graphics, Fan-Out, Peer-to-Peer Communication<br />
Feature PEX 8532 PEX 8533<br />
Lanes 32 32<br />
Ports 8 6<br />
Latency > 200ns 115ns (x8 to x8)<br />
Non-Transparency Yes No<br />
Hot-Plug Ports 8 3<br />
Max. Payload Size 256 B 1 KB<br />
Availability In Production Now In Production Now<br />
Package 35 x 35 mm 2 35 x 35 mm 2<br />
Typical Power 5.7 W 3.3 W<br />
© <strong>PLX</strong> Aug 2007 32
32 Lane Port Configurations<br />
PEX 8532<br />
PEX 8533<br />
x4<br />
x4<br />
PEX 8532<br />
x4 x4 x4 x4<br />
x4<br />
x4<br />
x8<br />
x16<br />
PEX 8532<br />
x8<br />
x8<br />
x8<br />
PEX 8533<br />
x4x4x4x4<br />
x8<br />
x16<br />
PEX 8533<br />
x8<br />
x8<br />
x8<br />
x8<br />
x8<br />
x8<br />
PEX 8532<br />
x8<br />
x8<br />
PEX 8532<br />
PEX 8533<br />
PEX 8533<br />
x4<br />
x4<br />
x4 x4 x4 x4<br />
x8<br />
x8<br />
x8<br />
x4x4x8x8<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 33
24 Lane <strong>Switch</strong>es<br />
‣ PEX 8524<br />
• Non-Transparent switch<br />
• Redundant Systems, Dual-Host, Fail-over Systems<br />
‣ PEX 8525<br />
• Performance optimized switch with industry’s lowest latency - 115ns<br />
• Servers, Storage, Graphics, Peer-to-Peer Communication<br />
Feature PEX 8524 PEX 8525<br />
Lanes 24 24<br />
Ports 6 5<br />
Latency > 200ns 115ns (x8 to x8)<br />
Non-Transparency Yes No<br />
Hot-Plug Ports 6 3<br />
Maximum Payload Size 256 B 1 KB<br />
Availability In Production Now In Production Now<br />
Package 31 x 31 mm 2 31 x 31 mm 2<br />
Typical Power 3.9 W 2.6 W<br />
© <strong>PLX</strong> Aug 2007 34
24 Lane Port Configurations<br />
PEX 8524<br />
PEX 8525<br />
x4<br />
x8<br />
x8<br />
x8<br />
x4<br />
PEX 8524<br />
PEX 8524<br />
PEX 8525<br />
PEX 8525<br />
x4 x4 x4 x4<br />
x8<br />
x8<br />
x4x4x4x4<br />
x8<br />
x8<br />
x8<br />
x8<br />
x8<br />
x4<br />
PEX 8524<br />
x2<br />
PEX 8524<br />
PEX 8525<br />
PEX 8525<br />
x4 x4 x4 x4<br />
x4 x4 x4x2<br />
x8<br />
x4<br />
x4<br />
x4x4x4x4<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 35
16 Lane <strong>Switch</strong>es<br />
‣ PEX 8518<br />
• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon<br />
• Redundant Systems, Fan-Out, Servers, HBAs, NICs, Mezzanine cards<br />
‣ PEX 8517<br />
• Pin compatible migration from <strong>PLX</strong> 1 st generation 16-lane PEX 8516<br />
Feature PEX 8518* PEX 8517 PEX 8516<br />
Lanes 16 16 16<br />
Ports 5 5 4<br />
Latency 150ns 150ns > 200ns<br />
Non-Transparency Yes Yes Yes<br />
Hot-Plug Ports 5 4 4<br />
Maximum Payload Size 256 B 256 B 256 B<br />
Availability In Production In Production In Production<br />
Package 23 x 23 mm 2 27 x 27 mm 2 27 x 27 mm 2<br />
Typical Power 2.6 W 2.6 W 3.2 W<br />
* PEX 8518 recommended for all new 16 lane designs<br />
© <strong>PLX</strong> Aug 2007 36
16 Lane Port Configurations<br />
x4<br />
PEX 8518<br />
x8<br />
PEX 8518<br />
PEX 8518<br />
x4<br />
x4 x4<br />
x4<br />
x2<br />
x2<br />
x4<br />
x8<br />
PEX 8518<br />
PEX 8518<br />
x4 x4 x2 x2<br />
x2 x2 x2 x2<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 37
12 Lane <strong>Switch</strong><br />
‣ PEX 8512<br />
• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon<br />
• Fan-Out, HBAs, NICs, AMC/XMC plug-in cards, Redundant<br />
Systems, Host Isolation<br />
Feature PEX 8512<br />
Lanes 12<br />
Ports 5<br />
Latency<br />
150ns<br />
Non-Transparency<br />
Yes<br />
Hot-Plug Ports 3<br />
Maximum Payload Size 256 B<br />
Availability<br />
In Production<br />
Package 23 x23 mm 2<br />
Typical Power<br />
2.2 W<br />
© <strong>PLX</strong> Aug 2007 38
12 Lane Port Configurations<br />
x4<br />
PEX 8512<br />
x4<br />
PEX 8512<br />
PEX 8512<br />
x4<br />
x4<br />
x4<br />
x2<br />
x2<br />
x4<br />
PEX 8512<br />
x2 x2 x2 x2<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 39
8 Lane <strong>Switch</strong>es<br />
‣ PEX 8508<br />
• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon<br />
• Redundant Systems, Host Isolation, AMC/XMC plug-in cards<br />
‣ PEX 8509<br />
• Industry’s only 8 lanes & 8 ports PCIe switch<br />
• Control Planes, Docking Stations, NICs, High-end Printers<br />
Feature PEX 8508 PEX 8509<br />
Lanes 8 8<br />
Ports 5 8<br />
Latency 150ns 118ns (in x4 to x1 configuration)<br />
Non-Transparency Yes No<br />
Hot-Plug Ports 5 3<br />
Maximum Payload Size 256 B 1 KB<br />
Availability<br />
In Production<br />
Samples Now<br />
Production in Oct 2007<br />
Package 19 x 19 mm 2 15 x 15 mm 2<br />
Typical Power 1.6 W 1.2 W<br />
© <strong>PLX</strong> Aug 2007 40
8 Lane Port Configurations<br />
PEX 8508<br />
PEX 8509<br />
x4<br />
x4<br />
x4<br />
x2<br />
PEX 8508<br />
PEX 8508<br />
PEX 8509<br />
x2<br />
PEX 8509<br />
x1 x1 x1 x1<br />
x2<br />
x2<br />
x1x1x1x1<br />
x1x1x1x1<br />
x4<br />
x2<br />
x2<br />
x1<br />
PEX 8508<br />
PEX 8508<br />
x1<br />
PEX 8509<br />
x1<br />
x1<br />
PEX 8509<br />
x1<br />
x1<br />
x2<br />
x1<br />
x1<br />
x2 x2 x2<br />
x1x1x1x1<br />
x1x1x1x1<br />
‣ Many other configurations possible<br />
‣ Higher lane-width port will auto-negotiation down<br />
© <strong>PLX</strong> Aug 2007 41
5 Lane <strong>Switch</strong><br />
‣ PEX 8505<br />
• 5 lanes & 5 ports PCIe switch<br />
• Control Planes, Docking Stations, I/O expansion in PCs, High-end<br />
Printers, Consumer Electronic Systems<br />
Feature PEX 8505<br />
Lanes 5<br />
Ports 5<br />
Latency<br />
Non-Transparency<br />
138ns (in x2 to x1 configuration)<br />
Hot-Plug Ports 3<br />
Maximum Payload Size<br />
Availability<br />
No<br />
1 KB<br />
Samples Now<br />
Production in Oct 2007<br />
Package 15 x 15 mm 2<br />
Typical Power<br />
0.8 W<br />
© <strong>PLX</strong> Aug 2007 42
5 Lane Port Configurations<br />
x1<br />
PEX 8505<br />
x2<br />
PEX 8505<br />
PEX 8505<br />
x1 x1 x1 x1<br />
x1<br />
x1<br />
x1<br />
x1<br />
x2<br />
x1<br />
PEX 8505<br />
PEX 8505<br />
PEX 8505<br />
x1<br />
x1<br />
x1<br />
x2<br />
x1<br />
x1<br />
x1<br />
© <strong>PLX</strong> Aug 2007 43
ExpressLane PCI Express Bridges<br />
‣ PEX 8111 / PEX 8112 PCI to PCI Express<br />
• 32-Bit PCI (up to 66 MHz)<br />
• x1 PCIe<br />
‣ PEX 8114 - PCI-X to PCI Express<br />
• 64-Bit PCI-X (up to 133 MHz)<br />
• x4 PCIe<br />
‣ PEX 8311 - Generic Local to PCI Express<br />
• 32-Bit Local (up to 66 MHz)<br />
• x1 PCIe<br />
‣ Available TODAY!<br />
© <strong>PLX</strong> Aug 2007 44
Bridge Road Map - PCI, PCI-X, PCIe<br />
PCI/PCI-X<br />
Bus Speeds<br />
64 Bits<br />
133 MHz<br />
64 Bits<br />
66 MHz<br />
PCI 6254<br />
Non-Transparent<br />
Asynchronous<br />
PCI 6154<br />
Asynchronous<br />
31x31 mm 2 304 PBGA<br />
PCI 6466<br />
Non-Transparent<br />
Asynchronous<br />
PCI 6540<br />
PCI-X Non-Transparent<br />
Asynchronous<br />
PCI 6520<br />
PCI-X Asynchronous<br />
27x27 mm 2 380 PBGA<br />
PEX 8114<br />
64-Bit 133MHz PCI-X<br />
to x4 PCIe<br />
• Forward & Reverse Mode<br />
• Small 17x17mm Package<br />
• No Heat Sink Required<br />
32 Bits<br />
66MHz<br />
32 Bits<br />
33MHz<br />
PCI 6150<br />
High Performance<br />
Asynchronous<br />
PCI 6152<br />
Smallest Footprint<br />
15x15 mm 2 160 TBGA<br />
PCI 6140<br />
Lowest Power<br />
(200mW)<br />
Shipping Now<br />
In Development<br />
Planned/Concept<br />
PEX 8111<br />
32-Bit 66MHz PCI<br />
to x1 PCIe<br />
• Forward & Reverse Mode<br />
• Small 10x10 & 13x13mm Package<br />
• No Heat Sink Required<br />
PEX 8112<br />
Cost Reductions &<br />
Enhancements<br />
2003 & Before<br />
2004<br />
2005 2007<br />
© <strong>PLX</strong> Aug 2007 45
Forward and Reverse Bridging<br />
Primary<br />
Primary Bus<br />
Bridge<br />
Bridge<br />
Secondary Bus<br />
Secondary<br />
Forward Bridge<br />
Reverse Bridge<br />
© <strong>PLX</strong> Aug 2007 46
PEX 8111 Overview<br />
‣ Proven Interoperability<br />
• Exhaustive Testing at <strong>PLX</strong> Interop<br />
Labs<br />
• Proven interface for broad range of<br />
devices and endpoints<br />
• PCI 32-Bit 33MHz to 66 MHz<br />
‣ Forward or Reverse Bridging<br />
‣ In Production since 2005!<br />
PEX 8111<br />
PCI 32-bit, 66 MHz<br />
‣ Cost-reduced version in design now<br />
• PEX 8112 available August 2007<br />
© <strong>PLX</strong> Aug 2007 47
Example in Add-in Cards<br />
Forward Mode<br />
Reverse Mode<br />
PCI<br />
Device<br />
PCIe<br />
Endpoint<br />
PEX 8111<br />
PEX 8111<br />
© <strong>PLX</strong> Aug 2007 48
Example on Motherboard<br />
PCI Slots<br />
PCI<br />
Chipset<br />
PCI Bus<br />
Host<br />
CPU<br />
PEX 8111<br />
PCI-to-PCI Express<br />
Bridge<br />
PCI Express<br />
Add-On Slot<br />
PEX 8111<br />
Creating PCI Slots<br />
PCI Slots<br />
Providing PCI Express<br />
Host<br />
CPU<br />
Root<br />
Complex<br />
PEX 8111<br />
PCI<br />
Device<br />
© <strong>PLX</strong> Aug 2007 49
PCI Express Features<br />
‣ Compliant with PCIe 1.0a specification<br />
• Listed on PCI-SIG integrators list<br />
‣ Maximum payload size 128 Bytes<br />
‣ Interrupts transferred between ports<br />
‣ Message signal interrupts (MSI) propagates to<br />
PCI<br />
‣ PCI interrupt propagates to MSI<br />
‣ Power management<br />
‣ Supports in-band power management<br />
‣ Link power states: L0, L0s, L1, L2/3, L2, L3<br />
‣ Device power management states: D0, D3 (hot)<br />
‣ Hot Plug<br />
PEX 8111<br />
PCI 32-bit, 66MHz<br />
© <strong>PLX</strong> Aug 2007 50
PCI Features<br />
‣ PCI r3.0 compliant<br />
‣ 32-bit PCI operation up to 66 MHz<br />
‣ 64-bit addressing as master and slave<br />
‣ Memory and I/O data transfers<br />
‣ PCI power management support<br />
‣ Supports D0, D3 (hot)<br />
PEX 8111<br />
‣ Arbiter supports 4 external masters<br />
‣ Arbiter can be disabled to allow external arbiter<br />
PCI 32-bit, 66MHz<br />
© <strong>PLX</strong> Aug 2007 51
PCI Express to PCI-X Bridge<br />
‣ PCI Express to PCI-X Bridge<br />
• 4 lane PCI Express port (x1, x2, or x4 config.)<br />
• Supports Forward & Reverse modes<br />
‣ 17 x 17 mm PBGA package<br />
• No heat sink, no air flow required<br />
‣ Low power (2 watts max)<br />
‣ PCI-X<br />
• 64-/32-bit, 133/100/66 MHz PCI-X<br />
• 64-/32-bit, 66/50/33/25 MHz PCI<br />
• Arbiter supports up to 4 masters<br />
‣ PCI Express<br />
• Maximum payload size = 256B<br />
• RAS features<br />
• Polarity Reversal<br />
• Hot Plug<br />
PEX 8114<br />
© <strong>PLX</strong> Aug 2007 52
PCIe to PCI-X Bridge Example<br />
4<br />
4<br />
PEX<br />
8114<br />
PEX 8114<br />
4<br />
Host<br />
CPU<br />
Root<br />
Complex<br />
Root<br />
Complex<br />
8<br />
PEX8532<br />
PEX 8532<br />
2<br />
Native<br />
4<br />
Native<br />
1<br />
Native<br />
‣ PEX 8114 can create legacy PCI-X slots in a PCI Express System<br />
© <strong>PLX</strong> Aug 2007 53
PCI Express Features<br />
‣ Maximum payload size 256B<br />
‣ Support for polarity reversal<br />
‣ EEPROM support<br />
‣ Interrupts transferred between ports<br />
• Message signal interrupt propagates to PCI-X interrupt<br />
• PCI-X interrupt propagates to message signal interrupt<br />
‣ Power management:<br />
• Link power management states:<br />
L0, L0s, L1, L2/L3 Ready, L2, L3<br />
• Device power management states:<br />
D0, D3 HOT<br />
‣ RAS features<br />
• Hot Plug master & slave<br />
• TLP Digest support:<br />
• Poison bit and End to end CRC<br />
PEX 8114<br />
© <strong>PLX</strong> Aug 2007 54
PCI-X/PCI Bus Features<br />
‣ PCI-X r1.0b and PCI r 3.0 compliant<br />
• PCI-X operation up to 133 MHz<br />
• 64-bit/32-bit PCI operation up to 66 MHz<br />
• 64-bit addressing as master and slave<br />
• Memory and I/O data transfers<br />
• Up to 8 outstanding split PCI-X<br />
transactions<br />
‣ PCI Power Management r1.1 compliant<br />
PEX 8114<br />
• Supports D0, D3 HOT<br />
‣ Arbiter supports 4 external masters<br />
• Arbiter can be disabled to allow external<br />
arbiter<br />
© <strong>PLX</strong> Aug 2007 55
Bridge on Add-in Card<br />
Forward Mode<br />
PCI-X<br />
Device<br />
PCI-X Bus<br />
PEX 8114<br />
PCI Express<br />
Reverse Mode<br />
PCIe<br />
Endpoint<br />
PCI Express<br />
PEX 8114<br />
PCI-X Bus<br />
© <strong>PLX</strong> Aug 2007 56
AdvancedTCA with AMC<br />
PCI - X<br />
PCI-X<br />
Device<br />
Device<br />
PCI-X<br />
- X<br />
Device<br />
PEX 8114<br />
PEX P-<br />
Bridge 8114<br />
‣ 8U Form Factor<br />
‣ 2.4 times board real estate as 6U<br />
‣ Up to eight (8) mezzanine slots<br />
‣ Robust power budget exists on<br />
ATCA board<br />
PCI-X<br />
PCI- X<br />
Device<br />
Device<br />
PEX P-<br />
Bridge 8114<br />
uProc CPU<br />
PCI PCI<br />
Device Device<br />
PEX P-<br />
Bridge 8114<br />
<strong>Switch</strong><br />
© <strong>PLX</strong> Aug 2007 57
Local Bus to PCI Express Bridge<br />
‣ Generic Local to PCI Express<br />
• 32-Bit Local (up to 66MHz)<br />
• x1 PCIe<br />
‣ Local Bus Modes<br />
• Non-Multiplexed 32-Bit address/data<br />
(C Mode)<br />
• Multiplexed 32-Bit address/data<br />
(J-Mode)<br />
32-Bit Generic Local<br />
PEX 8300<br />
Series<br />
‣ Root Complex & End Point Modes<br />
‣ 2 DMA Channels<br />
‣ Available in volume production<br />
© <strong>PLX</strong> Aug 2007 58
Local Bus Bridge Road Map<br />
Local/PCI<br />
Bus Speeds<br />
64 Bits<br />
133 MHz<br />
Target (Slave)<br />
Bus Master<br />
Devices<br />
Devices<br />
64 Bits<br />
66 MHz<br />
PCI 9656<br />
66MHz Local Bus<br />
Dual DMA<br />
• Easy way to Bridge Local Bus to PCI Express<br />
• Compatible with PCI 9056<br />
• Works well with FPGAs<br />
32 Bits<br />
66MHz<br />
32 Bits<br />
33MHz<br />
PCI 9030<br />
32-Bit, 60MHz LB to<br />
32-Bit 33MHZ PCI<br />
32-Bit 33MHZ PCI PCI 9054<br />
PCI 9052<br />
40MHz Local Bus<br />
ISA Compatible<br />
PCI 9056<br />
66MHz Local Bus<br />
Dual DMA<br />
32-Bit, 50MHz LB to<br />
32-Bit, 33MHz PCI<br />
PEX 8311<br />
32-Bit, 66MHz Local<br />
Bus to x1 PCIe<br />
Shipping Now<br />
In Development<br />
Planned/Concept<br />
2005 & Before 2006<br />
© <strong>PLX</strong> Aug 2007 59
PEX 8311 Overview<br />
‣ Generic Local bus to PCI Express Bridge<br />
• Available in volume production<br />
‣ Generic Local Bus<br />
• 32-Bit, Up to 66MHz<br />
• Multiplexed (C-Mode) & Non-Multiplex (J-Mode)<br />
• 2 DMA Channels<br />
• Register Backward compatible with<br />
<strong>PLX</strong> PCI 9056, 9656 & 9054<br />
• Local Bus protocol backward compatible with<br />
<strong>PLX</strong> PCI 9056 & 9656 up to 66MHz<br />
PEX 8311<br />
32-bit / 66MHz<br />
Local Bus<br />
‣ PCI Express<br />
• x1 Lane PCIe<br />
• Integrated SerDes<br />
• Rev 1.0a compliant<br />
• Maximum payload size: 128B<br />
• 1 Virtual Channel<br />
• Hot plug support in EndPoint mode<br />
© <strong>PLX</strong> Aug 2007 60
System Controller Card<br />
EEPROM<br />
SRAM<br />
FPGA<br />
DSP<br />
Proprietary<br />
ASIC<br />
Local<br />
CPU<br />
PEX 8311<br />
Generic Local Bus<br />
‣ Root Complex mode<br />
‣ Control Path implementation: x1 lane<br />
‣ Interface to <strong>Switch</strong>ing Fabric cards & I/O<br />
Cards<br />
‣ Generic interface to local bus devices<br />
‣ Backward compatible to PCI 9xxx family<br />
‣ 2 Gbps generic local bus/PCIe link<br />
© <strong>PLX</strong> Aug 2007 61
Industrial Control Video Monitor<br />
FPGA<br />
PEX 8311<br />
CPU<br />
SDRAM<br />
FPGA<br />
PEX 8311<br />
PEX 8532<br />
Host<br />
FPGA<br />
FPGA<br />
PEX 8311<br />
PEX 8311<br />
‣ x1 links<br />
‣ 2Gbps local bus<br />
throughput<br />
‣ More sources per board<br />
driving bandwidth<br />
‣ Unidirectional traffic<br />
‣ 1 DMA sufficient<br />
‣ Scatter/gather manages<br />
multiple flows<br />
© <strong>PLX</strong> Aug 2007 62
End of Presentation<br />
Thank You<br />
www.plxtech.com
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