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CompactPCI and AdvancedTCA Systems - OpenSystems Media

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P R O D U C T G U I D E<br />

P A C K A G I N G<br />

legacy PXI boards, where the P2 connector<br />

is replaced with the eHM connector,<br />

can be used in the hybrid slot.<br />

Switch slot<br />

This slot provides fan-out to drive all of<br />

the slot types. It contains a power connector<br />

<strong>and</strong> a large number of ADF connectors<br />

to accommodate all of the signals coming<br />

in from each slot. The 3U sized switch<br />

slot contains three ADF connectors <strong>and</strong><br />

can connect up to seven slots with x4<br />

ports. The 6U switch slot contains eight<br />

ADF connectors <strong>and</strong> can connect up to<br />

19 slots with x4 ports. Dual switch slots<br />

can be included in a backplane to provide<br />

redundant ports to each slot.<br />

Hybrid systems:<br />

Compatibility with existing boards<br />

Over the next several years, <strong>CompactPCI</strong>e<br />

systems will likely include a mixture of<br />

legacy slots, hybrid slots, <strong>and</strong> new PCIe<br />

slots. This will enable designers to mix<br />

<strong>and</strong> match older boards with newer highperformance<br />

boards. Over time, more <strong>and</strong><br />

more of the slots are expected to migrate<br />

to the PCIe st<strong>and</strong>ard.<br />

CPU modules will likely be the first modules<br />

to migrate to PCIe, given the rapid<br />

CPU board design turnover rates <strong>and</strong><br />

because newer chipsets have PCIe ports.<br />

Generic I/O boards such as Ethernet,<br />

video, <strong>and</strong> disk controller boards will<br />

migrate to PCIe next. Again, the underlying<br />

components will drive this transition.<br />

The latest components for these functions<br />

are now coming out, <strong>and</strong> they have PCIe<br />

ports coming directly out of the chip.<br />

Thus, new designs using the latest components<br />

will utilize PCIe.<br />

The last boards likely to migrate over to<br />

PCIe will likely be custom or low-volume<br />

specialty I/O boards. Some designers may<br />

choose the “easy” way out <strong>and</strong> add a PCIto-PCIe<br />

bridge onto these boards. This<br />

minimizes the engineering effort involved<br />

in getting a legacy board to work in a pure<br />

PCIe environment. Although easier, this<br />

approach does not achieve the performance<br />

advantages of PCIe, since the transfers<br />

end up going though legacy PCI <strong>and</strong><br />

are throttled by its lower performance.<br />

Future performance increases:<br />

Gen 2 timing<br />

The PCI-SIG has announced the next<br />

generation PCIe bus timing. In PCIe 2.0,<br />

the data transfer rate will double from<br />

2.5 gigabits per second to 5.0 gigabits per<br />

second. Components with the new Gen 2<br />

timing are expected to become available<br />

in early 2007, with systems appearing<br />

shortly thereafter.<br />

The technical subcommittee that defined<br />

<strong>CompactPCI</strong>e took the future Gen 2 timing<br />

into consideration when defining the<br />

specification. All simulations for the proposed<br />

backplane <strong>and</strong> connectors occured<br />

at frequencies beyond Gen 2, providing<br />

confidence that the upgrade path will be<br />

straightforward.<br />

The specification is defined such that<br />

Gen 2 boards will be compatible with the<br />

current backplanes <strong>and</strong> boards. In a mix<strong>and</strong>-match<br />

system, each bus interface<br />

will auto-negotiate with its associated<br />

interface. They both will begin communications<br />

at the slower 2.5 gibabits per second<br />

speed <strong>and</strong> then let each other know<br />

if they have the capability to move to<br />

5.0 gigabits per second. Due to the pointto-point<br />

nature of PCIe, the presence of<br />

Gen 1 boards will not slow down highspeed<br />

Gen 2 boards in the same system.<br />

This technique will allow systems to take<br />

advantage of even higher bus performance,<br />

while maintaining total hardware<br />

<strong>and</strong> software compatibility.<br />

Steve Cooper is president <strong>and</strong> CEO of<br />

One Stop <strong>Systems</strong>, <strong>and</strong> has more than<br />

18 years of sales, marketing, <strong>and</strong> general<br />

management experience in the st<strong>and</strong>ard<br />

bus <strong>and</strong> board marketplace. He began<br />

his career with Intel, where he became a<br />

technical spokesman for the concept of<br />

board-level open bus st<strong>and</strong>ards <strong>and</strong> the<br />

Multibus <strong>and</strong> Multibus II architectures.<br />

Steve then joined RadiSys, a company<br />

specializing in embedded PC-compatible<br />

computers. He also served as vice president<br />

of sales <strong>and</strong> marketing, <strong>and</strong> later<br />

president <strong>and</strong> chief operating officer, at<br />

I-Bus. Most recently, Steve was president<br />

<strong>and</strong> chief operating officer for<br />

SBS Technologies. He holds a BSEE<br />

degree from the University of California,<br />

Santa Barbara.<br />

To learn more, contact Steve at:<br />

One Stop <strong>Systems</strong><br />

735 South Vinewood St.<br />

Escondido, CA 92029<br />

Tel: 760-745-9883<br />

Fax: 760-745-9824<br />

E-mail: scooper@onestopsystems.com<br />

Website: www.onestopsystems.com<br />

38 / <strong>CompactPCI</strong> <strong>and</strong> <strong>AdvancedTCA</strong> <strong>Systems</strong> / September 2005

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