AD7760 : Tips & Solutions to Aid Optimum Performance - dreamm
AD7760 : Tips & Solutions to Aid Optimum Performance - dreamm
AD7760 : Tips & Solutions to Aid Optimum Performance - dreamm
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The World Leader in High <strong>Performance</strong> Signal Processing <strong>Solutions</strong><br />
<strong>AD7760</strong> : <strong>Tips</strong> & <strong>Solutions</strong> <strong>to</strong><br />
<strong>Aid</strong> <strong>Optimum</strong> <strong>Performance</strong><br />
Oc<strong>to</strong>ber 2005
<strong>AD7760</strong> Agenda<br />
Reference Voltage Filtering<br />
• Optimisation for <strong>AD7760</strong> DC operation<br />
On-chip Amplifier<br />
Supply Decoupling<br />
• Left Hand Side Supply & Reference Supply<br />
Clock Considerations<br />
Low Power Mode<br />
<strong>AD7760</strong>/2 updated performance specifications
Reference Voltage Filtering<br />
Low noise reference source<br />
• Recommended reference sources:<br />
ADR431 (2.5 V)<br />
ADR434 (4.096 V)<br />
Decouple and Filter reference supply<br />
• 100Ω resis<strong>to</strong>r and 100µF capaci<strong>to</strong>r filter noise on the reference output.<br />
• Decouple with 10nF capaci<strong>to</strong>r placed as close as possible <strong>to</strong> the Vref pin.<br />
• Optimised for use in AC applications in Normal power mode.<br />
Reference Voltage Filtering and Decoupling<br />
U3<br />
12V<br />
C15<br />
+<br />
C9<br />
10µF<br />
100nF<br />
2<br />
VIN<br />
ADR434<br />
(4.096 V)<br />
VOUT<br />
GND<br />
6<br />
C10<br />
100nF<br />
R30<br />
100Ω<br />
C11<br />
+<br />
100µF<br />
10Ω<br />
R17<br />
C46<br />
10nF<br />
Vref<br />
<strong>AD7760</strong><br />
Pin 10<br />
4
Reference Voltage Filtering Adjustment for<br />
Use in DC Applications<br />
Reference configuration in <strong>AD7760</strong> Datasheet (Figure 45)<br />
is optimised for AC operation<br />
For DC applications, removing the 100Ω resis<strong>to</strong>r in the<br />
reference filter network is advised<br />
• Current drawn from the reference has a slight code dependence<br />
noticeable with fixed DC input voltages<br />
• Current drawn is higher for ADC inputs which result in codes near<br />
FS and near 0 than current drawn for mid-scale codes<br />
• Why? Ohms law! Voltage drop across resis<strong>to</strong>r due <strong>to</strong> increased<br />
current reduces reference voltage at pin of <strong>AD7760</strong> causing code<br />
variation<br />
• The variation in the output code is more pronounced at high clock<br />
speeds
On-Board Differential Amplifier <strong>Tips</strong><br />
Configure Amplifier as 1 st Order Anti-alias filter<br />
Layout<br />
• Place all components on the same PCB layer<br />
• Symmetrical layout of Components<br />
Component Matching<br />
• 1 st order filter elements must be matched (R IN<br />
, R FB<br />
, C FB<br />
, R M<br />
)<br />
• Reduces dis<strong>to</strong>rtion of signal output by the Amplifier<br />
• Tolerance of 0.1% or better is required for these components<br />
Particular care should be taken in matching the resis<strong>to</strong>r values (CMRR)
Supply Decoupling<br />
Extremely important <strong>to</strong> the performance of the AD776x parts<br />
All supplies must be connected <strong>to</strong> the relevant pin through a<br />
ferrite bead (See circled red in Diagram)<br />
• Used <strong>to</strong> dampen “ringing” in the supply voltages<br />
• 0603 Size (Wurth Electronics 74279266)<br />
• 0805 Size (Meggitt Sigma BMB-2A-0600R-S2)<br />
Decouple all supplies through capaci<strong>to</strong>r <strong>to</strong> correct ground pin<br />
• Use 100nF, 0603 case size, X7R dielectric capaci<strong>to</strong>r<br />
AVDD2<br />
AVDD1<br />
AVDD3<br />
VDRIVE<br />
DVDD<br />
L1<br />
L3<br />
L5<br />
L11<br />
L6<br />
L7<br />
L12<br />
L8<br />
Pin 4<br />
(RHS)<br />
Pin 15<br />
(VBIAS)<br />
Pin 5<br />
(VMOD1)<br />
Pin 33<br />
(VMOD2)<br />
Pin 24<br />
(VDIF1)<br />
Pin 44<br />
(VDRV1)<br />
Pin 4<br />
(VDRV2)<br />
Pin 41<br />
(DVDD)<br />
C48<br />
100nF<br />
C50<br />
100nF<br />
C52<br />
100nF<br />
C53<br />
100nF<br />
C54<br />
100nF<br />
C56<br />
100nF<br />
C57<br />
100nF<br />
C58<br />
100nF
Supply Decoupling (contd..)<br />
Left Hand Side & Reference supplies<br />
are particularly sensitive <strong>to</strong> ringing<br />
• Use Ferrite Beads in both supply lines<br />
Left Hand Side supply (Pins 14 & 27)<br />
• Decouple Pin 14 <strong>to</strong> gnd using 100nF<br />
cap also connect <strong>to</strong> Pin 27 through a<br />
15nH induc<strong>to</strong>r<br />
• Suppresses THD issues<br />
• No 100nF decoupling capaci<strong>to</strong>r needed<br />
for Pin 27<br />
Pin 14<br />
(LHS)<br />
AVDD2<br />
L6<br />
C54<br />
100nF<br />
AVDD4<br />
Ferrite Bead<br />
Left Hand Side<br />
Decoupling Arrangement<br />
L9<br />
15nH<br />
Pin 27<br />
Reference Supply<br />
Decoupling Arrangement<br />
Reference Supply (Pin 12)<br />
• Insert 10Ω resis<strong>to</strong>r between<br />
10nF capaci<strong>to</strong>r and relevant<br />
ground pin (Pin 11)<br />
Pin 12<br />
(VBUF)<br />
L4<br />
C54<br />
10nF<br />
R38<br />
10 Ω<br />
Ferrite Bead<br />
Combination of<br />
10nF Decoupling<br />
Capaci<strong>to</strong>r required<br />
&<br />
10Ω Resis<strong>to</strong>r
Clock Considerations<br />
MCLK signal must be buffered before input <strong>to</strong> AD776x<br />
• Degradation in performance of <strong>AD7760</strong> when applying MCLK<br />
signal directly from its source <strong>to</strong> the MCLK pin (Pin 3, <strong>AD7760</strong>)<br />
• Buffering the MCLK signal improved the quality of the edges<br />
<strong>Aid</strong>s performance of internal clock divider<br />
• Recommended buffer - NC7S08 (Fairchild Semiconduc<strong>to</strong>r)<br />
2 I/P AND gate, Connect MCLK signal <strong>to</strong> both inputs<br />
Minimise trace length from buffer output <strong>to</strong> MCLK pin<br />
MCLK Input Amplitude<br />
• <strong>Optimum</strong> performance of AD776x is achieved using a 5V MCLK<br />
Clock edges are fastest with 5V MCLK implementation
Optimising AD776x External Circuitry for<br />
Low Power Mode<br />
<br />
<br />
Datasheet Circuitry is<br />
optimised for Normal Mode<br />
Modifications:<br />
1. Modify resistance value<br />
between Diff Amp &<br />
Modula<strong>to</strong>r I/Ps<br />
Rm value should be increased<br />
from 18Ω <strong>to</strong> 33Ω for Low power<br />
mode<br />
Resolves settling issues seen in<br />
Low power mode<br />
2. Modify Reference Voltage<br />
circuitry<br />
Replace 10Ω resis<strong>to</strong>r with 22nH<br />
induc<strong>to</strong>r for Low Power mode<br />
(2)<br />
2<br />
VIN<br />
(1)<br />
U3<br />
ADR434<br />
(4.096 V)<br />
6<br />
VOUT<br />
GND<br />
4<br />
Reference Voltage Filtering and Decoupling<br />
Low Power Mode<br />
C10<br />
100nF<br />
R30<br />
100 Ω<br />
C11<br />
+<br />
100µF<br />
22nH<br />
Increase R M <strong>to</strong> 33Ohms<br />
For Low Power Mode Operation<br />
Optimising Reference<br />
Circuitry for Low Power Mode<br />
C46<br />
10nF<br />
Vref<br />
<strong>AD7760</strong><br />
Pin 10
<strong>AD7760</strong> Updated <strong>Performance</strong> Figures<br />
<strong>AD7760</strong><br />
Dynamic Range<br />
78Khz<br />
120 dB<br />
Output Data Rate (40MHz MCLK)<br />
625Khz 2.5Mhz<br />
109 dB 100 dB<br />
SNR<br />
112 dB<br />
107 dB<br />
100 dB<br />
SFDR<br />
126 dBc<br />
120 dBc<br />
120 dBc<br />
THD<br />
-105 dB<br />
-105 dB<br />
-103 dB<br />
Resolution<br />
24-Bit<br />
Max<br />
Throughput<br />
2.5 MSPS<br />
Channel No.<br />
1<br />
Interface<br />
Parallel<br />
Power Supply<br />
5V<br />
Package<br />
64-TQFP
AD7762 Updated <strong>Performance</strong> Figures<br />
AD7762<br />
Dynamic Range<br />
78Khz<br />
120 dB<br />
Output Data Rate (40MHz MCLK)<br />
312Khz 625Khz<br />
114 dB 109 dB<br />
SNR<br />
112 dB<br />
109 dB<br />
107 dB<br />
SFDR<br />
126 dBc<br />
126 dBc<br />
120 dBc<br />
THD<br />
-105 dB<br />
-105 dB<br />
-108 dB<br />
Resolution<br />
24-Bit<br />
Max<br />
Throughput<br />
625 kSPS<br />
Channel No.<br />
1<br />
Interface<br />
Parallel<br />
Power Supply<br />
5V<br />
Package<br />
64-TQFP
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