software engineering - Reiner Hartenstein

keynote
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
1
reiner@hartenstein.de
4 December 2009
10 Sep 2009, Stockholm, Sweden
Reiner
Hartenstein
The Impact of
Reconfigurable Computing on
Manycore Programming Trends
reiner@hartenstein.de
9:15 – 10:00
1
Teaching for Change: an early martyr
„Turing is irrelevant“
punished for blasphemy?
D. L. Parnas (keynote):
"Teaching for Change“;
10 th Conf. Softw. Engineering Education
and Training (CSEET '97)
http://www.sigsoft.org/SEN/parnas.html
The von Neumann model
is the emulation of a tape machine
„The von Neumann syndrome“:
coined ~ a decade later
(mimicking tape
on RAM)
Prof. C.V.
Ramamoorthy,
(UC Berkeley),
SDPS 2006,
San Diego, CA
Critique of von Neumann is not new:
Peter G.
Neumann
Dijkstra 1968: The Goto considered harmful Peter G. Neumann 1985-2003: 216x
http://hartenstein.de
Brad Cox 1990:
“Inside
Planning
Risks“
(18 years inside back cover
R. Hartenstein, © 2009, G. Koch 1975: The universal Bus considered harmful the Software Industrial Revolution
reiner@hartenstein.de
of Comm_ACM)
Backus 1978: Can programming be liberated from the von Neumann style? L. Savain 2006:
Arvind et al., 1983: A critique of Multiprocessing the von Neumann 2 Style Why Software is bad …
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
2
reiner@hartenstein.de
4 December 2009
Outline (1)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
3
Impact of the
von Neumann
Syndrome
Dig more coal --
the PCs are coming
Peter W. Huber,
Mark P. Mills,
05.31.99
http://www.forbes.com/forbes/1999/0531/6311070a.html
[1989 from a student at Kaiserslautern]
http://hartenstein.de
© 2009,
reiner@hartenstein.de
4
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Production (%)
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
3
reiner@hartenstein.de
4 December 2009
never run out of energy?
2007:
80% crude oil coming from decline fields
natural gas: similar situation
„6 more Saudi Arabias needed
for demand predicted for 2030“
~ 55 %
http://hartenstein.de
© 2009,
reiner@hartenstein.de
> 30 %
[Fatih Birol, Chief Economist IEA]. https://www.theoildrum.com/
100
typical oil field operation
0
5
coal
hydro
nuclear
gas
oil
5
Power consumption by internet:
x30 til 2030 if trends continue
G. Fettweis, E. Zimmermann: ICT Energy Consumption - Trends
and Challenges; WPMC'08, Lapland, Finland, 8 –11 Sep 2008
Server Farms
at banks of the Columbia river:
[Randy Katz: IEEE Spectrum, Febr. 2009]
at Dallas
Quincy
each 6500 m 2
WASHINGTON
at Quincy, size: 10
Am. football fields
48 MW
power for
40,000 homes
Dalles
Boardman
OREGON
the electricity bill is a key issue
http://hartenstein.de
© 2009,
reiner@hartenstein.de
6
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
4
reiner@hartenstein.de
4 December 2009
(subject
of my talk)
Power Consumption of Computers
... has become an industry-wide issue:
incremental improvements are on track,
but „we may ultimately need
revolutionary new solutions“ [Horst Simon, LBNL, Berkeley]
Current trends will lead to
unaffordable future operation
cost of our cyber infrastructure
Energy cost may overtake
IT equipment cost
in the near future
[Albert
Zomaya]
http://hartenstein.de
© 2009,
reiner@hartenstein.de
7
Outline (2)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
8
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
5
reiner@hartenstein.de
4 December 2009
Single-core
approach:
10 9
Software Performance
10 8
10 7
free ride on
10 Moore„s Law
6
10 the burden of
5
software performance is
the task of chip designers*
10 3
10 4
*) M-&-Ccreated
year population
70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 04 06 08
http://hartenstein.de
© 2009,
reiner@hartenstein.de
9
Rapid VLSI Design Education Revolution
1980 - 1983
E.I.S.
project
(Heinz
Riesenhuber)
The incubator
of the free ride
on Moore‘s law
massive
funding:
DARPA; NSF; many
national governments;
European Union …
Created the missing
designer population
The most http://hartenstein.de effective
project © 2009,
in the
reiner@hartenstein.de
history of modern
[Foto: GMD]
computer science 10
10
10 Carver
Mead
Lynn
Conway
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
6
reiner@hartenstein.de
4 December 2009
The End of Moore„s Law
10 9
10 8
10 7
10 6
the end of the
single-core era
stop in
2005
soon:
the 20
nm wall
The end of
Moore„s Law
10 5
10 4
traditional instruction-based computing
is running out of steam
[DAC’09 special session: Computation in the Post-Turing Era]
year
10
70 3
72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 04 06 08
http://hartenstein.de
© 2009,
reiner@hartenstein.de
11
Growth beyond Moore„s Law?
relative performance
10 13
10 12
10 11
10 10
10 9
10 8
10 7
10 6
10 5
the end of the
single-core era
10 4
year
10 3 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
http://hartenstein.de
© 2009,
reiner@hartenstein.de
the key issue:
processor cores
number of transistors
doubles every 2 years
12
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

egin of the
multicore era
begin of the
multicore era
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
7
reiner@hartenstein.de
4 December 2009
Multimedia in the Multicore Era
relative performance
Multimedia
Performance Needs
application performance
needs up to:
Audio
800 MIPS
Graphics
11 GOPS
Video
160 GOPS
Digital TV
900 GOPS
[Pierre Paulin, MPSoC’09]
year
94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
http://hartenstein.de
© 2009,
reiner@hartenstein.de
13
13
Broadband in the Multicore Era
relative performance
[courtesy E. Sanchez]
MIPS
needed
performance
growing
faster than
Moore‘s law
next
GSM GPRS EDGE UMTS standard year
94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
http://hartenstein.de
© 2009,
reiner@hartenstein.de
14
14
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
8
reiner@hartenstein.de
4 December 2009
ICT is at an inflection point
handheld & living room commercially more important
than the comparatively small PC market.
„Future prosperity depends on network capacity,
..., efficient pricing, and flexible platforms“
Cheap Revolution:
affordable broadband
& software performance
MIPS
[courtesy E. Sanchez]
requirement
growing
faster than
Moore‘s law
„Broadband is significant at the inflection point,
prompting major market governance changes“
Senior Counselor
to the U.S. Trade
Representative
(USTR) on strategy
and negotiations.
Cowhey„s & Aronson„s Law:
massive funding needed
http://hartenstein.de
© 2009,
reiner@hartenstein.de
15
Funding market governance changes
RUS Broadband Initiatives Program (BIP)
NTIA Broadband Technology Opportunities Program (BTOP).
other
sources
DARPA ?
ARPA-E ?
EU-FP7 ?
EFRCEs ?
Energy Frontier
Research Centers 777 bio $
http://www.broadbandusa.gov/
The Recovery Act:
$7.2 billion
http://hartenstein.de
© 2009,
reiner@hartenstein.de
16
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
9
reiner@hartenstein.de
4 December 2009
Outline (3)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
17
Multicore has been around for decades
Dead (Super)Computer Society [Gordon Bell, keynote, ISCA 2000]
•ACRI
•Alliant
•American Supercomputer
•Ametek
•Applied Dynamics
•Astronautics
•BBN
•CDC
•Convex
•Cray Computer
•Cray Research
•Culler-Harris
•Culler Scientific
•Cydrome
http://hartenstein.de
© 2009,
reiner@hartenstein.de
•Dana/Ardent/ Stellar/Stardent
•DAPP
•Denelcor
•Elexsi
•ETA Systems
•Evans and Sutherland
Computer
•Floating Point Systems
•Galaxy YH-1
•Goodyear Aerospace MPP
•Gould NPL
•Guiltech
•ICL
•Intel Scientific Computers
•International Parallel
Machines
•Kendall Square Research
•Key Computer Laboratories
18
only 2 or 3
successes
•MasPar
•Meiko
•Multiflow
•Myrias
•Numerix
•Prisma
•Tera
•Thinking Machines
•Saxpy
•Scientific Computer
•Systems (SCS)
•Soviet Supercomputers
•Supertek
most in
1985-1995
- mainly
research
•Supercomputer Systems
•Suprenum
•Vitesse Electronics
the single core sequential mind set was the winner
18
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Speedup-Factor
Speedup-Factor
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
10
reiner@hartenstein.de
4 December 2009
?
Speed-up factors
*
by GPGPUs (1)
[Michael Garland, NVIDIA Research: Parallel Computing
on Manycore GPUs; IPDPS, Rome, Italy, June 25-29, 2009]
The power efficiency is disputable
this hardware can only be
used only in certain ways.
?
such speed-ups by GPGPUs
only for embarrassingly
parallel applications
effective only at problems
that can be solved using
stream processing.
http://hartenstein.de
© 2009,
reiner@hartenstein.de
10 3
10 2
10 1
10 0
streams provide data parallelism
Jan
2007
July
2007
19
Jan
2008
19
(up to ~150 x)
July
2008
130
100
50
30
18
149
146
47
36
20
Jan
2009
July
2009
Numerics
Imaging
Bioinformatics
Video
Jan
2010
*) migration from x86 singlecore
*
Speed-up factors by GPGPUs (2)
NVIDIA
GeForce
GTX
stream
processor
cores
Compute Unified Device
Architecture (CUDA),
accelerates BLAS
libraries (Basic Linear
Algebra Subroutines)
http://hartenstein.de
Less flexible
© 2009,
reiner@hartenstein.de
than FPGAs.
minium
power supply
recommended
275 240 650–680 watt
295 480 650–680 watt
(GPGPU tool development
years earlier than f. x86)
10 3
http://www.nvidia.co.uk/object/cuda_home_uk.html#state=home
CUDA ZONE pages [NVIDIA Corp.]:
non-reviewed CUDA user submissions
675
470
340 500
250
270 327 420
169 270
150 260 169 170
138 150
100 109 100
100
100
120 172
100
100 100
100
55
100
90
60
90
55
77
75
50
30
5055
60
50 50 60
50
50
36
50 40
35
29
35
40 30 50 39 50
35
35
35
32
27
26 20 30 26
31
29
15 16 20 20 25 23
17 20
12
15 13 16
15
13
15
10
10
12
10 10 10
10 10
10 9
10
7
10 9
9 7 8
5
5 5
5 5
4
8
4
4 . 3
4
3 . 5
4
3 3
3 5
2 2 2
1 . 3
10 2
10 0
Jan
2007
July
2007
Jan
2008
EDA
20
July
2008
Intel Core2 Quad (desktop PCs): 4 cores
Intel Xeon "Nehalem-EX" for servers: 8 cores
(up to ~600 x)
34
oil &
gas
Jan
2009
20
July
2009
Jan
2010
Astrophysics
Bioinformatics
CFD Computational
Fluid Dyamics
Cryptography
DCC
10 1 DSP
2 Imaging
Digital
Content
Creation
Digital Signal
Processing
Graphics
Numerics
Video & Audio
*) migration from x86 singlecore
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

egin of the
multicore era
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
11
reiner@hartenstein.de
4 December 2009
relative
performance
Growth by Multicore
94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
year
http://hartenstein.de
© 2009,
reiner@hartenstein.de
21
21
Hastily knitted
compilers for the
heavy lifting?
new types
of bugs
introduced
e. g. automatically
parallelizing
compilation via
multi-threading,
and many other
ad-hoc solutions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
John
Hennessy:
“wait for current
generation of
programmers to die
off and be replaced
by programmers
widespread confusion and brought up on the
competing claims, „I would be new paradigm?”
panicked if I were in industry“
[Jim Turley]
22
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
12
reiner@hartenstein.de
4 December 2009
50 years to die off
„software engineering“:
the term appeared the late 50ies
Max Planck:
Replacement of false doctrines
by new insights needs 50 years
waiting for not only old professors
but also their scholars to die off.
http://hartenstein.de
© 2009,
reiner@hartenstein.de
23
Outline (4)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
24
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

egin of the
multicore era
Speedup-Factor
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
13
reiner@hartenstein.de
4 December 2009
relative performance
Growth in the Multicore Era
94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
year
http://hartenstein.de
© 2009,
reiner@hartenstein.de
25
Speed-up
factors
obtained
by Software
to Configware
migration
(up to ~30,000x)
vs. GPU: almost 50x
http://hartenstein.de
© 2009,
reiner@hartenstein.de
(200x)
2 orders of magnitude
10 6
10 3
“... design techniques will evolve, by
necessity, to satisfy the demands of
reconfigurable hardware and software
programmability”. J. R. Rattner, DAC 2008
intel supports direct front
side bus access by FPGAs
10 0
real-time
face detection
6000
GRAPE
by FPGA:
Image processing,
Pattern matching,
Multimedia
26
DSP and
wireless
video-rate
stereo vision
pattern 730
recognition
900
52
BLAST
40
26
Reed-Solomon
Decoding 2400
MAC
1000
400
288
SPIHT wavelet-based
image compression 457
FFT
88
protein
identification
20 Astrophysics
DES breaking
Viterbi Decoding
Smith-Waterman
pattern matching
100
DNA & protein
sequencing
crypto
1000
8723
molecular
dynamics
simulation
28514
3000
CT imaging
CUDA
ZONE
Bioinformatics
~50x
(200x)
Garland
IPDPS‘09
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

0.5xMOPS/MHz/Billion Transistors
SPECfp2000/MHz/Billion Transistors
Speedup-Factor
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
14
reiner@hartenstein.de
4 December 2009
10 6 Speedup-
Factor
Grid-based DRC*
(„fair comparizon“)
15000
Grid-based DRC:
2000
no FPGA: DPLA
on MoM by TU-KL*
10 3
Lee Routing
160
(DPLA by TU-KL*)
39.4
2-D FIR filter (no
FPGA: DPLA by TU-KL*)
fabricated by E.I.S.
Multi University
Project
http://hartenstein.de
©
*)
2009,
TU Kaiserslautern
reiner@hartenstein.de
10 0
1985 1990
10 6
+ Pre-FPGA solutions
10 3
1984: 1 DPLA
replaced 256
FPGAs
10 0
Image processing,
Pattern matching,
Multimedia
real-time
face detection
6000
GRAPE
27
DSP and
wireless
video-rate
stereo vision
pattern 730
recognition
900
52
BLAST
40
27
Reed-Solomon
Decoding 2400
MAC
1000
400
288
SPIHT wavelet-based
image compression 457
FFT
88
protein
identification
20 Astrophysics
DES breaking
crypto
1000
Viterbi Decoding
Smith-Waterman
pattern matching
100
8723
molecular
dynamics
simulation
28514
DNA & protein
sequencing
3000
CT imaging
Bioinformatics
Benchmarks: Moore‘s
law does not indicate
microprocessor MIPS
200
175
150
125
100
75
50
1996
420
[BWRC, UC Berkeley, 2004]
25
HP
0
1990 1995 2000
Software vs. FPGA
46
relative performance
10 5
10 4
10 3
10 2
10 1
?
!
year
10 0 96 98 00 02 04 06 08 10
http://hartenstein.de
© 2009,
reiner@hartenstein.de
28
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Speedup-Factor
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
15
reiner@hartenstein.de
4 December 2009
Moore‟s law not applicable to all aspects
For multicore*:
the Law of More …
…with drastically declining
programmer productivity
*) number of cores doubles every 2 years
http://hartenstein.de
© 2009,
reiner@hartenstein.de
29
Software
vs. FPGA
(2)
Massive
Energy Saving
factors: ~10%
of speedup factor
http://hartenstein.de
© 2009,
reiner@hartenstein.de
10 6
10 3
10 0
Image processing,
Pattern matching,
Multimedia
real-time
face detection
6000
GRAPE
30
DSP and
wireless
video-rate
stereo vision
pattern 730
recognition
900
52
BLAST
40
30
Reed-Solomon
Decoding 2400
MAC
1000
400
288
SPIHT wavelet-based
image compression 457
FFT
88
protein
identification
20 Astrophysics
DES breaking
crypto
1000
Viterbi Decoding
Smith-Waterman
pattern matching
100
molecular
dynamics
simulation
28514
DNA & protein
sequencing
8723
3000
CT imaging
Bioinformatics
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
16
reiner@hartenstein.de
4 December 2009
RC*: Demonstrating the intensive Impact
Tarek
El-Ghazawi
[Tarek El-Ghazawi et al.: IEEE COMPUTER, Febr. 2008]
SGI Altix 4700 with RC 100 RASC compared to Beowulf cluster
Application
Speed-up
factor
Savings
Power Cost Size
DNA and Protein
sequencing 8723 779 22 253
DES breaking 28514 3439 96 1116
much less memory and bandwidth needed
*) RC = Reconfigurable Computing
massively
saving energy
much less
equipment
needed
http://hartenstein.de
© 2009,
reiner@hartenstein.de
31
31
Why such Speed-up Factors ...
... with FPGAs: a much worse technology !
massive wiring overhead
+ massive reconfigurability overhead
+ routing congestion growing with FPGA size
The „Reconfigurable Computing Paradox“
main reason: no von Neumann Syndrome!
more recently also: more „platform FPGAs“
http://hartenstein.de
© 2009,
reiner@hartenstein.de
32
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

end of the
singlecore era
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
17
reiner@hartenstein.de
4 December 2009
„RC“ =
Reconfigurable
Computing
RC versus Multicore
RC: speed-up often higher
by orders of magnitude
Sure !
RC: energy-efficiency often higher:
very much, or, by orders of magnitude ?
this is the
silver bullet
We need both: Multicore and RC
Sure !
Multicore:
legacy software,
control-intensive
applications, etc.
http://hartenstein.de
© 2009,
reiner@hartenstein.de
33
For a Booming Multicore Era
relative performance
94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
von-Neumann-only http://hartenstein.de
is not the silver bullet
Reconfigurable
© 2009,
reiner@hartenstein.de
Computing is indispensable!
34
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden
34
year

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
18
reiner@hartenstein.de
4 December 2009
Outline (5)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
35
CPU-centric
flat world
(Aristotelian model)
typical programmer
qualification:
sequential-only
mind set –
CPU-“centric“ but no
hardware know-how
(kind of tunnel view)
This
Software-centric
world model
is obsolete
http://hartenstein.de
© 2009,
reiner@hartenstein.de
36
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
19
reiner@hartenstein.de
4 December 2009
Machine Model of the Mainframe Era
Machine
model
resources
programming
property source
property
sequencer
programming source
state
register
CPU hardwired - programmable Software
(instruction streams)
program
counter
http://hartenstein.de
© 2009,
reiner@hartenstein.de
37
F. L. Bauer
40 years Software Crisis
Wirth„s Law [Niklaus Wirth]
“software is slowing faster
than hardware is accelerating“
Oct 1957
The Economist: Nov 19th 1955
Nathan Myhrvold
Software critics is not new:
Nathan‟s Law: Software is a gas.
It expands to fill its container ...
… until being limited by Moore’s Law
[& Kryder’s Law]
[Cyril Northcote Parkinson]
In 1955, Parkinson could not have
foreseen the impact of software.
formula: bureaucracy growth independent of actual work to be done
F. L. Bauer 1968, coined the term „Software Crisis“
http://hartenstein.de
N. N. © 1995: 2009, THE STANDISH GROUP REPORT
reiner@hartenstein.de
Robert N. Charette 2005: Why Software Fails; IEEE Spectrum, Sep 2005
Anthony Berglas 2008: Why it is Important that Software 38 Projects Fail
Peter G. Neumann 1985-2003:
216x “Inside Risks“(18 years inside back
cover of Comm_ACM)
L. Savain 2006:
Why Software is bad
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
20
reiner@hartenstein.de
4 December 2009
“Software”
the uglyness
of this term
stands for extremely
memory-cycle-hungry instruction streams
Patterson‟s Law:
bandwidth gap grows 50% / year
Dave has reached >1000x
Patterson
“The Memory Wall”
coined by Sally McKee (& co-author)
The von Neumann
Syndrome:
C.V.
Ramamoorthy
from earlier talks:
overhead piles up to code sizes
of astronomic dimensions
datastream
parallelism
from earlier talks:
instruction stream
parallelism
http://hartenstein.de
© 2009,
reiner@hartenstein.de
stolen from Bob Colwell
memory
wall,
caches,
...
data meet PU
39
Machine Model of the PC Era
Machine
model
resources
property
programming
source
property
sequencer
programming source
ASIC
accelerator hardwired - hardwired -
CPU hardwired - programmable Software
(instruction streams)
state
register
program
counter
http://hartenstein.de
© 2009,
reiner@hartenstein.de
“the tail is
wagging
the dog“
Application-Specific Integrated Circuit &
other accelerators: e.g. graphics processor
[ ]
ISIS 1997
Austin, TX
40
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
21
reiner@hartenstein.de
4 December 2009
Thomas S. Kuhn 1969:
The Structure of
Scientific Revolutions
Thomas S. Kuhn
Science does not
progress continuously,
… shortcomings in an established
paradigm produces a crisis
that may lead to a revolution
…in which the established paradigm
is overthrown and replaced. .
?
?
The von Neumann paradigm?
http://hartenstein.de
© 2009,
reiner@hartenstein.de
41
Outline (6)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
42
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
22
reiner@hartenstein.de
4 December 2009
From CPU to RPU
machine
model
right now
http://hartenstein.de
© 2009,
reiner@hartenstein.de
resources
programming
property source
property
43
sequencer
programming
source
ASIC
accelerator hardwired - hardwired -
CPU hardwired - programmable
RPU
accelerator
programmable
now accelerators
are programmable!
non-von-Neumann-
Configware
(configuration
code)
programmable
Reconfigurable
Processing Unit
Software
(instruction
streams)
Flowware
(data streams)
state
register
program
counter
data
counters
we need 2 more program sources
What Revolution?
Thomas
Kuhn
is right !
“… in which the established paradigm is
overthrown and replaced.”
[Thomas S. Kuhn 1969: The Structure of Scientific Revolutions]
However, not the von Neumann paradigm
will be overthrown and replaced.
The CPU-centric world model of Software Engineering
will be replaced by removing the tunnel view perspective
http://hartenstein.de
© 2009,
reiner@hartenstein.de
44
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
23
reiner@hartenstein.de
4 December 2009
RC* outside a
CPU-centric
flat world?
For the
Multicore era
we need
a new model
(Copernican)
http://hartenstein.de
© 2009,
reiner@hartenstein.de
45
*) RC = Reconfigurable Computing
Program Performance
„Multicore computers shift the burden of software
performance from chip designers to programmers.“
... performance drops & other problems
in moving single-core to multicore ...
Since People have to write code differently,
we anyway need a Software Education Revolution ...
46
[J. Larus: Spending Moore's
Dividend; C_ACM, May 2009]
... the chance to move RC* from niche to mainstream
Embedded syst. & hdw scene have the right background
to reform the parallelism education of SW programmers
Missing http://hartenstein.deprogrammer population and methodology:
© 2009,
reiner@hartenstein.de
a scenario like before the Mead-&-Conway revolution
*) RC = Reconfigurable Computing
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
24
reiner@hartenstein.de
4 December 2009
A Heliocentric CS Model
time to space
mapping
issue
special
Flowware
Engineering
RPU
FE
SE
Software
Engineering
The Generalization of
Software Engineering —
PE
Program
Engineering
*) do not confuse
with „dataflow“!
A Twin Paradigm Dual
Dichotomy Approach.
http://hartenstein.de
© 2009,
reiner@hartenstein.de
47
A Multicore Submarine Model?
mapping parallelism just into the time domain:
“abstracting” away the space domain is fatal
C is not the silver bullet: it’s inherently serial
There is no easy way to program in parallel
http://hartenstein.de
© 2009,
reiner@hartenstein.de
48
But nobody wants to
learn a new language.
The programmer needs to understand how data flows
through cores, accelerators, interconnect and peripherals
The datastream model of the twin-paradigm approach
helps to understand the space domain and parallelism
The programmer* needs system visualization in the space
domain, to understand performance under parallelism
*) and, especially the student
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

David Parnas
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
25
reiner@hartenstein.de
4 December 2009
Our Contemporary Computer Machine Model
Machine
resources
sequencer
model
programming
property source
property
programming
source
ASIC
accelerator hardwired - hardwired -
CPU hardwired - programmable
Software
(instruction
streams)
RPU
accelerator
programmable
Configware
Flowware
(configuration programmable (data
code)
streams)
data counters of reconfigurable
address generators in asM (autosequencing)
data memory blocks
state register
program
counter
in CPU
data
counters
in RAM
twin Paradigm Dichotomy
the same language primitives!
http://hartenstein.de
© 2009,
reiner@hartenstein.de
49
Time to Space Mapping
Machine
resources
sequencer
model
programming
property source
property
programming
source
ASIC
accelerator hardwired - hardwired -
CPU hardwired - programmable
Software
(instruction
streams)
RPU
accelerator
programmable
Configware
Flowware
(configuration programmable (data
code)
streams)
Relativity Dichotomy
loop turns
2 pipeline C
state register
program
counter
data
counters
1967
„The biggest payoff will come from Putting Old ideas into
Practice and teaching people how to apply them properly.“
C
http://hartenstein.de
© 2009,
reiner@hartenstein.de
50
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
26
reiner@hartenstein.de
4 December 2009
How to achieve acceptance
Hardware description
languages hidden
Tools usable by users
not being hardware
designers
„How to hide the ugliness
from the user“ [Herman Schmit]
Courses tailored for
students not being
hardware-savvy
[Courtesy Richard Newton]
http://hartenstein.de
© 2009,
reiner@hartenstein.de
51
Software Education (R)evolution:
step by step, not overthrowing the SE scene
by simultaneous dual domain co-education:
traditional qualification in the time domain
+ lean qualification in the space domain
= lean hardware modeling qualification
at a higher level of abstraction
viable methodology for dual rail education
(only a few % curricula need to be changed)
http://hartenstein.de
© 2009,
reiner@hartenstein.de
52
52
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
27
reiner@hartenstein.de
4 December 2009
We need a Software Education Revolution
2010 - ....
DOS to Windows
took 10 years
partially
re-write
the code
Create the
missing
programmer
population
next most
http://hartenstein.de
effective
©
project in
2009,
reiner@hartenstein.de
the history of modern
computer science
The incubator
of the free ride
on Cowhey‘s &
Aronson‘s law
53
53
massive
funding
required
RAW 2010
in conjunction with:
17th Reconfigurable Architectures Workshop
April 19-20, 2010, Atlanta (Georgia), USA
Run-Time Reconfiguration & Adaptive Computing:
Architectures, Algorithms, Technologies
24th IEEE International
Parallel and Distributed
Processing Symposium
April 19-23, 2010,
Atlanta (Georgia) USA
http://www.ece.lsu.edu/vaidy/raw/
Manuscript due: October 18, 2009
Notification of acceptance: December 14, 2009
Camera-ready Papers Due: February 1, 2010
http://www.ipdps.org/
http://hartenstein.de
© 2009,
reiner@hartenstein.de
54
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

the end of the
singlecore era
Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
28
reiner@hartenstein.de
4 December 2009
Outline (7)
• The Power Consumption of Computing
• The Single-Core Approach
• The Multicore Scenario
• The Silver Bullet?
• A CPU-centric Flat World
• The Generalisation of Software Engineering
• Conclusions
http://hartenstein.de
© 2009,
reiner@hartenstein.de
55
Conclusions (1)
To maintain a Booming Multicore Era:
possible for 2 or 3 more decades?
Not without Reconfigurable Computing!
relative
performance
http://hartenstein.de
© 2009,
reiner@hartenstein.de
04 06 08 10 12 14 16 18 20 22
56
24 26 28 30
year
56
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
29
reiner@hartenstein.de
4 December 2009
key motivation: performance and
energy consumption of programs
Conclusions
additional Flowware / Configware skills are
essential qualifications for programmers.
we need to master hetero of
all 3: Singlecore, Multicore,
& Reconfigurable Computing
Mead-&-Conway-style
SE Revolution toward
dual-rail education
is urgently needed
SERUM-RC
the key issue:
ease of use!
massive long term
R&D funding required
like known from DARPA
http://hartenstein.de
© 2009,
reiner@hartenstein.de
A main problem: selecting (or
creating) tools for lab courses
57
We need „une' Levée en Masses“
We need „une'
Levée en Masses“
http://hartenstein.de
© 2009,
reiner@hartenstein.de
58
58
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
30
reiner@hartenstein.de
4 December 2009
thank you for your
patience
http://hartenstein.de
© 2009,
reiner@hartenstein.de
59
59
END
http://hartenstein.de
© 2009,
reiner@hartenstein.de
60
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
31
reiner@hartenstein.de
4 December 2009
CV of Reiner Hartenstein
Credited to be „The father of Reconfigurable Computing“ (also pre-FPGA era) [1],
Creator of KARL[2], most successful [3] trailblazer HDL before VHDL came up
EU grant (80ies), 85 mio ECU (pre-€): complete EDA framework [4,5] around KARL
1981: visiting professor at UC Berkeley (& coop. w. Xerox PARC)
KARL: a
Pascalish
hardware
language
1983: founder of the German contribution to the Mead-&-Conway VLSI design revolution:
the multi university „E.I.S. project“ (gov. grant: 38 million Deutschmark)
Founder / co-founder of several international annual conference series
IEEE fellow, SDPS fellow, FPL fellow, best paper awards, other awards
Professor (ordinarius emeritus), TU Kaiserslautern
his hobby:
giving keynotes
http://hartenstein.de/keynotes.htm
reiner@hartenstein.de
All acad. degrees from KIT Karlsruhe Institute of Technology (his mentor: Karl Steinbuch)
[1] qu. Viktor Prasanna (with Gerald Estrin as the grandfather of Reconfigurable Computing, who proposed it in 1960 WJCC)
[2] R. Hartenstein: Fundamentals of Structured Hardware Design; American Elsevier, 1977 -- Bestseller
[3] for users, usage details, quotations,etc.see: http://www.fpl.uni-kl.de/staff/hartenstein/KARLUsers.html
[4] R. http://hartenstein.de
Hartenstein: The History of KARL and ABL; in: J. Mermet (editor): Fundamentals and Standards in
Hardware © 2009, Description Languages; ISBN 0-7923-2513-4, Kluwer (now Springer), September 1993.
also reiner@hartenstein.de
see: http://xputers.informatik.uni-kl.de/karl/karl_history_fbi.html
[5] format-checking functional floorplan graphic editor, and textual editors, calculus-based term rewriting floorplan generator,
embedded router, automatic test generation, testability analysis, structured logic 61synthesis, simulator, et al. -- also see [4]
1977 & later
used as a
textbook at
UC Berkeley
(not only here)
61
backup for discussion
http://hartenstein.de
© 2009,
reiner@hartenstein.de
62
62
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
32
reiner@hartenstein.de
4 December 2009
Double Dichotomy
1) Paradigm Dichotomy
von Neumann Machine Datastream Machine
instruction stream data stream
(Software-Domain)
(Flowware-Domain)
2) Relativity Dichotomy
time: space:
-Procedure -Structure
(Software-Domain)
(Configware-Domain)
http://hartenstein.de
© 2009,
reiner@hartenstein.de
63
63
time
time domain:
procedure domain
Relativity Dichotomy
space
2 phases:
1) programming
instruction streams
2) run time von Neumann Machine
(time time/space)
space domain:
structure domain
3 phases:
1) reconfiguration
of structures
2) programming
data streams
3) run time
Datastream Machine
http://hartenstein.de
© 2009,
reiner@hartenstein.de
64
64
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
33
reiner@hartenstein.de
4 December 2009
time-iterative to space-iterative
n time steps,
1 CPU
a time to
space
mapping
1 time step,
n DPUs
loop transformation
methodogy: 70ies and later
e. g. example: bubble sort migration
Often the space dimension is limited
n*k time steps,
1 CPU
a time to
space/time
mapping
n time steps,
k DPUs
Strip mining
[D. Loveman, J-ACM, 1977]
http://hartenstein.de
© 2009,
reiner@hartenstein.de
65
65
time to space mapping
time domain:
procedure domain
conditional
swap
http://hartenstein.de
© 2009,
reiner@hartenstein.de
program loop
n time steps, 1 CPU
Bubble Sort
n x k time steps,
x
y
time algorithm
1 „conditional
swap“ unit
time algorithm
space domain:
structure domain
space algorithm
pipeline
1 time step, n DPUs
Shuffle Sort
k time steps,
n „conditional
swap“ units
space/time algorithm s
conditional
swap
conditional
swap
conditional
swap
conditional
swap
66
66
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
34
reiner@hartenstein.de
4 December 2009
4
2
3
1
*> Declarations
EastScan is
step by [1,0]
end EastScan;
SouthScan is
step by [0,1]
endSouthScan;
NorthEastScan is
loop 6 times until [*,1]
step by [1,-1]
endloop
end NorthEastScan;
SouthWestScan is
loop 7 times until [1,*]
step by [-1,1]
endloop
end SouthWestScan;
HalfZigZag is
EastScan
loop 3 times
SouthWestScan
SouthScan
NorthEastScan
http://hartenstein.de
© 2009,
reiner@hartenstein.de
EastScan
endloop
end HalfZigZag;
Main program:
goto PixMap[1,1]
HalfZigZag;
SouthWestScan
uturn (HalfZigZag)
y
x
JPEG zigzag scan pattern
Flowware language example (MoPL):
programming the datastream
1 2 3 4 5 6 7 8
data HalfZigZag
counter
data counter
data counter
data counter
HalfZigZag
67
(an animation)
67
x
1
2
3
4
5
6
7
8
y
LPF 1
FMDemod
Split
LPF 2 LPF 3
Programming model: Flowware
• Pros for streaming
[Pierre Paulin]
– Streamlined, low-overhead
communication
– (More) deterministic behaviour
– Good match for many simple media
rich applications
HPF 1 HPF 2 HPF 3
Gather
• Cons
– control-dominated applications
– shunt yard problem
Source:
MIT
StreamIT
Adder
Speaker
We„ve to find out, which applications
types and programming models Students
should exercise for the flowware approach
http://hartenstein.de
© 2009,
reiner@hartenstein.de
68
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
35
reiner@hartenstein.de
4 December 2009
Flowware means parallelism
resulting from time to space migration
Flowware
Flowware: scheduling data streams -
from a generalization of the systolic arrays
supports any wild free form of pipe networks:
spiral, zigzag, fork and join, and even more wild,
unidirectional and fully or partially bidirectional,
Fifos, stacks, registers, register files, RAM blocks...
http://hartenstein.de
© 2009,
reiner@hartenstein.de
69
Ways to implement an Algorithm
• Hardware
• Software
• Configware
• mixed
RAM-based
von
Neumannmachine
datastream
machine
singlecore
multicore
manycore
. manycore
per se
http://hartenstein.de
© 2009,
reiner@hartenstein.de
70
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
36
reiner@hartenstein.de
4 December 2009
Acceleration Mechanisms
•parallelism by multi bank memory architecture
•auxiliary hardware for address calculation
•address calculation before run time
•avoiding multiple accesses to the same data.
•avoiding memory cycles for address computation
•optimization by storage scheme transformations
•optimization by memory architecture transformations
http://hartenstein.de
© 2009,
reiner@hartenstein.de
71
New boundary constraints
New boundary constraints are the limiting factor
Legacy scientific applications: predominantly sequential
The entire software ecosystem will need to evolve
(including curricula): O/S, libraries, software
development environments, compilers and languages
additional levels of parallelism: chaining, pipelining,
systolic, super-systolic, wavefront arrays
additional data structures and storage organization:
the new distributed memory discipline
http://hartenstein.de
© 2009,
reiner@hartenstein.de
27 October 2008 Software 2008, Zurich
72
72
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
37
reiner@hartenstein.de
4 December 2009
old Paradigms and Methodologies
1946: Machine Paradigm (von Neumann)
1980: Datastreams (Kung, Leiserson)
1989: Anti Machine** Paradigm (TU-KL)
1990: first rDPA* (Rabaey)
1994: higher Anti Machine** Programming Language (Flowware: TU-KL)
1995: super systolic array: rDPA (Kress)
1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), ...
**) datastream machine
(flowware machine):
no „dataflow machine“!!
*) rDPA = reconfigurable
Data Path Array
1997+: Discipline of Distributed Memory Architectures (IMEC …)
1997: first automatically partitioning Configware/Software Co-Compiler
(TU-KL)
http://hartenstein.de
© 2009,
reiner@hartenstein.de
73
“We urgently need a
Mead-&-Conway-style
new mass movement“
SERUM-RC*
http://hartenstein.de
© 2009,
reiner@hartenstein.de
74
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden

Reiner Hartenstein, TU Kaiserslautern, Germany
http://hartenstein.de/RH-bio.pdf
38
reiner@hartenstein.de
4 December 2009
SERUM-RC*
Software Education Revolution
for using Multicore - and RC* (SERUM-RC*)
*) Reconfigurable Computing
http://hartenstein.de
© 2009,
reiner@hartenstein.de
75
75
“We urgently need a
Mead-&-Conway-dimension
text book on twin-paradigm
programming education“
Teaching computing fundamentals
Ignoring Reconfigurable Computing
in teaching computing fundamentals
within our CS curricula is one of
the biggest mistakes in the history of
information technology application
causing to waste billions of dollars.
http://hartenstein.de
© 2009,
reiner@hartenstein.de
reiner@hartenstein.de
76
Opening keynote, the 6 th FPGAworld Conference, 10 Sep 2009, Stockholm, Sweden