VTTF VLSI Test Technology Future - Laboratory for Reliable ...

Electronic Design Automation and Test 2002
VTTF
VLSI Test Technology Future
Chauchin Su
Department of Electrical and Control Engineering
National Chiao Tung University
Hsinchu, Taiwan 300
http://ccsu.cn.nctu.edu.tw/
NTHU DTC 2002 P.1

ITRS 2001 Summary
T Nodes
2001
2003
2005
2007
2010
2013
2016
Gate L (nm)*
90
65
45
32
22
16
11
DRAM HPitch
130
100
80
65
45
32
22
Memory (Gbits)
0.54
10.7
2.15
4.29
8.59
32
64
Logic Size (MTx)
69
110
174
276
552
1104
2209
On-Chip Clk(GHz)
1.7
3.1
5.2
6.7
12
19
28
Off-Chip Clk(GHz)
1.7
3.1
5.2
6.7
12
19
28
Signal IO Pins
1500
1700
2000
2200
2400
2700
3000
Min Vdd (V)
1.1
1..0
0.9
0.7
0.6
0.5
0.4
* Off-Chip Clk is for high speed peripheral buses
NTHU DTC 2002 P.2

Market Drivers
Portable and Wireless
Function: 2x / 2 years
Broad Band
Bandwidth: 2x / 9 months
Function: 20% increase / year
Internet Switching
Bandwidth: 4x / 3-4 years
Consumer
Time-to-Market: < 12 months
Function: novelty
Computer
Speed: 2x / 2 years
Form Factor: Shrinking size
Automotive
Ruggedness
Reliability and Safety
Mass Storage
Density: 60% increase / year
Speed: 2x by 2005
NTHU DTC 2002 P.3

System Drivers
Microprocessor (MPU)
Microprocessors
Memories
Reprogrammable (FPGA)
Analog / Mixed-Signal (AMS)
RF Circuits
Analog Circuits
Analog / Digital Converters
System on Chip (SoC)
A yet-Evolving Product
Integrates MPU and AMS IPs
Hardware / Software Codesign
NTHU DTC 2002 P.4

System on Chip Overview
High
Transistor
Count
High
Pin
Count
SoC
High
Speed
NTHU DTC 2002 P.5

SoC - System on Chip
ASIC
IP
System on Board
System on Chip
NTHU DTC 2002 P.6

SoC - The Benifits
• Reduction in
• Size
• Weight
• Cost
• Time
• Power
• Increase in
• Profit
• Powerfulness
• Portability
NTHU DTC 2002 P.7

SoC - The Emerging Issues
• Integration
− Soft Core
− Firm Core
− Hard Core
• Description
− Documentation
− Simulation
− Verification
− Security
• Testing
− High Speed
− Mixed Signal
− RF Testing
− Varieties
NTHU DTC 2002 P.8

SoC - Applications
Computer
SoC
Communication
Consumer
NTHU DTC 2002 P.9

SoC - Computers
Monitor
KeyBoard
Mouse
P Ports
S Ports
USB
Processor
Processor
Processor
Processor
Processor
Processor
BIOS
PU
CPU
MMU
Cache
RAM
Processor
Processor
Processor
Processor
Processor
Processor
Audio
FireWire
Ethernet
USB
Floppy
HardDisk
NTHU DTC 2002 P.10

SoC - Computers
Monitor
KeyBoard
Mouse
P Ports
S Ports
USB
Processor
Processor
Processor
Processor
Processor
Processor
BIOS
PU
SoC
CPU MMU
Cache
RAM
Processor
Processor
Processor
Processor
Processor
Processor
Audio
FireWire
Ethernet
USB
Floppy
HardDisk
NTHU DTC 2002 P.11

SoC - Communications
ADC
Encode
Digital
Modulation
DAC
DAC
Decode
Digital
Demod
ADC
STR
VCXO
PLL
Freq
Synth
Difficulties
NTHU DTC 2002 P.12

SoC - Consumer Electronics
Audio
Video
Servo
VoCoder MD DCC CD
Digital Camera Digital Camcorder
CD CDROM DVD Robot
Image
Sensor
LCD
Display
ADC
DAC
Video
Encode
Video
Encode
MPU
Memory
Mass Storage
NTHU DTC 2002 P.13

SoC – Multiple Technologies
Logic
SRAM
Flash
E-DRAM
CMOS RF
FPGA
FRAM
MEMS
Chemical Sensors
Electro-Optical
Electro-Biological
98 00 02 04 06 08 10 12
NTHU DTC 2002 P.14

SoC Trends –PDA SoC-LP Driver
Year
2001
2004
2007
2010
2013
2016
Technology (nm)
130
90
65
45
32
22
Supply (V)
1.2
1
0.8
0.6
0.5
0.4
Frequency (MHz)
150
300
450
600
900
1200
Perform (GOPs)
0.3
2
15
103
720
5042
Avg Power (W)
0.1
0.1
0.1
0.1
0.1
0.1
Stdby Pwr (mW)
2.1
2.1
2.1
2.1
2.1
2.1
Battery (Wh/Kg)
120
200
200
400
400
-
Applications
Still
Image
Web
Mailer
Schdl
Real Time Video
TV Telephone
Voice Recogn.
Authentication
RT Interpretation
TV Telephone
Voice Recogn
NTHU DTC 2002 P.15

Grand Challenges
90nm
65nm
45nm
Maximum Quality Design Productivity (Design)
Power Management (Design)
High Speed Device Interface (Test)
Highly Integrated Design and SoCs (Test)
New Reliability Screens (Test)
22nm
11nm
2001 2003 2005 2007 2010 2013 2015
Global Wiring Issues (Interconnect)
Noise Management (Design)
Error-Tolerant Design
NTHU DTC 2002 P.16

Test Difficult Challenges
90nm
65nm
45nm
22nm
11nm
High Speed Device Interface
Highly Integrated Design
Reliability Screens
Manufacturing Test Cost
Modeling and Simulation
2001 2003 2005 2007 2010 2013 2015
DUT to ATE Interface
Test Methodology
Defect Analysis
Failure Analysis
Disruptive Device Technologies
NTHU DTC 2002 P.17

Test Difficult Challenges - Revisit
90nm
65nm
45nm
22nm
11nm
High Speed Device Interface
Highly Integrated Design
Reliability Screens
Manufacturing Test Cost
Modeling and Simulation
2001 2003 2005 2007 2010 2013 2015
DUT to ATE Interface
Test Methodology
Defect Analysis
Failure Analysis
Disruptive Device Technologies
NTHU DTC 2002 P.18

Test Difficult Challenges
• High Speed Device Interface
– High frequency and high pin count test socket
– High speed serial interface requires high speed source/capture and
jitter analysis. FDT/DFM techniques must be developed.
– Device interface must not degrade BW, especially for LVDS.
• Highly Integrated Design
– Structure and specific DFT for embedded specialized cores.
– Analog DFT and BIST techniques to simplify test interface.
– RF and audio circuit embedded in large noisy digital blocks.
– Test reuse for reusable cores in complex designs.
NTHU DTC 2002 P.19

Test Difficult Challenges
•Reliability Screens
– Limited existing methodologies: burn-in v.s. thermal runaway, IDDq v.s
large background current.
– Identify novel infant mortality defect stress conditions.
•Manufacturing Test Cost
– Cost reduction: massively parallel, wafer level test, wafer level burn in.
– Through DFT to reduce test pin count and time and equipment reuse.
– Test standards to enable test content reuse and manufacturing agility.
•Modeling and Simulation
– Logic and timing accurate simulation of the ATE, DIB, and DUT.
– Accurate simulation model for pin electronics, power supply, and DIB.
NTHU DTC 2002 P.20

Test Trend – Test Technology Requirements
• Potential Yield Losses
• Automated Test Equipment Cost
• Test and Yield Learning
• IDDQ Testing
• High Frequency Serial Communications
• High Performance ASIC Test Requirement
• High Performance Microprocessor Test Requirement
• Low End Microcontroller Test Requirements
• Mixed Signal Testing
• Equipment for Testing Devices Designed with DFT
• Semiconductor Memories Test Requirements
• Reliability Technology Requirements
• Material Handling Technology Requirement
• Device Interface Technology Requirement
• Potential Solutions
NTHU DTC 2002 P.21

Test Challenges – Yield Losses
90nm
600ps
40 ps
75nm
Device Period
450ps
30ps
60nm
Resolution (5%)
300ps
20ps
45nm
Overall Timing Accuracy
150ps
10ps
30nm
2001 2002 2003 2004 2005 2006 2007
NTHU DTC 2002 P.22

Test Challenges – Yield Losses
1.8ns
2ns
0.3ns
Device Period: 2ns
Timing Accuracy: 0.2ns
Timing Test at: 1.8ns
Guard Band: 0.2ns
Yield Loss: ~5%
Device Period: 0.3ns
Timing Accuracy: 0. 1ns
Timing Test at: 0.2ns
Guard Band 0.1ns
Yield Loss: 30~40%
NTHU DTC 2002 P.23

Test Trend – ATE Equipment Cost
TestCost = b + ∑ ( m×
x)
n
Tester Segment
b
Base Cost
m
Cost Per Pin
x
Pin Count
High Performance ASIC/MPU
Mixed Signal
250 ~ 400K
250 ~ 350K
2.7 ~ 6K
3 ~ 18K
512
128 ~ 192
DFT Tester
100 ~ 350K 0.15 ~ 0.65K 512 ~ 2500
Low End Microcontroller/ASIC
Commodity Memory
RF
200 ~ 350K
200+
200+
1.2 ~ 2.5K
0.8 ~ 1K
~ 50K
256 ~ 1024
1024
32
* DFT and BIST are main stream in high end digital but penetration
into analog and SoC.
NTHU DTC 2002 P.24

Test Trend – Test and Yield Learning
• Software-based fault localization tools.
– Based on pass/fail test, voltage test, and IDDq test results.
– Integrating layout-based likelihood and/or in-line test results.
• Hardware-based fault localization methodologies.
– Multiple physical measurement points
– Fault distinguishing and diagnosis oriented test generation
– Design for debug or on-line repair.
• Non-destructive inspection
– Monitoring timing-varying signal
– Laser Voltage Probe (LVP)
– Picosecond Imageing Circuit Analysis (PICA)
– X-ray tomography
• Signature analysis techniques for failure analysis
– Tighter coupling between design, timing, and diagnosis tools.
– Integration of process monitoring structure into diagnostics.
NTHU DTC 2002 P.25

Test Trend – IDDq Testing
Year
2001
2003
2005
2008
2002
2002
IDDQmax (mA)
30–70
70-150
150-400
400-1.6A
1.6-8A
8-20A
• Use Delta IDDQ or IDDQ ratio
• Transient and charged-base Idd techniques.
• Subtrate biasing to control Vt.
• Power supply partitioning
• IDDQ measurement for multiple Vdd voltage
• IDDQ limits based on comparison with neighboring dies.
• IDDQ limits as a function of other parameters (speed)
• Built-in IDDQ sensor or on-chip measurement aids.
NTHU DTC 2002 P.26

Test Trend – High Frequency Serial Communication
2001
2.5Gbps
2002
3.125G
2004
10Gbps
2006
40Gbps
2016
80Gbps
• Giga bit serial I/Os
– SerDes, SONET/SDH, Gigabit Ethernet, Fiber Channel, Serial ATA,
Infiniband, Flat Panel Link,RAMBus, LVDS, TMDS, etc.
• Frequency
– CMOS: 3.125Gbps (‘01), SiGel: 10Gbps, GaAs and InP: 40Gbps
• Port Count:
– 20-80 pairs in 2001, 100+ pairs in 2002.
• Jitter Measurement:
– 2.5Gbps SerDes: PP Jitter=40ps,

Test Trend – Mixed Signal Test
ADC
Encode
Digital
Modulation
DAC
DAC
Decode
Digital
Demod
ADC
STR
VCXO
PLL
Freq
Synth
Difficulties
NTHU DTC 2002 P.28

ATS 2000 Panel Discussion
Mixed Signal Testing:
Is Mixed-Signal Design-for-Test on Its Ways?
Chauchin Su
Department of Electrical Engineering, National Central University
Chung-Li, Taiwan 32054, R.O.C.
http://www.ee.ncu.edu.tw/~ccsu
ccsu@ee.ncu.edu.tw
NTHU DTC 2002 P.29

The Answer is
YES
NO
MAY
BE
SO
NTHU DTC 2002 P.30

250nm
200nm
150nm
100nm
Yes. From Digital Point of View
• Look at the DFT/BIST roadmap of digital circuits.
• Look at the SIA roadmap (ITRS 1999).
Mixed Signal Instrument
BIST/DFT
Probe & Test Socket
IDDQ Testing
Test Development Time
50nm
1997 1999 2001 2003 2006 2009 2012
Fault Model
Rules to Test
Standard Test
Software
DFT
Failure Analysis
NTHU DTC 2002 P.31

No, From Practical Point of View
• Analog circuit designers design perfect circuits.
• No one dare to change it.
v s
NTHU DTC 2002 P.32

May Be. It will never happen.
• Analog are giving up ground to digital.
• The performance becomes very critical.
RF, IF, BB, AD/DA, Digital
RF, IF, AD/DA, Digital
RF, AD/DA, Digital
NTHU DTC 2002 P.33

May Be. It will never happen.
• Analog design is an endless game.
• Ft is always 10 times the operating frequency.
T Nodes
1997
1999
2001
2003
2006
2009
2012
Feature Size (nm)
250
180
150
130
100
70
50
Supply Voltage
2.5~1.8
1.8~1.5
1.6~1.3
1.5~1.2
1.2~0.9
0.9~0.6
0.8~0.5
Frequency (GHz)
1.8~2.5
2.5~3.5
3.0~4.0
3.5~5.0
5.0~6.5
6.5~9.5
9.5~13
Current (uA)
100
75
60
50
40
30
20
Fmax
25
35
40
50
65
90
120
Ft
20
30
35
40
55
75
100
Noise Figure
2
1.5
1.3
1.2
30
>35
>40
>40
>40
NTHU DTC 2002 P.34

So. Test Resource Partitioning
Analog
Analog
ADC
DAC
MPU
RAM
External
Instrument
Loop
Back
Digital
DSP
ROM
• Specialized DFT and BIST for digital modules.
• ATE assisted DFT/BIST for analog modules
• External instruments are responsible for reference
signal generation.
• DSP and MPU are the resources for analog signal
metrology and response analysis.
NTHU DTC 2002 P.35

Test Trend – Potential Solutions
DFT/BIST Methodology
Current DFT/BIST/IDDQ
New DFT/BIST/IDDQ
Aanlog DFT/BIST
Design Owns Test
Cost of Test
100% DFT/BIST
Standard Test Lib
Design to Test
Test Reuse
High Performance Interface
> GHz Interface
+/-1% Temp Control
Reliability Screen
New Acceleration Mechanism
01 03 05 07 09 11 13 15
Research Development Production
01 03 05 07 09 11 13 15
NTHU DTC 2002 P.36

System on Chip
Design and Test?
Analog
Analog
ADC
DAC
MPU
RAM
Digital
DSP
ROM
NTHU DTC 2002 P.37

So, Come and Join VTTF Taiwan.
VTTF: VLSI Test Technology Forum
http://eda.ee.nthu.edu.tw/VTTF/
NTHU DTC 2002 P.38