Cadence OrCAD PCB Designer

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SCLK nSS MISO MISO SCLK nSS PTE6 PTE7 PTE6 PTE7 VCC VCC VCC VCC VCC V+ R7 100k R7 100k U1D LM324 U1D LM324 + 12 - 13 V+ 4 V- 11 OUT 14 R8 47k R8 47k R9 10k R9 10k R10 10k SET = 0.5 R10 10k SET = 0.5 J1 Sensor J1 Sensor 1 2 3 4 C1 100n C1 100n U1B LM324 U1B LM324 + 5 - 6 V+ 4 V- 11 OUT 7 C2 100n C2 100n SW1 Tare SW1 Tare R1 100k R1 100k C3 10u 16V C3 10u 16V U1C LM324 U1C LM324 + 10 - 9 V+ 4 V- 11 OUT 8 R2 4.7k R2 4.7k SW2 Calibrate SW2 Calibrate R3 100k R3 100k J2 Softec J2 Softec 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 U2 TLC549 U2 TLC549 AIN 2 I/OCLK 7 REF+ 1 REF- 3 DOUT 6 CS 5 U1A LM324 U1A LM324 + 3 - 2 V+ 4 V- 11 OUT 1 R4 100k R4 100k R5 100k R5 100k R11 4.7k R11 4.7k R6 100k R6 100k Figure 22. Instrumentation amplifier and analogue-to-digital converter for an electronic weight scale. 42
Property Editor with Edit > Properties. . . . Make the Pins sheet active instead of the usual Parts. This shows the numbers and names of the pins (and more). Make sure that the names are defined elsewhere to provide the correct connections. • Why three capacitors in parallel? These are for decoupling noise away from sensitive components and must be positioned carefully when you lay out the board. One of the 100 nF capacitors should be as close as possible to the power pins of the op-amp and the other should be as close as possible to those of the ADC. The 10 µF capacitor is electrolytic and its placement is less critical. • The variable resistor R11 is a ‘virtual component’ and must be replaced by a real component in your schematic. How is this done? • The pushbuttons are in a local Capture library called projects, which is in the tdp3_orcad folder on the Elecapps networked drive. • Note the orientation of the 8 × 2 header carefully. Pin 1 is top left when viewed from the top of the board but the part is mirrored in some libraries. Hint for demonstrators. ❦ 1. A power or ground symbol called V− must be added to the ground net. (There is a convenient space below V+!) 2. The power pins of the ADC are called VCC and GND so they are automatically connected without further effort. 3. The variable resistor must be replaced by a potentiometer, whose wiper is connected to one end (it doesn’t matter which). 4. Check the orientation of J2 despite the warning in the instructions. ☛ Milestone: Ask a member of staff to check your schematic drawing before proceeding. Here are a few more points to help you lay out the <strong>PCB</strong>. • The footprints for the pushbutton have four pins but the capture symbol has only two pins. You must therefore create a NC property with the value 3,4 to mark these pins as unconnected, as for the op-amp on page 30. • I’ve provided the front pages of the data sheets for the LM324 and TLC549 so that you can see the pinouts and general features. • Aim to keep the noisy, digital SPI away from the sensitive analogue inputs. • The four op-amps within the LM324 are identical so you might wish to swap them around to get a better layout – I assigned the four randomly. • Make the power and ground tracks wider as usual. 43
Page 1 and 2: Electronic Design Project 2 Cadence
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Page 5 and 6: 2. The base-emitter junction of a t
Page 7 and 8: • Select an Analog or Mixed A/D p
Page 9 and 10: Figure 2. Gain as a function of fre
Page 11 and 12: Capture Draw schematic PCB Editor S
Page 13 and 14: 2. Choose Edit > Properties. . . fr
Page 15 and 16: Figure 6. Completed dialogue box fo
Page 17 and 18: Figure 7. Completed dialogue box fo
Page 19 and 20: Figure 8. Screenshot of OrCAD PCB E
Page 21 and 22: Figure 9. The Placement dialogue bo
Page 23 and 24: • To rotate a selected component,
Page 25 and 26: Hint for demonstrators. Some studen
Page 27 and 28: • Usually the Plot scaling should
Page 29 and 30: Table 2. Footprints for instrumenta
Page 31 and 32: Figure 13. Constraint manager after
Page 33 and 34: Figure 15. Screenshot of SPECCTRA,
Page 35 and 36: Figure 17. My one-sided layout afte
Page 37 and 38: Figure 18. Printout at actual size
Page 39 and 40: • The pins of the integrated circ
Page 41: in 2007-08, which was an electronic
Page 45 and 46: 9 Summary: PCB design flow This lis
Page 47 and 48: A Where to learn more The online he
Page 49 and 50: B Power-user tips and random jottin
Page 51 and 52: Figure 24. Padstack editor settings
Page 53 and 54: Figure 26. Screenshot and photomask
Page 55 and 56: 3. The list on the right-hand side
Page 57 and 58: • Our local allegro library doesn

Cadence OrCAD PCB Designer

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