05 Arithmetic in VHDL
05 Arithmetic in VHDL 05 Arithmetic in VHDL
Declaring Arithmetic Signals & Variables • NUMERIC_STD offers 2 data types – SIGNED, UNSIGNED – These are declared in a similar method to ‘std_logic_vector’ – Can be used to ‘declare’ signals, variables, even ports in an entity • UNSIGNED – Assumes that only positive values are going to be used – Example declaration signal count: unsigned (3 downto 0) – This creates a signal used for storing values 0 -> 15 114
Declaring Arithmetic Signals & Variables • SIGNED – 2’s complement form, with MSB used as a sign bit – Example declaration signal count: signed (3 downto 0) – Creates a signal used for storing the values -8 -> +7 Integer Signed -8 1000 -1 1111 0 0000 +7 0111 115
- Page 1 and 2: Arithmetic Packages- Introduction
- Page 3: Arithmetic Package Overview- II •
- Page 7 and 8: Arithmetic Package Functions- I •
- Page 9 and 10: Arithmetic Package Functions- III
- Page 11 and 12: Arithmetic Package Functions- V •
- Page 13 and 14: Arithmetic Package Functions- VII
- Page 15 and 16: Arithmetic Package Example- I • S
- Page 17 and 18: Arithmetic Package Example- III •
Declar<strong>in</strong>g <strong>Arithmetic</strong> Signals & Variables<br />
• NUMERIC_STD offers 2 data types<br />
– SIGNED, UNSIGNED<br />
– These are declared <strong>in</strong> a similar method to ‘std_logic_vector’<br />
– Can be used to ‘declare’ signals, variables, even ports <strong>in</strong> an entity<br />
• UNSIGNED<br />
– Assumes that only positive values are go<strong>in</strong>g to be used<br />
– Example declaration<br />
signal count: unsigned (3 downto 0)<br />
– This creates a signal used for stor<strong>in</strong>g values 0 -> 15<br />
114
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