05 Arithmetic in VHDL
05 Arithmetic in VHDL 05 Arithmetic in VHDL
Arithmetic Package Overview- I • VHDL offers a number of packages which provide common arithmetical functions – Addition (+) – Subtraction (-) – Multiplication (*) – Division (/) – Comparison (=, >,
Arithmetic Package Overview- II • There are a number of different packages that exist for historical reasons – STD_LOGIC_ARITH, std_logic_signed, std_logic_unsigned – NUMERIC_STD (IEEE) • We will only consider ‘NUMERIC_STD’ as it is the only standard package which is defined on all commercial synthesis and simulation tools – Tools must provide a common set of arithmetical functions – Synthesis result (gates and how they are connected) will change with synthesis tool, but functionality will not 113
- Page 1: Arithmetic Packages- Introduction
- Page 5 and 6: Declaring Arithmetic Signals & Vari
- Page 7 and 8: Arithmetic Package Functions- I •
- Page 9 and 10: Arithmetic Package Functions- III
- Page 11 and 12: Arithmetic Package Functions- V •
- Page 13 and 14: Arithmetic Package Functions- VII
- Page 15 and 16: Arithmetic Package Example- I • S
- Page 17 and 18: Arithmetic Package Example- III •
<strong>Arithmetic</strong> Package Overview- II<br />
• There are a number of different packages that exist for<br />
historical reasons<br />
– STD_LOGIC_ARITH, std_logic_signed, std_logic_unsigned<br />
– NUMERIC_STD (IEEE)<br />
• We will only consider ‘NUMERIC_STD’ as it is the only<br />
standard package which is def<strong>in</strong>ed on all commercial<br />
synthesis and simulation tools<br />
– Tools must provide a common set of arithmetical functions<br />
– Synthesis result (gates and how they are connected) will change<br />
with synthesis tool, but functionality will not<br />
113
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