05 Arithmetic in VHDL
05 Arithmetic in VHDL 05 Arithmetic in VHDL
Arithmetic Package Functions- VI • Simple conversion functions – Used to convert integer/ natural numbers to and from signed/ unsigned Function Description Argument 1 Argument 2 Returns to_integer Convert to integer unsigned signed natural integer to_unsigned to_signed Convert to unsigned Convert to signed natural integer natural (size) natural (size) unsigned (size) signed (size) 122
Arithmetic Package Functions- VII • Conversion to/ from std_logic_vector – Used to convert signed and unsigned values to and from std_logic_vector » Really just copies each bit Function Description Argument Returns unsigned Convert to unsigned std_logic_vector unsigned signed Convert to signed std_logic_vector signed std_logic_vector Convert to std_logic_vector unsigned std_logic_vector std_logic_vector Convert to std_logic_vector signed std_logic_vector 123
- Page 1 and 2: Arithmetic Packages- Introduction
- Page 3 and 4: Arithmetic Package Overview- II •
- Page 5 and 6: Declaring Arithmetic Signals & Vari
- Page 7 and 8: Arithmetic Package Functions- I •
- Page 9 and 10: Arithmetic Package Functions- III
- Page 11: Arithmetic Package Functions- V •
- Page 15 and 16: Arithmetic Package Example- I • S
- Page 17 and 18: Arithmetic Package Example- III •
<strong>Arithmetic</strong> Package Functions- VII<br />
• Conversion to/ from std_logic_vector<br />
– Used to convert signed and unsigned values to and from<br />
std_logic_vector<br />
» Really just copies each bit<br />
Function Description Argument Returns<br />
unsigned<br />
Convert to<br />
unsigned<br />
std_logic_vector<br />
unsigned<br />
signed<br />
Convert to<br />
signed<br />
std_logic_vector<br />
signed<br />
std_logic_vector<br />
Convert to<br />
std_logic_vector<br />
unsigned<br />
std_logic_vector<br />
std_logic_vector<br />
Convert to<br />
std_logic_vector<br />
signed<br />
std_logic_vector<br />
123
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