Design Rules for Silicon Photonics Prototyping - Institute of ...

Design Rules for Silicon Photonics
Prototyping
Version 1 (released February 2008)
Introduction
IME’s Photonics Prototyping Service offers 248nm lithography based fabrication technology for
passive Silicon-on-insulator photonic circuits at a cost affordable to research groups and
companies.
This document briefly describes:
1) Key fabrication process of this technology,
2) Guidelines for the design and fabrication of passive Silicon-on-insulator photonic circuits
through this technology,
3) Design rules for the mask files.
Technology Key Aspects
• 200 mm Silicon-on-Insulator wafer: typically, 220nm top silicon, 2000nm buried oxide
• 248nm deep UV lithography
• Typical/minimum pitch [nm]: 450 / 400 (binary mask)
• Typical/minimum line width [nm]: 220 / 170 (binary mask)
(Phase Shift Mask is optional for structures with feature size smaller than above spec., Please
contact coordinator for detailed information.)
• Use of Tip couplers
Coordinator Contact
Patrick Lo Guo Qiang
Institute of Microelectronics, Singapore
logq@ime.a-star.edu.sg
Phone: +65-6770-5705
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Contents
1. Description of Key Fabrication Process
1.1 Fabrication Process flow 3
1.2 Wafer Specification 3
1.3 Lithography 3
1.4 Etching 4
1.5 Mask Technology 4
1.6 Facilitating Measurements 4
2. Design Rules
2.1 Minimum Feature Sizes 5
2.2 Multiple Structure Design 5
2.3 Multiple Circuit Design 6
2.4 Appendix: Exposure Latitude for Some Critical Structures 6
Photonic Crystal Holes 6
Isolated Lines (photonic wires) 7
Gap Width 8
Tip Coupler Design 8
3. Mask File
3.1 Mask File Format 9
3.2 Hierarchy 9
3.3 Software 9
3.4 Dark Field/ Light Field 10
3.5 Layer Structure 10
3.6 General Layout Rule 11
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1. Description of Key Fabrication Process
1.1 Fabrication Process Flow
The standard fabrication process flow IME uses for photonic passive device and
components are schematically shown as below (here 248nm lithography is used):
(a) Bare Si-substrate wafer
Si
-- Si-substrate
SiO2
-- Buried SiO 2 (2 μm)
-- Top Si Layer (220nm)
Si
(b) Bottom AR coating (BARC)
(c) Photo-resist (PR) coating and soft bake
(d) Exposure
(e) Post-exposure bake
(f) Development
PR
Si
SiO2
Si
Barc
(g) BARC & Silicon etch
PR
Si
SiO2
Barc
Si
(h) Photo-resist strip & clean
(i)
Si-surface Treatment
Si
SiO2
Si
1.2 Wafer Specification
The wafers are Silicon on Insulator (SOI), typically with 220nm top silicon layer and
2000nm buried oxide.
1.3 Lithography
The standard lithography process used for nanophotonic structures makes use of 410 nm
thick Shipley UV210 resist with a bottom antireflective coating; exposed with illumination
conditions of numerical aperture of 0.68 and a spatial coherency factor of 0.31.
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1.4 Etching
ICP low pressure/high density etch system with a chemistry based on SF 6 /C 4 F 8 /O 2 is used
to etch only the top Silicon layer.
Prior to hardmask and Si etching, BARC etch is performed using plasma etching that also
smoothen the sidewall of resist to reduce roughness (refer to process flow). BARC etch can
also be used to compensate for a feature size bias between litho and etch.
1.5 Mask Technology
The mask will be a binary Chrome Mask (without Phase Shifting features). The default
polarity of the masks are dark-field, which means that all features defined on the mask will
be transparent and therefore etched away (refer to 3.4 Dark Field/ Light Field for details).
The mask will have a useful area roughly 10 x 13.2 cm 2 , with a reduction factor of 4 ×.
Mask shop will be appointed by IME.
(For users who require Phase Shift Mask for special design, please contact coordinator for more
information.)
1.6 Facilitating Measurements
IME provides deep trench etch process using deep reactive ion etch (DRIE) to facilitate
optical measurements, without additional effort of polishing after wafer dicing.
IME also provides wafer dicing and packaging services.
Please contact the technical coordinator for more information:
Patrick Lo Guo Qiang
Institute of Microelectronics, Singapore
logq@ime.a-star.edu.sg
Phone: +65-6770-5705
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2. Design Rules
2.1 Minimum Feature Sizes
The minimum feature size that can be fabricated depends on the type of structure needed
(i.e., dependent on pattern density, shapes etc). To provide some guidelines for design,
the following table lists some of the minimum feature sizes that can be fabricated within a
periodic pattern. For users with more complex design requirements, kindly contact the
technical coordinator for more information.
Periodic structure Feature Minimum Size Typical Size
Pitch > 400nm > 450nm
Lines Width > 170nm > 220nm
Line spacing > 180nm > 220nm
Triangular Holes Diameter > 190nm > 220nm
Triangular Holes Spacing > 200nm > 240nm
For feature sizes smaller than the above listed specifications, resolution enhancement by use
of Phase Shift Masking may be used. Kindly contact the coordinator for more information.
2.2 Multiple Structure Design
Fabricated feature size varies as a function of exposure dose, which is typically expressed
in mJ/cm 2 ; quantifying the amount of light projected onto the photo-resist. E.g. holes will
become larger for a higher exposure dose, while lines will become smaller. The dose used
to fabricate structures at the desired size is called “best exposure dose”. However, in
general, structures of different types (holes vs. lines) and even structures of the same type
with different feature/pitch size will have different “best exposure dose”. Therefore, one
should take special care when incorporating structures of different types (e.g. photonic
wires and photonic crystals) on a single mask design.
Usually a sweep of the exposure dose is performed to estimate the “best exposure dose” of
the most critical structure(s). The results are summarized in the Figures of 2.4 Appendix.
Some mask design bias may be designed based on the data provided in these figures.
The following example illustrates a possible mask design bias:
Example 1: when incorporating a photonic crystal structure with triangular holes of diameter
350nm and pitch of 500nm, together with an isolated line (photonic wire) of 500nm width on
a single mask design, “best exposure dose” for holes is 40 mJ/cm 2 (see Figure 1 in 2.4
Appendix). However, at this dose, the isolated line will print at 410nm width instead of the
intended 500nm width, giving off-target results (see Figure 3 in 2.4 Appendix).
While it is most recommended that there should be only one critical structure on each layer,
i.e. for instance in example 1, either the hole size of the photonic crystal structure or the
width of the coupling wire should be critical; a ‘work-around’ solution to get both features to
print on-target in this case would be to adjust one or more structures’ size in order that they
print correctly at the same exposure dose. That is, in this case, the layout of the isolated
line on the mask can be increased to 580nm (to give the necessary 80nm design bias), so
that both photonic crystal structures and isolated line (photonic wire) can print correctly at
the same exposure of 40 mJ/cm 2 .
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In conclusion for this example, it should be noted that while such straight forward design
bias works well for simple structures, more complicated designs require more advance
compensation techniques such as placement of scattering bars etc for design of mask
biases. For such jobs, kindly contact the coordinator for more information.
2.3 Multiple Circuit Design
When incorporating multiple circuits with different “best exposure dose”, one can have all
circuits on the same wafer, but on different dies if the various “best exposure dose”, are not
too widely spread. Otherwise, different circuits will be fabricated on more than one wafer.
2.4 Appendix
Photonic Crystal Holes
Figure 1 shows the measured diameter of holes patterned in a triangular hole array (on
wafer) as a function of lithographic exposure dose for a variety of pitch and diameter (on
mask).
600
Figure 1
Triangular hole diameter vs Exposure dose
Measured Hole Diameter [nm]
500
400
300
200
100
350:450
Design diameter:pitch [nm]
350:500
300:500
270:450
240:400
0
20 30 40 50 60 70 8090100
Exposure Dose [mJ/cm 2 ]
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Figure 2 shows the measured diameter of holes patterned in square lattice array (on wafer)
as a function of lithographic exposure dose for a variety of pitch and diameter (on mask).
Figure 2
Measured Hole Diameter [nm]
500
400
300
200
100
0
Square hole diameter vs exposure dose
Design diameter:pitch [nm]
250:500
226:450
200:400
20 30 40 50 60 70 8090100
Exposure Dose [mJ/cm 2 ]
Isolated Lines (Photonic Wires)
Figure 3 shows the measured line width (on wafer) as a function of lithographic exposure
dose for a variety of designed line widths (on mask)
Figure 3
800
Isolated line width vs exposure dose
Measured line width [nm]
700
600
500
400
300
200
100
200
design iso-line width [nm]
700
600
500
400
300
0
20 30 40 50 60
Exposure dose [mJ/cm 2 ]
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Gap Width
Figure 4 shows the measured gap spacing (on wafer) between two lines with width of 0.3
μm as a function of lithographic exposure dose for a variety of designed gap widths (on
mask).
.
Measured Gap Width [nm]
Tip Coupler
900
800
700
600
500
400
300
200
100
0
Figure 4
Gap width vs exposure dose
design gap width [nm]
600 nm
550 nm
500 nm
450 nm
400 nm
350 nm
300 nm
250 nm
200 nm
20 30 40 50 60 70 80 90
Exposure Dose [mJ/cm 2 ]
For tip coupler, the following figure shows an example:
a = 180 nm
b = 200 µm
Si waveguide
a
b
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3. Mask Files
3.1 File Format
For submission of design layout to IME, the file format to be used should be GDSII. As not
all software tools support the full GDSII command set, users should limit structure
definitions to the following types:
i. BOUNDARY
Filled, closed polygons; with a maximum of 200 nodes.
ii. PATH
Open lines with a physical width.
iii. Simple Reference (SREF)
Singular reference to a previously defined structure. Transformations on references are
allowed as long as the rotation angle is a multiple of 90º.
iv. Array Reference (AREF)
An array of references to a previously defined structure. Transformations on references are
allowed as long as the rotation angle is a multiple of 90º.
Here, it is to be noted that the use of BOUNDARY type structures are preferred to PATH
type in order to avoid arbitrary grid snapping in PATH type boundaries. Also, the following
structure types are NOT supported:
i. NODE
Such elements are ignored and will not be fabricated on the mask.
ii. LABEL
Such elements are also ignored and will not appear on the mask.
3.2 Hierarchy
The layout should make full use of the GDSII hierarchy scheme such that SREFs and
AREFs are used to define repeating structures where possible so as to keep final layout file
size acceptably low. For instance, where a periodic photonic crystal lattice is required, it
should not be composed of copying thousands of individual polygons, but rather created
through instances call up of SREFs or AREFs.
The final layout should comprise of only a single top cell in which the other sub-cells of
SREFs and AREFs lower on the hierarchy are referenced.
3.3 Software
GDSII layouts may be created on most layout tools such as Cadence, Silvaco Expert, L-edit
etc. For partners without such software, layout can be created by IME in-house at a fee.
Alternatively, free layout software such as Ruby GDSII Library may be used for writing
GDSII data in the Ruby programming language (http://en.wikipedia.org/wiki/Ruby). As this
is a third-party software, its correctness and usage is solely the decision of the user, for
which IME cannot be responsible for.
For viewing of GDSII files without data manipulation, the free software CleWin may be used
(http://www.phoenixbv.com ).
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3.4 Dark Field/ Light Field
For ease of definition, the default polarity of the masks are in dark field, so that structures
defined in the layout mask files become transparent on a chrome background, and are
etched away after processing. On the other hand, to accommodate layers whereby it is
much simpler to define the structures as portions that should not be etched away (for
example in waveguides layers for lines features), light field layer definition may be used
instead of laying out two trenches to define the line.
For layers whereby there are to be both light and dark field features, the different fields are
to be laid out on separate GDSII layer numbers so as to enable subsequent logic operation
processing as shown in the next section. In general, it is highly recommended that each
layer consist of a single field type (i.e., either light or dark field).
3.5 Layer Structure
To facilitate the processing of mask data and also the application of proximity corrections for
mask data optimization. A table of the different categories for structure types is listed as
follows for layout drawing layer assignment:
Layer
Number
Layer Type
1 to 5 Non critical
6 to 10 Typical
11 to 15
16 to 20
21 to 25
26 to 30
31 to 35
36 to 40
Critical
Alternating
phase shifted
Structure
Lines, trenches,
polygons etc
Lines, trenches,
polygons etc
Lines
Trenches
Holes, pillars, polygon
widest dimension
Lines
Trenches
Holes Only
Critical
Dimension (CD)
≥ 1 µm
250 nm ≤ CD < 1 µm
Examples
Alignment marks, text,
logos, fiber grooves etc
Broad lines, ridges,
polygons etc
170 nm ≤ CD < 250 nm Photonic wires, tapers
180 nm ≤ CD < 250 nm Gaps
190 nm ≤ CD < 250 nm Photonic crystal lattice
100 nm ≤ CD < 150 nm Waveguides, gratings
140 nm ≤ CD < 190 nm Gratings, gaps
160 nm ≤ CD < 200 nm Photonic crystal
Here, the density of the patterns should also be specified, as a function of pitch, which
should not be less than 400nm unless they are of the alternating phase shifted type, which
has minimum pitch of 280nm for line space patterns and 300nm for hole-type feature.
Also, for layers with more than one type of structure, the categorisation of layers is
determined by the smallest feature on that mask. For example, for a mask having both
photonic crystal structures (with CD of 250nm), together with broad line waveguides, the
mask is assigned a layer number ranging from 21 to 25 for data processing.
On a final note, further to the description for combining of clear and dark feature on a same
mask. The following Figure 5 schematically explains the logical ‘OR’ operation of a dark
field (photonic crystal layer ‘X’) with a clear field (waveguide layer ‘Y’) layout for final layout
patterned structure as given in schematic ‘Z’.
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Dark field -
Photonic
crystal drawn
as squares
Layout
layer
‘X’
OR
Clear field -
Waveguides
drawn as lines
Layout
layer
‘Y’
To obtain this
final patterned
structure
Etched
pattern
on wafer
White area =
resist cleared
Figure 5: Schematic of logical operation involving combination of both dark and clear field
On a same mask layer.
3.6 General Layout Rules for Basis Cells
For mask fabrication at IME, all layout contributions will be fitted onto a basis cell size of
either 25 × 32 mm 2 or 25 × 16 mm 2 . This is to allow for standardised processing flow and
optimised utilisation of mask area. For every mask layer which requires subsequent
alignment and process quantification, clear-out areas without interference from other
patterns need to be reserved for both alignment and metrology structures. In general, ‘N’
such layers would require layout area of ‘N × 2500 × 100 μm 2 ’ horizontally and ‘N × 2100 ×
100 μm 2 ’ vertically. Further, for every two layers with overlay requirement, clear-out area of
150 × 80 μm 2 need to be reserved at each corner of the basis cell.
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