Si Stacked Module - Institute of Microelectronics - A*Star

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A publication of the Institute of Microelectronics
ISSN 0218-7477
An ISO 9001 certified organisation
April 2004
Contents
2 Copper low-k
interconnects
and Packaging
3 IME helping
Singapore enterprises
to “Grow, Glow, and
4 to 5
Globalise”
New microlithography
techniques for device
miniaturization
6 8 to
News Bites
Si Stacked Module - a platform technology
for semiconductor integration
and packaging
Si stacked module: 11 chips on 3 camiers at 1.2mm total height.
IME has developed a platform technology for silicon (Si)
stacked module. The Si stacked module aims to combine
different devices and circuit functions within the same
module. The development of Si stacked module is timely in
meeting the complex performance, cost, and size demands
of portable electronic devices, high performance computing
systems, and communication and entertainment systems,
which run on various combinations of analog, digital, memory,
signal processing, communications or optical ICs.
4. Si micro-channeled liquid-cooled heat sink.
The successful demonstration of Si stacked module has
attracted 9 companies to join forces with IME on 30th
January 2004 to develop the second generation of Si stacked
module through IME’s flagship consortium - 7th Electronic
Packaging Research Consortium (EPRC VII). For the first
time, this EPRC VII is championed by IME and three other
Comparing to conventional 2D integration and packaging,
3D integration and packaging offer advantages such as
higher packaging density, lower interconnect loss & delay
due to proximity between chips etc. To realize 3D integration
and packaging, there are three methods of stacking, i.e. chip
level, package level and wafer-level stacking.
a
b
Combining the best of both chip level and wafer level stacking,
IME Si stacked module offers unique features such as
1. Wafer level test strategy;
2. High yield and thus overcoming the Known Good-Die
(KGD) issue in 3D integration and packaging technologies;
3. Low insertion loss of less than -0.5dB at 40GHz;
4. Integrated cooling structure fabricated within the Si
stacked module up to 80W power dissipation.
c
(a) Through wafer solder interconnects, (b) Through wafer copper
interconnects, (c) Ultra thin 8” wafer (d) Ultra thin bumped wafer
d
To make the Si stacked module possible, a full range of stateof-the-art
facilities, expertise and competencies are needed,
including
1. Si carrier processing;
2. Si through wafer interconnect;
3. Wafer thinning and handling solutions for MEMS wafers
& bumped Si wafers with the latter’s thickness down to
70 µm;
Integrated
cooling
solution for
Si stacked
module.
Continued to page 2 >>
A research institute of the Agency for Science, Technology and Research (A*STAR)

page 2
Copper low-k interconnects and Packaging
IME developed reliable Pb-free solder flip chip packaging for Cu/ultra low-k devices
IC designers work to improve chip performance with more
complex circuits and packing them even closer on a single
piece of silicon. Limits are being reached as closely-packed
circuits start to generate interference - just as crosstalk can
occur between telephone lines. Traditionally, semiconductor
industry has used aluminum as the conductor for “wiring”
within the chip, and silicon-dioxide as dielectric for 30 years.
However, the explosive demand for miniaturized and high
performing electronics created the need for conductor
material with higher electrical conductivity (i.e. copper), and
other dielectric materials with lower k value.
Notwithstanding these requirements, Copper low-k (Cu/lowk)
technology has yet to be widespread in the IC industry
because of processing and reliability issues such as delamination
and bond pad failure. IME’s research efforts
in these areas take the form of research consortia and
collaborations with its industry partners.
In 2001, COPBOND: Breakthrough in processing and wirebond
packaging of Cu/low-k ICs
IME’s Copper Chip Wire Bond Consortium (COPBOND), a
14 member industrial consortium, achieved breakthrough
in processing, packaging and testing ICs with Cu/low-k
(k=2.67). Entering an un-chartered territory, this project
successfully delivered technologies for packaging of Cu/
low-k IC in standard Cu wire bonded BGA format. A novel
wire bond fatigue methodology for reliability study was also
established. IME’s expertise with extensive evaluations in
structural modeling and bonding processes resulted in an
innovative bond pad design. This enabled a reliable direct
bonding of fine-pitch Cu wires onto the Cu/low-k structures.
In this project different demonstrators of Cu/SiO2 & Cu/lowk
chips with and without cap metallization were wire-bonded
and packaged. They were all qualified under the industrial
reliability standards.
In 2002, WTC: Next significant milestone
Striving towards addressing the next level of challenges,
IME started Singapore’s first Wafer Technology Consortium
(WTC) with 10 participating member companies in 2002.
The consortium addressed challenges in flip chip packaging
of Cu/ultra-low-k (ULK) devices (k=2.4). The team evaluated
different stack structures in Cu/ultra-low-k devices. The
leading research effort delivered new concepts for flip chip
packaging solution which meet all industrial level reliability
tests. For the first time in the world, a Cu-based under bump
metallization which can be integrated into the Cu backend-of-line
fabrication was developed for Pb-free solder
bumping. With that, reliable flip-chip packaging for Cu/ultralow-k
devices was established.
Continued from 1 >>
sister institutes IMRE (Institute of Materials
Research and Engineering), IHPC (Institute of
High Performance Computing) and SIMTech
(Singapore Institute of Manufacturing
Technology) under the umbrella of Micro-
System Packaging (MSP) program (formerly
known as Electronic Packaging or EP).
Si stacked module is one of the many recent
milestones that IME achieved in its Si-based
advanced packaging program, which also
includes
1. Surface mountable 3D wafer level packaging
for MEMS;
2. Wafer level interconnects & packaging
targeting at future ICs of 10,000 I/Os at
20 µm pitch. In 2003, wafer level package
(WLP) of 600 I/Os @ 400 µm pitch was
delivered to the member companies of 6th
Electronic Packaging Research Consortium
(EPRC VI); in 2004, WLP of 4,000 I/Os @
100 µm pitch was achieved.
3. Cu/low-K interconnects & packaging
Surface Mountable Wafer
Level Packaging for MEMS
Together with six industry partners, IME developed low cost yet reliable
wafer level packaging that is directly mountable to PCB. This platform
technology is suitable for RF or inertial MEMS (micro-electromechanical
system) found in e.g. industrial and communication electronics. 3D
integration is also possible with other electronic functions.
Highlights of the surface
mountable WLP for
MEMS are
• Ultra low insertion loss

page 3
2004 and beyond...
Technology and industrial thrusts propelled IME to spearhead
the third research consortium on Cu/low-k packaging through
WTC 2. This consortium was launched on 12 March 2004
with the participation of seven member companies. Having
completed the extensive work in flip chip packaging of single
damascene Cu/ultra-low-k structures, the WTC 2 aims to
resolve the challenges of wire bond and flip chip packaging
of multilayer dual damascene Cu with hybrid of CVD and
spin-on deposited low-k. The project emphasizes on:
• Design, modeling & fabrication of test vehicles*
• Materials, assembly & process characterization
• Direct Au wire bond on Cu metallization and on IME
alteranate cap metallization**.
• Novel packaging approach enabling low stress on Cu/
low-k stack
* Cu/low-k ICs usually suffer from chipping during
mechanical dicing. IME has developed a low-cost
methodology which prevents mechanical dicing
from causing chipping to ICs.
** The advantages of IME alternate cap materials for
Cu metallized devices are
- simpler chemical process;
- no additional masks required;
- good bond quality;
- better longevity to oxidation & corrosion
compared to other capping methods, and
- lesser probe pad damage compared to
conventional aluminum cap.
Alternate
cap
Tantalum
barrier
Au ball
Cu bond pad
Au ball
Silicon
Alternate cap metallization on Cu/low-k
The first Wafer Technology Consortium (WTC 1) completed
with excellent physical and electrical performance obtained
from single damascene Cu/ultra-low-k interconnects
(k=2.4) Cu metallization was successfully integrated for BEOL
interconnection. The integrated Cu/dielectric metallization
was also proven to be reliable.
Other important results were obtained:
• No integration issues such as voiding in ULK were
observed;
• Optimized etch and clean recipes produced straight trench
profiles without carbon depletion;
• Cu CMP recipe was successfully developed with 1.5psi
down force without any peeling between metallization
layer and dielectrics;
• Dielectric liners improved CMP process margin and
reliability performance.
Supporting Singapore enterprises to
“Grow, Glow, and Globalise”
Growing Enterprises with Technology
Upgrade, or GET-UP, is a pro-active
integrated programme aimed at
boosting the global competitiveness of
local technology-intensive enterprises
to equip them for the knowledgebased
economy. The programme
harnesses the existing schemes of
EDB, SPRING Singapore, IE Singapore
and the technical capabilities of
Agency for Science, Technology and
Research (A*STAR) research institutes
to assist these growing enterprises
(GEs) upgrade & globalise.
One of the key features of the GET-
UP programme is the Technology
for Enterprise Capability Upgrading
“
The researchers
are a big boost to
getting the new chip
to market faster
as the researchers
have both commercial
and technical
expertise.
Pang Tuck Wing ”
CFO, WinEdge & Wireless
(T-UP) scheme, in which highly skilled
research engineers or scientists from
the A*STAR research institutes are
seconded to work full time in the
participating local enterprise. The aim
of the T-UP scheme is to upgrade the
technology and competencies of local
enterprises.
IME is one of the seven research
institutes participating in this scheme.
To date, IME has seconded its research
staff to FTD Technologies, WinEdge &
Wireless, Intelligent Micro Devices
(IMD), Inscope Labs, and AdvanPack
Solutions.
Continued to page 3 >>

page 4
Continued from 3 >>
In the case of FTD Technologies, an
IC design company, IME’s Dr Rajinder
Singh is serving his attachment to
FTD as its Chief Technology Officer.
According to FTD Technologies: “Dr
Rajinder is a role model to FTD’s
technical team by his immense
contribution to process and quality
aspects. He is an important guide
and benchmark who has helped FTD
with new technology initiatives and
is helping FTD to set new standards
internally as well as make us more
competitive in the technology world.
... We do not know how we can
operate without Rajinder in the future.
In a quick time, he has become one of
the most valuable asset and value to
the FTD group of companies and its’
businesses.”
For WinEdge & Wireless, IME’s
seconded researchers M. K. Raja, Dr
Yadav Ram Chandra, and Technical
Advisor D. Pinjala enabled the
company research into innovative
ideas that were previously not
possible. Mr Pang Tuck Wing, CFO
of WinEdge & Wireless, said: “With
this new improved R&D environment
where there is a more vibrant R&D
effort and projects, we could now
have a more holistic approach to the
development of the final products.
This new R&D atmosphere has already
generated some positive results in
our UltraSST chipset solutions where
the holistic approach has made the
solutions more robust.
From the results of our first T-Up
project, which is the development of
the UltraSST phone application, our
company has proceeded with the
Project Jupiter where we have aimed
to innovate a whole new radio system
that is truly low-cost, good powerefficiency,
and provides a robust
wireless communication solution.”
New microlithography
techniques for device
miniaturization
New enabling technology for making 15nm FinFET device,
100nm trenches and 140 nm vias for back-end-of-line
(BEOL) Cu interconnects, and mass producible photonic
crystal devices.
In a bid to satisfy industry demands for smaller, more complex, and cost-efficient
devices, IME researchers are working on new microlithography techniques to
stretch their process technologies to capabilities beyond their limitations.
Novel microlithography techniques for processing silicon wafers were developed
using 248nm scanner. These techniques include Chromeless phase lithography
(CPL), Alternating Phase Shift Mask (PSM), Attenuated PSM technology, and IME’s
very own Dual Exposure With Shift (DEWS) method. These techniques are being
implemented for patterning geometries for sub 130nm technology. Patterning is
being developed for CMOS transistor gates, interconnect trenches and vias, and
photonic crystals.
In microlithography, either optical lithography or E-Beam is used. Optical
lithography is the preferred process because it is faster, has a shorter printing time,
and enables large-scale processing of large wafers.
IME’s capabilities in microlithography
Synergized capabilities to develop patterning technology for 90 nm node using
Phase Shift Mask
Together with Hoya Corporation, Japan, IME developed patterning technology
for 90 nm and smaller technology node. The joint development program (JDP) is
geared towards stretching the limits of the 248 nm exposure tool to pattern 90nm
geometries for production. This JDP also aims at patterning geometries below 90
nm for research purposes.
The designs of phase shift masks are being
done at IME using their in-house expertise.
Valuable learning cycles are being used to
identify the limits of different phase shift
technologies, understand the positive and
negative points of each technique, the
limitations of mask making processes and
improvements of the same.
One of IME’s missions is to support
the electronics industry in Singapore.
We expect more of our researchers
would be seconded to the industry in
the coming months, thereby fulfilling
our mission.
Some examples of different techniques
that are being used to pattern different
structures will be discussed in the
subsequent sections.
15nm fin after patterning using
CPL followed by resist trim

page 5
Chromeless phase lithography
Chromeless phase lithography (CPL) has enabled the
patterning of 40nm fins for FinFET devices, which are 3D
MOS transistors. The Fin Field Effect Transistor (FinFET) is
a promising future CMOS device to control short channel
effects and enhance drive current. The superior leakage
control characteristics make FinFET transistors an attractive
candidate for future nano-scale CMOS generations, which
are expected to be in manufacturing within the next decade.
With proper reticle design and adjustment of exposure dose
conditions, the chromeless phase-shift technology leads 248
nm scanner well below the resolution limit to pattern the 40
nm thin fins for FinFET devices. After an effective resist trim
process this size can be further reduced to 15 nm.
IME’s fin patterning process provides inherent widening of
the Source/Drain (S/D) extension region, which is crucial in
reducing the parasitic S/D resistance.
CPL techniques have also been used for patterning
conventional transistor structures. Promise is seen at
patterning down to 90 nm gate structures.
Alternating phase technology
IME researchers have also developed technologies that use
the conventional alternating phase method to pattern lines,
trenches and holes for BEOL Cu interconnects. Both isolated
and dense patterns for lines, trenches and holes have been
realized in practice. Various optical techniques including
the use of scatter bars have been used to pattern isolated
trenches down to 100 nm and below.
70 nm line 120 nm trench 88 nm trench
Via size 140, 1:1 Pitch,
Alternating Mask
Via size 144 nm,
1:5 Pitch
140nm via at (a) higher density of 1:1 pitch and (b) lesser
density of 1:4 pitch using alternating phase shift mask.
88.3nm
Via
Side
lobe
With side lobes
Attenuated PSM Technology
An effective method with anti side lobe structures have been
put in place by IME to eliminate the appearance of sidelobes
on an attenuated PSM.
Sidelobes are undesired patterns printed on wafers when
attenuated (leaky chrome) masks are used for patterning.
These are caused by negative field amplitude that is large
with attenuated phase shift masks.
A corrective lithography technology, attenuated PSM
improves the edge contrast of features on advanced
integrated circuits (ICs). This method can be used for
structures of any size and shape, and replaces the more
conventional method of using tri-tone masks (much higher
cost), or manipulating undesirable design rules.
DEWS technique for patterning sub-100nm lines
What can normally be achieved by using only the most
advanced and expensive Resolution Enhancement
Techniques, high numerical apertures (NA>

NEWS BITES
page 6
Continued from 5>>
Volume production of ‘high
fill factor’ photonic crystal
devices a reality with 248 nm
Lithography
The use of photonic crystal to
manipulate light in sub micrometer
dimensions is a new approach. The
abilities to manipulate lights such
as guiding and trapping have many
potential applications in optical
communications and optical quantum
computing. In this case, the optical
lithography process (248nm scanner)
is used to realize photonic crystals on
silicon devices.
IME and Toppan Electronics
Singapore develop RFID chip
IME, I 2 R, and Toppan join hands in the development of the RFID system
IME has jointly developed an original 2.45GHz radio frequency identification (RFID)
chip, TesStar (trademark pending) with Toppan Electronics Singapore (TES).
Optical splitter on photonics crystals
(100nm spacing between holes)
Almost all research efforts in photonics
crystals are currently at university
labs, and E-beam lithography is
widely used to pattern the photonic
crystals. Due to inherently long
writing times associated with e-bean
lithography, optical lithography
is preferred, if only the desired
pattern dimensions can be achieved.
IME’s efforts in using the 248 nm
lithography for making photonic
crystal structures is aimed to achieve
this. Research efforts at IME focus
on issues such as patterning square
and triangular lattice arrangement
of photonic crystals, proximity effect,
and patterning line/space and hole
together. As the pursuit includes
patterning smaller periodicity of
structures, photonic crystals can be
made for visible spectrum rather than
the more common infrared.
This small and complex CMOS-based chip consists of radio frequency, analog,
and digital circuits together with efficient power generation circuits, has been
optimized for maximum communication distance. Through this collaboration,
new integrated circuit design
intellectual properties were
TesStar
Antenna
created.
This development was announced
in a joint press conference by
Toppan, IME, and the Institute
of Infocomm Research (I 2 R), who
Prof Er and Dr Tan sealing the
collaborative research effort between
NTU and IME.
RFID tags
RFID
tag
Forging closer ties with university
through Joint Microelectronics
Laboratory (JML)
IME and the Nanyang Technological University
(NTU) signed a memorandum of understanding
to synergize their capabilities in the area
of microelectronics. Three programs were
identified for collaboration: Si micro-photonics;
Micro and nano devices and technologies; and
very high speed integrated circuit for optical
and wireless communication. IME and National
University of Singapore (NUS) also have a JML
which is operational since 2003.
This MOU will further enhance IME’s and NTU’s
research efforts in microelectronics in the
future.

page 7
International recognitions
Prized images in failure analysis
wins international recognition
IME’s Scanning Capacitance Micro-scopy
(SCM) imaging of a 0.8µm n-channel transistor
won the first prize in the 2003 International
Symposium for Testing and Failure Analysis
(ISTFA) conference. This image later went on
to grace the cover of the Electronic Device
Failure Analysis Society (EDFAS) Newsletter in
February 2004.
Different colors represent different material types: purple/pink N, red P, green/
black oxide and heavily doped material.
This is not the first time that IME’s
research work has won an award. In
2002, the SEM micrograph of our 8 layer
metal interconnect structure of Cu dual
damascene garnered the third prize at
the ISTFA Photocontest, and was selected
as the hero picture in the ISTFA 2003
proceedings (right).
IME researcher authored Ultra Large Scale Integration
(ULSI) atlas
Led by two IME staff, Chih-Hang Tung and George T.T. Sheng (retired from IME
in 2000), this atlas was written by three renowned pioneers in their field. This
is the first book available on the subject using fully TEM (Transmission Electron
Microscopy) images. ULSI Semiconductor Technology Atlas uses examples and
TEM micrographs to explain ULSI process technologies and their associated
problems. More than 1,100 TEM images illustrate the science of ULSI.
Dr Lim Thiam Beng, Deputy Director for Industry,
received the IEEE CMPT Outstanding Sustained
Technical Contributions Award
For leading edge research in advanced packaging technologies and
for managing and transferring that research and development to the
microelectronics industry and research organisations worldwide.

NEWS BITES
page 8
Science Outreach program and Graduate
Student Training
Bringing microelectronics closer to
Singapore youths
In staging a series of events in conjunction with Science
‘03 orangised by A*STAR, IME played an important role
in educating Singapore’s youth by lending its expertise
in microelectronics to the public event. The Science ‘03
aimed to create greater awareness of science, technology
and biomedicine, and to inspire and inculcate an interest in
Singapore youths to pursue science as a career.
Setting a precedent in the Science Outreach program
history, a group of students from three secondary schools:
River Valley High School, ShuQun Secondary School, and
Clementi Town Secondary School learnt the basic knowledge
of microelectronics from IME researchers and went ahead to
build three creative science exhibits explaining some of the
scientific and technical principles that go into the making
of silicon chips. The students went further to explain the
concepts of the exhibits in a public exhibition, and to their
peers during an IME open house to students.
Symposium of Microelectronics (SOM
2003) enables young microelectronics
aspirants to share research ideas
As part of IME’s graduate student training program, this
inaugural one day symposium created a new platform for
research students attached to IME to present their research
activities in microelectronics and to network with their
peers.
Students explaining the principles & concepts of their projects to
their peers at the IME open house, another IME initiative to spark
interest in microelectronics among youths.
Owing to the overwhelming response and interest from the
research students and university professors, the symposium
will now be an annual event. The SOM 2004 is scheduled for
4th June 2004 and is currently calling for papers. For more
information, visit www.ime.a-star.edu.sg
IME innovations commercialized by
local enterprise
SiMEMS, a local company, signed a licensing agreement to utilize a special silicon-based
micro-PCR and DNA micro extraction chip technologies. These two technologies were
jointly developed by IME and the National University of Singapore through the Biosensor
Focused Interest Group (BFIG).
These two technologies will give SiMEMS a head-start in bringing their products closer to
the market.
Editorial Board
Advisor: Lim Thiam Beng
Editors: Janet Chang, Teo Keng Hwa
Contributors: Mukherjee-Roy Moitreyee, V. Kripesh, Tsang Chi Fo, Mohandass Sivakumar