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FPGA Based Non Uniform Illumination Correction in Image ...

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Abhishek Acharya,Rajesh Mehra,Vikram S<strong>in</strong>gh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358<br />

ISSN:2229-6093<br />

AHE <strong>in</strong> real time. The Xil<strong>in</strong>x System<br />

Generator, embedded <strong>in</strong> MATLAB<br />

Simul<strong>in</strong>k was used to program the model<br />

and test <strong>in</strong> the <strong>FPGA</strong> board us<strong>in</strong>g the<br />

hardware co-simulation feature tools.<br />

See the comparison Table 1 for<br />

comparison.<br />

8. Future Scope & Recommendations<br />

XSG is a very useful tool for develop<strong>in</strong>g<br />

computer vision algorithms. It could be<br />

described as a timely, advantageous<br />

option for develop<strong>in</strong>g <strong>in</strong> a much more<br />

comfortable way than that permitted by<br />

hardware description languages (HDLs).<br />

The purpose of this paper was to<br />

demonstrate the use of System Generator<br />

to correct the uneven illum<strong>in</strong>ation for<br />

image and video process<strong>in</strong>g. This design<br />

is implemented <strong>in</strong> the device Spartan 3<br />

(xc3s200-5ft256) and Virtex II Pro<br />

(Virtex 2 Pro xc2vp7- 6ff672). Further<br />

some more variants of histogram<br />

equalization can be used. The size of<br />

image under consideration was<br />

1024x1024 maximum, which can be<br />

extended to bigger size. Nature <strong>in</strong>spired<br />

comput<strong>in</strong>g can also be employed to<br />

enhance the quality of image due to<br />

uneven illum<strong>in</strong>ation.<br />

Acknowledgement<br />

The authors would like to thank Dr. S.<br />

Chatterji, Professor and Head,<br />

Electronics & Communication<br />

Eng<strong>in</strong>eer<strong>in</strong>g Department, NITTTR,<br />

Chandigarh for constant encouragement<br />

and guidance dur<strong>in</strong>g this research work.<br />

Author would also like to express<br />

gratitude towards Sh. O. S. Khanna,<br />

Associate Professor <strong>in</strong> the Department of<br />

Electronics & Communication<br />

Eng<strong>in</strong>eer<strong>in</strong>g for giv<strong>in</strong>g valuable<br />

suggestions time to time.<br />

Table 1: Resources of <strong>FPGA</strong> used <strong>in</strong> the implementation of<br />

<strong>Non</strong> <strong>Uniform</strong> <strong>Illum<strong>in</strong>ation</strong> <strong>Correction</strong> Algorithm<br />

Resources Under<br />

Consideration<br />

Spartan 3 xc3s200-5ft256<br />

Virtex 2 Pro xc2vp7-6ff672<br />

Used Available Used Available<br />

Number of Slices 301 1920 296 4928<br />

Number of Slice Flip Flop 440 3840 432 9856<br />

Number of 4 <strong>in</strong>put LUTs 535 3840 529 9856<br />

Number of Bonded IOBs 73 173 69 396<br />

Maximum Frequency 128.54 MHz 151.057 MHz<br />

355

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