FPGA Based Non Uniform Illumination Correction in Image ...

Abhishek Acharya,Rajesh Mehra,Vikram Singh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358
ISSN:2229-6093
(a) Software Component
(b)Hardware Component
Figure 7: Results of Non Uniform Illumination
Correction of Color image (Software and
Hardware Components)
(b) Hardware Component
Figure 7: Results of Non Uniform Illumination
Correction of grey level image (Software and
Hardware Components)
(a)Software Component
Table 1 shows that when design is
implemented on Virtex 2 Pro FPGA, the
number of hardware resources used are
lesser than the Spartan 3 FPGA. As the
clock frequency is increased, the speed
is also improved. Table 2 shows that
number of resources used in our
approach are slightly lesser that the
method used for uneven illumination
correction by color space conversion
only.
7. Conclusion
These results are obtained for image size
of 512x512. The approach discussed
can be used up to the image size of
1024x1024. Here we have discussed the
implementation of the Adaptive
Histogram Equalization algorithm using
Xilinx System Generator 11.1i. This
implementation was realized with a
Xilinx Spartan 3 xc3s200-5ft256 and
Virtex 2 Pro xc2vp7-6ff672 FPGA,
clocked at 130.75 MHz and 155.15
respectively. The use of a
reprogrammable device permits the
continuing parametric changes of the
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