FPGA Based Non Uniform Illumination Correction in Image ...

More documents

Recommendations

Info

Abhishek Acharya,Rajesh Mehra,Vikram Singh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358 ISSN:2229-6093 subtraction, the boundary artifacts can also be reduced. 5. System Generator Based Design It is requirement of an efficient rapid prototyping system to develop an environment targeting the hardware design platform. The used tools are MATLAB R2008a with Simulink from Math-Works [3, 4], System Generator 11.1 for DSP and ISE 11.1 from Xilinx presents such capabilities (figure 1). Although the Xilinx ISE 11.1 foundation software is not directly utilized, it is required due to the fact that it is running in the background when the System Generator blocks are implemented. The System Generator environment allows for the Xilinx line of FPGAs to be interfaced directly with Simulink. In addition there are several cost effective development boards available on the market that can be utilized for the software design development phase. The Xilinx Integrated Software Environment (ISE) is a powerful design environment that is working in the background when implementing System Generator blocks. The ISE environment consists of a set of program modules, written in HDL, that are utilized to create, capture, simulate and implement digital designs in a FPGA target device. The synthesis of these modules creates net list files which serve as the input to the implementation module. After generating these files, the logic design is converted into a physical file that can be downloaded on the target device. Here architecture is proposed for FPGA implementation using Xilinx System Generator block-set. The architecture can only be applied to an image of size 1024 width x 1024 height x 24 bits (for 8 bits x 3 channels). However in order to run images of different sizes the parameters supplied to architecture have to be modified. The design of the component‘s architecture is shown in Figure 3.The logic for the component is encoded in the Xilinx MATLAB Code block, which is a container used for executing user-supplied MATLAB functions within Simulink. This block executes the MATLAB functions to calculate the output during the simulation. However, it must be emphasized that the M-code block only supports a limited subset of the MATLAB language. Figure 3, 4 shows the model that uses the top level HDL module and its Xilinx block-set for Non Uniform Illumination Correction. This model can be used for co-simulation. Once the design is verified, a hardware co-simulation block can be generated and then will be used to program the FPGA for the non uniform illumination correction model implementation. Figure 4 shows the model with the hardware co-simulation block. The bit stream download step is performed using a JTAG cable. Here Xilinx System Generator Token is used which is necessary for the design of such models. Figure 3: Proposed Model for Grey Level Image Processing 352
Abhishek Acharya,Rajesh Mehra,Vikram Singh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358 ISSN:2229-6093 Figure 5: Proposed Model for Color Image Processing After the co-simulation step the VHDL codes were automatically generated from the System Generator block sets. The VHDL codes were then synthesized using Xilinx ISE 11.1i and targeted for Xilinx Spartan3 and Virtex II Pro family.. The optimization setting is for maximum clock speed. Table 1 details the resource requirements of the design. Note that in practice, additional blocks are needed for input/output interfaces, and synchronization. The target FPGA chip is Xilinx Virtex II Pro xc2vp7- 6ff672 and Spartan 3 xc3s200-5 ft256. During the Simulink-to-FPGA design flow, circuit modeling is built up with Simulink basic blocks and Xilinx specified blocks. Input and output data are combined with MATLAB workspace, which is convenient to convert number format and debug. Include results section here Figure 6: JTAG Co-Simulation for Color Image 6. H/W Co-simulation Results Xilinx system generator is a very useful tool for developing computer vision algorithms. It could be described as a timely, advantageous option for developing in a much more comfortable way than that permitted by VHDL or other hardware description languages (HDLs). The Model was compiled successfully in the SIMULINK environment. Hardware co-simulation block was generated without any errors and the processing speed and hardware resources were obtained using the synthesis and ISE implementation tool. Figure 7, 8 are showing that almost there is no difference between result obtained from MATLAB and FPGA. Figure 7 shows the non uniform illumination correction in grey scale image and Figure 8 shows the non uniform illumination correction in color image processing. Figure 5: JTAG Co-Simulation for Grey Level Image 353
Page 1 and 2: Abhishek Acharya,Rajesh Mehra,Vikra
Page 3: Abhishek Acharya,Rajesh Mehra,Vikra

FPGA Based Non Uniform Illumination Correction in Image ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?