FPGA Based Non Uniform Illumination Correction in Image ...

Abhishek Acharya,Rajesh Mehra,Vikram Singh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358
ISSN:2229-6093
subtraction, the boundary artifacts can
also be reduced.
5. System Generator Based Design
It is requirement of an efficient rapid
prototyping system to develop an
environment targeting the hardware
design platform. The used tools are
MATLAB R2008a with Simulink from
Math-Works [3, 4], System Generator
11.1 for DSP and ISE 11.1 from Xilinx
presents such capabilities (figure 1).
Although the Xilinx ISE 11.1 foundation
software is not directly utilized, it is
required due to the fact that it is running
in the background when the System
Generator blocks are implemented. The
System Generator environment allows
for the Xilinx line of FPGAs to be
interfaced directly with Simulink. In
addition there are several cost effective
development boards available on the
market that can be utilized for the
software design development phase.
The Xilinx Integrated Software
Environment (ISE) is a powerful design
environment that is working in the
background when implementing System
Generator blocks. The ISE environment
consists of a set of program modules,
written in HDL, that are utilized to
create, capture, simulate and implement
digital designs in a FPGA target device.
The synthesis of these modules creates
net list files which serve as the input to
the implementation module. After
generating these files, the logic design is
converted into a physical file that can be
downloaded on the target device.
Here architecture is proposed for FPGA
implementation using Xilinx System
Generator block-set. The architecture
can only be applied to an image of size
1024 width x 1024 height x 24 bits (for 8
bits x 3 channels). However in order to
run images of different sizes the
parameters supplied to architecture have
to be modified. The design of the
component‘s architecture is shown in
Figure 3.The logic for the component is
encoded in the Xilinx MATLAB Code
block, which is a container used for
executing user-supplied MATLAB
functions within Simulink. This block
executes the MATLAB functions to
calculate the output during the
simulation. However, it must be
emphasized that the M-code block only
supports a limited subset of the
MATLAB language.
Figure 3, 4 shows the model that uses
the top level HDL module and its Xilinx
block-set for Non Uniform Illumination
Correction. This model can be used for
co-simulation. Once the design is
verified, a hardware co-simulation block
can be generated and then will be used to
program the FPGA for the non uniform
illumination correction model
implementation. Figure 4 shows the
model with the hardware co-simulation
block. The bit stream download step is
performed using a JTAG cable. Here
Xilinx System Generator Token is used
which is necessary for the design of such
models.
Figure 3: Proposed Model for Grey Level Image
Processing
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