FPGA Based Non Uniform Illumination Correction in Image ...

Abhishek Acharya,Rajesh Mehra,Vikram Singh Takher, Int. J. Comp. Tech. Appl., Vol 2 (2), 349-358 

ISSN:2229-6093 

FPGA Based Non Uniform Illumination Correction in 

Image Processing Applications 

Abhishek Acharya 1 , Rajesh Mehra 2 , Vikram Singh Takher 3 

1 Assistant Professor, Department of Electronics & Communication, 

Govt. Engineering College Bikaner 

2 Assistant Professor, Department of Electronics & Communication 

National Institute of Technical Teachers’ Training & Research, Chandigarh 

3 Senior Lecturer, Department of Electronics & Communication 

Govt. Polytechnic College, Bikaner 

1 acharya_g@rediffmail.com 

Abstract 

This paper outlines, an efficient FPGA based 

hardware design for enhancement of color and 

grey scale images in image and video 

processing. The approach used is adaptive 

histogram equalization which works very 

effectively for images captured under extremely 

dark environment as well as non-uniform 

lighting environment where bright regions are 

kept unaffected and dark objects in bright 

background. To meet the speed and area 

constraints, it is important to quantify the 

reduction in processing speed as well as FPGA 

resources that can be achieved if a component 

of the image/video processing system is 

embedded onto a hardware based platform like 

an FPGA. A flexible field programmable gate 

array device lets develop the image processing 

application so that the same logic substrate is 

reconfigured and reused by several custom 

coprocessors during the different operation 

stages of the sequential biometric algorithm. 

The results obtained with this technology reveal 

that a reconfigurable FPGA faces both realtime 

and parallel compute-intensive demands of 

the image enhancement process. 

Keywords: Image Enhancement, Real Time 

Constraints, FPGA, Non-Linear Filtering, 

Adaptive Histogram Equalization, Co- 

Simulation. 

1. Introduction 

Image processing is used to modify 

pictures to improve them (enhancement, 

restoration), extract information 

(analysis, recognition), and change their 

structure (composition, image editing). 

Images can be processed by optical, 

photographic, and electronic means, but 

image processing using digital 

computers is the most common method 

because digital methods are fast, 

flexible, and precise [1]. 

Image processing technology is used by 

planetary scientists to enhance images of 

Mars, Venus, or other planets. Doctors 

use this technology to manipulate CAT 

scans and MRI images. Image 

enhancement improves the quality 

(clarity) of images for human viewing. 

Removing blurring and noise, increasing 

contrast, and revealing details are 

examples of enhancement operations. 

For example, an image might be taken of 

an endothelial cell, which might be of 

low contrast and somewhat blurred. 

Reducing the noise and blurring and 

increasing the contrast range could 

enhance the image. The original image 

might have areas of very high and very 

low intensity, which mask details. An 

adaptive enhancement algorithm reveals 

these details. Adaptive algorithms adjust 

their operation based on the image 

information being processed. In this case 

the mean intensity, contrast, and 

sharpness could be adjusted based on the 

pixel intensity statistics in various areas 

of the image. 

349


ISSN:2229-6093 

2. Real Time Constraints 

In the case of real time Image processing 

application such as automated 

surveillance or radar system number of 

image processing stages and the biggest 

performance bottleneck is the time 

involved in processing the images 

captured by the camera. It is also during 

this preprocessing phase, when a large 

amount of data is being processed, that 

the system seeks to enhance the quality 

of the images captured by removing 

noise or unbalanced Lighting. Meeting 

such real-time constraints is not always 

possible by relying solely on a software 

based solution implemented on a general 

purpose computer (PC). This is because 

there are multiple constraints placed on 

such computers by memory and 

peripheral devices connected to it. 

This leads to explore possible hardware 

based alternatives such as FPGA. Field 

Programmable Gate Arrays (FPGA) is a 

reconfigurable device used to place 

some or all of the system onto the 

hardware. They allow rapid prototyping 

of a system and offer an inexpensive 

option to validate system requirements 

[2]. Placing the functionality of image 

processing applications onto hardware 

allows faster processing as it is no longer 

necessary to split the individual 

instructions into fetch, decode and apply 

cycle needed in the typical processing 

unit of a computer [3]. Moreover, the 

parallelism inherent in most low-level 

image processing operations can now be 

exploited to its full extent as they can be 

partitioned into subsystems, all of which 

can run concurrently with each other. 

Hence the goal of our research will be to 

implement the image processing 

algorithms developed for our 

surveillance system so that the 

processing speed of the components of 

the system is bounded within a specified 

timing constraint considered typical of 

such systems. 

3. Non Uniform Illumination 

Illumination is one of the most 

important factors affecting the 

appearance of an image. It often leads 

to diminished structures or 

inhomogeneous intensities of the image 

due to different texture of the object 

surface and the shadows cast from 

different light source directions. On the 

other hand, uneven background, also 

known as background bias, background 

intensity in-homogeneity, or nonuniform 

background, is the problem that 

an ideal image f is corrupted by an 

uneven background signal b so that the 

observed image I = f +b. Recovering f 

from I is not an easy task when b is 

non-uniform. In essence, both the 

varying illumination and the uneven 

background are inhomogeneous 

intensity patterns that are either 

multiplicative or additive. 

A common issue irrespective of the type 

of camera and method of microscope 

attachment is uneven illumination at the 

edges of the image, otherwise known as 

vignetting. This may be attributed to 

multiple factors from the illumination 

filament, the design of the light path 

between the camera and the 

microscope, or the behavior of the 

imaging device. Conventional digital 

cameras—for example, are not designed 

for microscopy imaging, and many of 

their automatic functions can interfere 

with the correct aperture and exposure 

settings. Common problem irrespective 

of the type of camera and method of 

microscope attachment is uneven 

illumination at the edges of the image, 

known as vignetting (Figure 1, 2) 

350


ISSN:2229-6093 

narrow histogram, thereby achieving 

contrast enhancement. In histogram 

equalization (HE), the goal is to obtain a 

uniform histogram for the output image, 

so that an ―optimal‖ overall contrast is 

perceived. However, the feature of 

interest in an image might need 

enhancement locally. And although there 

was no decrease in delectability of 

simulated low contrast live metastases 

for an experienced reader [4], 

radiologists always find the appearance 

of the HE enhanced images to be 

objectionable in that they often introduce 

undesirable artifacts and noise [6]. 

Figure 1: Image Suffering from Un-even 

illumination (Grey Level Image size - 512x512) 

Figure 2: Image Suffering from Un-even 

illumination (Color Image size - 512x512) 

4. Adaptive Histogram Equalization 

The histogram of an image represents 

the relative frequency of occurrence of 

gray levels within an image. Histogram 

modeling techniques modify an image so 

that its histogram has a desired shape. 

This is useful in stretching the lowcontrast 

levels of an image with a 

For images which contain local regions 

of low contrast bright or dark regions, 

global histogram equalization won't 

work effectively. A modification of 

histogram equalization called the 

Adaptive Histogram Equalization can be 

used on such images for better results. 

Adaptive histogram equalization works 

by considering only small regions and 

based on their local Cumulative Density 

Function, performs contrast 

enhancement of those regions. 

Adaptive Histogram Equalization (AHE) 

computes the histogram of a local 

window centered at a given pixel to 

determine the mapping for that pixel, 

which provides a local contrast 

enhancement. However, the 

enhancement is so strong that two major 

problems can arise: noise amplification 

in ―flat‖ regions of the image and ―ring‖ 

artifacts at strong edges [09]. A 

generalization of AHE, contrast limiting 

AHE (CLAHE) has more flexibility in 

choosing the local histogram mapping 

function. By selecting the clipping level 

of the histogram, undesired noise 

amplification can be reduced. In 

addition, by method of background 

351


ISSN:2229-6093 

subtraction, the boundary artifacts can 

also be reduced. 

5. System Generator Based Design 

It is requirement of an efficient rapid 

prototyping system to develop an 

environment targeting the hardware 

design platform. The used tools are 

MATLAB R2008a with Simulink from 

Math-Works [3, 4], System Generator 

11.1 for DSP and ISE 11.1 from Xilinx 

presents such capabilities (figure 1). 

Although the Xilinx ISE 11.1 foundation 

software is not directly utilized, it is 

required due to the fact that it is running 

in the background when the System 

Generator blocks are implemented. The 

System Generator environment allows 

for the Xilinx line of FPGAs to be 

interfaced directly with Simulink. In 

addition there are several cost effective 

development boards available on the 

market that can be utilized for the 

software design development phase. 

The Xilinx Integrated Software 

Environment (ISE) is a powerful design 

environment that is working in the 

background when implementing System 

Generator blocks. The ISE environment 

consists of a set of program modules, 

written in HDL, that are utilized to 

create, capture, simulate and implement 

digital designs in a FPGA target device. 

The synthesis of these modules creates 

net list files which serve as the input to 

the implementation module. After 

generating these files, the logic design is 

converted into a physical file that can be 

downloaded on the target device. 

Here architecture is proposed for FPGA 

implementation using Xilinx System 

Generator block-set. The architecture 

can only be applied to an image of size 

1024 width x 1024 height x 24 bits (for 8 

bits x 3 channels). However in order to 

run images of different sizes the 

parameters supplied to architecture have 

to be modified. The design of the 

component‘s architecture is shown in 

Figure 3.The logic for the component is 

encoded in the Xilinx MATLAB Code 

block, which is a container used for 

executing user-supplied MATLAB 

functions within Simulink. This block 

executes the MATLAB functions to 

calculate the output during the 

simulation. However, it must be 

emphasized that the M-code block only 

supports a limited subset of the 

MATLAB language. 

Figure 3, 4 shows the model that uses 

the top level HDL module and its Xilinx 

block-set for Non Uniform Illumination 

Correction. This model can be used for 

co-simulation. Once the design is 

verified, a hardware co-simulation block 

can be generated and then will be used to 

program the FPGA for the non uniform 

illumination correction model 

implementation. Figure 4 shows the 

model with the hardware co-simulation 

block. The bit stream download step is 

performed using a JTAG cable. Here 

Xilinx System Generator Token is used 

which is necessary for the design of such 

models. 

Figure 3: Proposed Model for Grey Level Image 

Processing 

352


ISSN:2229-6093 

Figure 5: Proposed Model for Color Image 


After the co-simulation step the VHDL 

codes were automatically generated from 

the System Generator block sets. The 

VHDL codes were then synthesized 

using Xilinx ISE 11.1i and targeted for 

Xilinx Spartan3 and Virtex II Pro 

family.. The optimization setting is for 

maximum clock speed. Table 1 details 

the resource requirements of the design. 

Note that in practice, additional blocks 

are needed for input/output interfaces, 

and synchronization. The target FPGA 

chip is Xilinx Virtex II Pro xc2vp7- 

6ff672 and Spartan 3 xc3s200-5 ft256. 

During the Simulink-to-FPGA design 

flow, circuit modeling is built up with 

Simulink basic blocks and Xilinx 

specified blocks. Input and output data 

are combined with MATLAB 

workspace, which is convenient to 

convert number format and debug. 

Include results section here 

Figure 6: JTAG Co-Simulation for Color Image 

6. H/W Co-simulation Results 

Xilinx system generator is a very useful 

tool for developing computer vision 

algorithms. It could be described as a 

timely, advantageous option for 

developing in a much more comfortable 

way than that permitted by VHDL or 

other hardware description languages 

(HDLs). The Model was compiled 

successfully in the SIMULINK 

environment. 

Hardware co-simulation block was 

generated without any errors and the 

processing speed and hardware resources 

were obtained using the synthesis and 

ISE implementation tool. Figure 7, 8 are 

showing that almost there is no 

difference between result obtained from 

MATLAB and FPGA. Figure 7 shows 

the non uniform illumination correction 

in grey scale image and Figure 8 shows 

the non uniform illumination correction 

in color image processing. 

Figure 5: JTAG Co-Simulation for 

Grey Level Image 

353


ISSN:2229-6093 

(a) Software Component 

(b)Hardware Component 

Figure 7: Results of Non Uniform Illumination 

Correction of Color image (Software and 

Hardware Components) 

(b) Hardware Component 

Figure 7: Results of Non Uniform Illumination 

Correction of grey level image (Software and 

Hardware Components) 

(a)Software Component 

Table 1 shows that when design is 

implemented on Virtex 2 Pro FPGA, the 

number of hardware resources used are 

lesser than the Spartan 3 FPGA. As the 

clock frequency is increased, the speed 

is also improved. Table 2 shows that 

number of resources used in our 

approach are slightly lesser that the 

method used for uneven illumination 

correction by color space conversion 

only. 

7. Conclusion 

These results are obtained for image size 

of 512x512. The approach discussed 

can be used up to the image size of 

1024x1024. Here we have discussed the 

implementation of the Adaptive 

Histogram Equalization algorithm using 

Xilinx System Generator 11.1i. This 

implementation was realized with a 

Xilinx Spartan 3 xc3s200-5ft256 and 

Virtex 2 Pro xc2vp7-6ff672 FPGA, 

clocked at 130.75 MHz and 155.15 

respectively. The use of a 

reprogrammable device permits the 

continuing parametric changes of the 

354


ISSN:2229-6093 

AHE in real time. The Xilinx System 

Generator, embedded in MATLAB 

Simulink was used to program the model 

and test in the FPGA board using the 

hardware co-simulation feature tools. 

See the comparison Table 1 for 

comparison. 

8. Future Scope & Recommendations 

XSG is a very useful tool for developing 

computer vision algorithms. It could be 

described as a timely, advantageous 

option for developing in a much more 

comfortable way than that permitted by 

hardware description languages (HDLs). 

The purpose of this paper was to 

demonstrate the use of System Generator 

to correct the uneven illumination for 

image and video processing. This design 

is implemented in the device Spartan 3 

(xc3s200-5ft256) and Virtex II Pro 

(Virtex 2 Pro xc2vp7- 6ff672). Further 

some more variants of histogram 

equalization can be used. The size of 

image under consideration was 

1024x1024 maximum, which can be 

extended to bigger size. Nature inspired 

computing can also be employed to 

enhance the quality of image due to 

uneven illumination. 

Acknowledgement 

The authors would like to thank Dr. S. 

Chatterji, Professor and Head, 

Electronics & Communication 

Engineering Department, NITTTR, 

Chandigarh for constant encouragement 

and guidance during this research work. 

Author would also like to express 

gratitude towards Sh. O. S. Khanna, 

Associate Professor in the Department of 

Electronics & Communication 

Engineering for giving valuable 

suggestions time to time. 

Table 1: Resources of FPGA used in the implementation of 

Non Uniform Illumination Correction Algorithm 

Resources Under 

Consideration 

Spartan 3 xc3s200-5ft256 

Virtex 2 Pro xc2vp7-6ff672 

Used Available Used Available 

Number of Slices 301 1920 296 4928 

Number of Slice Flip Flop 440 3840 432 9856 

Number of 4 input LUTs 535 3840 529 9856 

Number of Bonded IOBs 73 173 69 396 

Maximum Frequency 128.54 MHz 151.057 MHz 

355


ISSN:2229-6093 

Table 2: Comparison of Resources of FPGA (Spartan 3) used in the implementation of 

Non Uniform Illumination Correction Algorithm with existing Method 

Resources Under 

Consideration 

Our Approach (AHE) 

Existing Method (CSC) 

Used Available Used Available 

Number of Slices 301 1920 307 1920 

Number of Slice Flip Flop 440 3840 446 3840 

Number of 4 input LUTs 535 3840 545 3840 

Number of Bonded IOBs 73 173 75 173 

Maximum Frequency 128.54 MHz 129.721 

Reference: 

[1]. Carl Steven Rapp, Image Processing and Image 

Enhancement, East Tennessee University, 

Johnson City, Texas. 

[2]. Kiran, M.; Kan Mei War; Lim Mei Kuan; Liang 

Kim Meng; Lai Weng Kin, Implementing image 

processing algorithms using ‗Hardware in the 

loop‘ approach, IEEE Conference on Electronic 

Design, December 1-3, 2008, Penang, Malaysia 

pp 1-6. 

[3]. T. Moreo, P. N. Lorente, F. S. Valles, J. S. Muro, 

C. F. Andrés, Experiences on developing 

computer vision hardware algorithms using 

Xilinx system generators, Elsevier Journal of 

Microprocessors and Microsystems 29, 2005 pp 

411- 419. 

[4]. Yinpeng Jin, Laura Fayad, Andrew Laine, 

Contrast Enhancement by Multi-scale Adaptive 

Histogram Equalization, Department of 

Biomedical Engineering, Columbia University, 

New York, NY. 

[5]. Kassem, M. Hamad, E. Haidamous, Image 

Compression on FPGA using DCT, IEEE 

Conference on Advances in Computational Tools 

for Engineering Applications, 2009 Zouk 

Mosbeh, Lebanon pp 220-223. 

[6]. T. Saidani , D. Dia, W. Elhamzi, M. Atri and R. 

Tourki, Hardware Co-simulation For Video 

Processing Using Xilinx System Generator, 

Proceedings of the World Congress on 

Engineering 2009 Vol I, London, UK pp 151 - 

155. 

[7]. Alba M. Sánchez G., Ricardo Alvarez G., Sully 

Sánchez G.; FCC and FCE BUAP, Architecture 

for filtering images using Xilinx System 

Generator, International Journal of Mathematics 

& Computers in Simulation, Issue 2, Volume 1, 

2007 pp 101 – 107. 

[8]. N. Shirazi, J. Ballagh, Put Hardware in the Loop 

with Xilinx System Generator for DSP, Xcell 

Journal, Fall 2003 pp 01-03. 

[9]. Sima Haifeng Liu Lanlan, Local Adaptive Image 

Enhancement Based on HSI Space, Third 

International Symposium on Computer Science 

and Computational Technology(ISCSCT ‘10), 

Jiaozuo, P. R. China, 14-15,August 2010, pp. 

253-255. 

[10]. Chi-Jeng Chang, Pei-Yung Hsiao, Zen-Yi Huang, 

Integrated Operation of Image Capturing and 

Processing in FPGA, IJCSNS, Journal of 

Computer Science and Network Security, VOL.6 

No.1A, January 2006 pp 173 - 180. 

356


ISSN:2229-6093 

[11]. K.T. Gribbon, D.G. Bailey, A. Bainbridge-Smith, 

‗Development Issues in Using FPGAs for Image 

Processing‘, Proceedings of Image and Vision 

Computing New Zealand 2007, pp. 217–222. 

[12]. K. T. Gribbon, D. G. Bailey, and C. T. Johnston, 

"Using Design Patterns for Image Processing 

Algorithm Development on FPGAs," in Proc. of 

the Third IEEE International Workshop on 

Electronic Design, Test, and Applications 

(DELTA 2006), Kuala Lumpur, Malaysia 2006, 

pp. 47-53. 

[13]. Yasuyuki Matsushita, Ko Nishino, Katsushi 

Ikeuchi Masao Sakauchi, Illumination 

normalization with Time-Dependent Intrinsic 

Images for Video Surveillance, IEEE 

Transactions on Pattern Analysis and Machine 

Intelligence, VOL. 26, No. 10, October 2004 pp 

1336-1347. 

[14]. T. Latha, M. Sasi kumar, A. Albert Raj, FPGA 

Based Digital Image Restoration Using Multi- 

Resolution Transform Based Filtering, IET-UK 

International Conference on Information and 

Communication Technology in Electrical 

Sciences 2007 pp 625 - 629. 

[15]. Daniel E. Michek, Developing Image Processing 

Algorithms using System Generator, Xcell 

Journal, fall winter 2004 pp 01-03. 

[16]. S. Lam, H. De Smet ―Frame Resolution 

Scalability in Wavelet Based Multiple Line 

Addressing for Passive Matrix Displays‖. IEEE 

Society for Information Displays 2006, 

International Symposium Digest of Technical 

Papers. Vol. 37. 2006. pp. 355-358. 

[17]. L.M. Reyneri, A Simulink-based hybrid codesign 

tool for rapid prototyping of FPGA‘s in 

signal processing systems, Elsevier Journal of 

Microprocessors and Microsystems 28 2004, pp 

273–289. 

[18]. K. Benkrid, A. Benkrid, S. Belkacemi, Efficient 

FPGA hardware development: A multi-language 

approach, Elsevier Journal of Systems 

Architecture 2007 pp 184–209. 

[19]. Nicolas Ley, Christian Weigel and Markus 

Mehnert, GPU-Based Background Illumination 

Correction, Consumer Electronics, IEEE 

International Symposium on Consumer 

Electronics 2007, pp 1-5. 

[20]. Lopez, M.; Canto, E.; Fons, M, Hardware- 

Software Co-design of a Fingerprint Image 

Enhancement Algorithm, IEEE Conference on 

Industrial Electronics, 2006 pp 3496-3501. 

[21]. Thomas W. Fry, Scott Hauck, SPIHT Image 

Compression on FPGAs, Circuits and Systems 

for Video Technology, IEEE Transactions on 

Image Processing, 2005 pp 1138 - 1147. 

[22]. Daggu Venkateshwar Rao, Shruti Patil, Naveen 

Anne Babu and V Muthukumar, Implementation 

and Evaluation of Image Processing Algorithms 

on Reconfigurable Architecture using C-based 

Hardware Descriptive Languages, International 

Journal of Theoretical and Applied Computer 

Sciences, Volume 1 Number 1 (2006) pp 9–34. 

[23]. Rajan, S.Ravi, FPGA Based Hardware 

Implementation of Image Filter with Dynamic 

Reconfiguration Architecture, International 

Journal of Computer Science and Network 

Security, VOL.6 No.12, December 2006 pp 121 - 

127. 

[24]. Bei Tang, Guillermo Sapiro, Vicent Caselles, 

Color Image Enhancement via Chromaticity 

Diffusion, Circuits and Systems for Video 

Technology, IEEE Transactions on Image 

Processing, VOL. 10, 2001 pp 701-707. 

[25]. Sally L. Wood, Chris Dick, Concepts of 

Parallelism In An Introductory Computer 

Architecture Courses With FPGA Laboratories, 

34th ASEE/IEEE Frontiers in Education 

Conference, October, 2004, Savannah, GA pp 15 

–21. 

[26]. Mike Hodson, Prototyping Image Processing 

Applications, Image Processing Techniques Ltd., 

Xcell Journal, Fourth Quarter 2007 pp 31-33. 

[27]. D.Crookes, K.Benkrid, A.Bouridane, K.Alotaibi 

and A.Benkrid, Design and implementation of a 

high level programming environment for FPGAbased 

image processing, IPA99 Special Section, 

IEE Proc.-Vis. Image Signal Process., Vol. 147, 

No. 4, 2000 pp 377 - 384. 

[28]. M. Sapkal, Mousami Munot, Dr. M. A. Joshi, R' 

G'B' to Y'CbCr Color Space Conversion Using 

FPGA, IET International Conference on 

Wireless, Mobile and Multimedia Networks, 

2008 pp 255 - 258. 

[29]. Charles D. Norton, Thomas A. Werne, Paula J. 

Pingree, Sven Geier, An Evaluation of the Xilinx 

Virtex-4 FPGA for On-Board Processing in an 

Advanced Imaging System, IEEEAC paper 1030, 

Version 3 Aerospace conference, 2009 IEEE pp 

1-9. 

[30]. Saegusa, T. Maruyama, T. Yamaguchi, Y. 

Tsukuba Univ., Tsukuba, How fast is an FPGA in 

image processing, IEEE International Conference 

on Field Programmable Logic and Applications, 

2008 pp 77 - 82. 

357


ISSN:2229-6093 

[31]. Chakalabbi Jairaj M., Shaila Subbaraman, QMF 

Implementation using Xilinx System Generator 

(XSG), 3rd IEEE International Conference on 

Computer Science and Information Technology , 

2010 pp 142 - 145. 

[32]. Yadong Wu, Zhiqin Liu, Yongguo Han, 

Hongying Zhang, An Image illumination 

Correction Algorithm based on Tone Mapping, 

IEEE 3rd International Congress on Image and 

Signal Processing (CISP2010), pp 648-648 

[33]. WANG Zhiming, TAO Jianhua, A Fast 

Implementation of Adaptive Histogram 

Equalization, IEEE International Conference on 

Signal Processing, 2006 pp 52-55. 

[34]. I. Alston, B. Madahar, From C to netlists: 

hardware engineering for software engineers?, 

Electronics and Communication Engineering 

Journal 14 (4) (2002) 165–173. 

[35]. I.S. Uzun, A.A.A. Bouridane, FPGA 

implementations of fast Fourier transforms for 

real-time signal and image processing, IEEE 

International Conference on Field-Programmable 

Technology (FPT), 2003, pp. 102–109. 

areas of interest are VLSI Design and its application 

in signal and image processing systems Mr. Acharya 

has been awarded by various organizations for 

excellence in teaching learning process. 

Rajesh Mehra: Mr. Rajesh Mehra 

is currently Assistant Professor at National Institute 

of Technical Teachers’ Training & Research, 

Chandigarh, India. He is pursuing his PhD from 

Panjab University, Chandigarh, India. He has 

completed his M.E. from NITTTR, Chandigarh, India 

and B. Tech from NIT, Jalandhar, India. Mr. Mehra 

has 15 years of academic experience. He has 

authored more than 40 research papers in national, 

international conferences and reputed journals. His 

interest areas are VLSI Design, Embedded System 

Design, Advanced Digital Signal Processing, 

Wireless & Mobile Communication and Digital 

System Design. Mr. Mehra is life member of ISTE. 

[36]. A. T. Moreo, P. N. Lorente, F. S. Valles, J. S. 

Muro, C. F. Andrés, Experiences on developing 

computer vision hardware algorithms using 

Xilinx system generators, Microprocessors and 

Microsystems 29, (2005) 411- 419. 

[37]. C. Vicente-Chicote, A. Toledo, P. Sanchez- 

Palma, Image Processing Application 

Development: From Rapid Prototyping to 

SW/HW Co-simulation and Automated Code 

Generation, Springer-Verlag, pp.659-666, 2005. 

Authors Biography: 

Vikram Singh Takher: Mr. Vikram 

Singh Takher is currently Lecturer (senior scale) at 

Govt. Polytechnic College, Bikaner, Rajasthan, 

India. He is pursuing his M.E. from NITTTR, 

Chandigarh, India. He has completed his B.E. from 

MNIT, Jaipur, Rajasthan, India. Mr. Takher has 14 

years of academic experience. He has authored 03 

research papers in national conferences and 04 

research papers in international conferences. Mr. 

Takher’s interest areas are VLSI Design, Embedded 

System Design & Advanced Digital Signal 


Abhishek Acharya: Mr. Abhishek 

Acharya is currently working as Assistant Professor 

in the Department of Electronics & Communication 

at Govt. Engineering College Bikaner. He received 

his B.E. from University of Rajasthan, Jaipur and he 

has been a M.E Scholar of NITTTR Chandigarh. He 

has around 8 years of teaching experience at UG/PG 

level. He has authored around 15research papers to 

various international and national conferences. His 

358

FPGA Based Non Uniform Illumination Correction in Image ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?