Implementation of Wallace Tree Multiplier Using Compressor

Naveen Kr.Gahlan et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1194-1199
ISSN:2229-6093
8×8 WTM 4.961 69.917 2.008
8×8 WTM using 5:2
& 4:2Compressor
8×8 WTM using 6:2
& 4:2Compressor
8×8 WTM using 7:2
& 4:2Compressor
5.178 74.642 2.128
5.390 74.309 1.765
5.698 74.278 1.526
Table.2 Simulation Result using Cadence
VII. CONCLUSIONS
The Wallace tree multipliers can be solved & analyzed
using a new modified method of Wallace tree construction
using compressors. The modified tree has a slightly smaller
critical path, a slightly larger wiring overhead but gives high
speed.. This modified design of multiplier which consist of
7:2 compressor ,6:2 compressor ,5:2 compressor ,4:2
compressor, 3:2 compressor, full adders and reduced no. of
half adder and reduces the complexity and reduce the time
delay.
Multiplier using Compressor have small increase in area and
power but the time delay is less compare to conventional
Wallace Tree Multiplier. As the Compressor order is
increased the time delay reduces respectively. Hence for
small delay requirement Wallace Tree Multiplier using
compressor is suggested.
References
[1] Dursun Baran, Mustafa Aktan and Vojin G. Oklobdzija,” Multiplier
Structures for Low Power Applications in Deep-CMOS”, IEEE
International Symposium on Circuits and Systems (ISCAS), 2011
[2] S. A. Shinde, R. K. Kamat,” FPGA based Improved Hardware
Implementation of Booth Wallace Multiplier using Handel C”,
ELEKTRONIKA IR ELEKTROTECHNIKA,Page No.71-74, 2011
[3] P.V. Rao, Cyril Prassana Raj P,S. Ravi,“VLSI Design and Analysis of
Multipliers for Low Power”,IEEE 2009 Fifth International
Conference On Intelligence Information Hiding and Multipedia
Signal processing,pp. 1354-1357,2009
[4] Soojin Kim, Kyeongsoon Cho,” Design of High-speed Modified
Booth Multipliers Operating at GHz Ranges”,World Academy of
Science ,Engineering and Technology,2010.
[5] Sumit R. Vaidya, D.R. Dandekar,”Delay-power Performance
Comparison of Multipliers in VLSI Circuit Design”, IJCNC, vol.
2,No. 4,pp. 47-56,July 2010
[6] Issam S. Abu-Khater, Abdellatif Bellaouar, M. I. Elmasry, “Circuit
Techniques for CMOS Low-Power High-Performance Multipliers”,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO.
10,Page No.1535-1546, OCTOBER 1996
[7] Prvinkumar G. Parate, Prafulla S. Patil, Dr (Mrs) S. Subbaraman
“ASIC Implementation of 4 Bit Multipliers”,IEEE First International
Conference on Emerging Trends in Engineering and Technology, pp.
408-413,2008
[8] Kiaml Z. Pekmestzi,” Multiplexer-Based Array Multipliers”, IEEE
TRANSACTIONS ON COMPUTERS, VOL. 48, NO. 1, JANUARY
1999.
[9] N. Ravi, A.Satish , Dr. T. Jayachandra Prasad, Dr. T. Subba Rao,”A
New Design for Array multiplier with Trade Off in power and Area”,
IJCSI ,vol. 8,issue 3, May 2011
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