Implementation of Wallace Tree Multiplier Using Compressor

Naveen Kr.Gahlan et al ,Int.J.Computer Technology & Applications,Vol 3 (3), 1194-1199
ISSN:2229-6093
Fig.8(b) 6:2 compressor architecture
Fig.9. Simulation result of 8 bit Wallace Tree Multiplier
VI.
MULTIPLIER PERFORMANCE AND
COMPARISON
The performance analysis of Wallace Tree Multiplier using
conventional method and using Compressor are listed in
Tables 1-2 in terms of number of occupied slices, number
of 4 input LUT using Xilinx and power, delay using
Cadence tool. The simulation results of number of occupied
slices and number of 4 input LUT are shown in Table-1.
The simulation results of power and delay are shown in
Table-2. Here Wallace Tree Multiplier represents as WTM
in Table 1-2.
Fig.8(c). RTL Schematic of 7:2 Compressor
V. VERIFICATION OF SIMULATION
Xilinx is powerful simulation tool for simulate and compile
Verilog/VHDL code efficiently. All the basic modules designed
for Wallace tree multiplier are compiled and tested vigorously
for functional correctness using waveforms. The complete
circuit of 8×8 bit Wallace tree multiplier is described in
Verilog, as a structural component. The hieratical structure is
created and the complete simulation can be observed. Fig.3
shows the waveform simulation result for the Wallace tree
multiplier.
Wallace Tree
Multiplier 4×4(WTM)
Number of
Number of
4 input LUTs occupied Slices
4×4 WTM 27 15
4×4 WTM using 4:2
Compressor
4×4 WTM using 5:2
Compressor
39 20
37 20
8×8 WTM 139 75
8×8 WTM using 5:2 &
4 :2 Compressor
8×8 WTM using 6:2 &
4:2 Compressor
8×8 WTM using 7:2 &
4:2 Compressor
Wallace Tree
Multiplier(WTM)
Table.1 Simulation Result using Xilinx
Leakage
Power
Power
(uW)
139 75
139 76
140 74
Dynamic
Power
Time Dealy
(psec)
4×4 WTM 1.078 10.835 0.921
4×4 WTM using 4:2
Compressor
4×4 WTM using 5:2
Compressor
1.168 10.399 0.962
1.080 10.746 0.896
IJCTA | MAY-JUNE 2012
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