3D System, SoC and SoP - KTH

Performance and cost trade-offs for
SoC, SoP and 3-D integration
Prof. Li-Rong Zheng
Prof. Hannu Tenhunen,
Roshan Weerasekera
Laboratory of Electronics and Computer Systems
Royal Institute of Technology (KTH)
SE-164 40 Kista-Stockholm, Sweden
(Tutorial Workshop, ISSCC 2007, )
KTH/ESD/HT 02/04/2008 1

Outline
•New Paradigms for System Integration: SoC and SoP
•SoP vs. SoC? (the opportunity of SoP)
•Future SoP Challenges
KTH/ESD/HT 02/04/2008 2

Evolution of Integrated Circuits
The System on a Chip Paradigm
Yesterday’s chip is today’s functional block!
System-on
on-a-chip will be the final destination!
20K gates
Schematics
& simulation
50K gates
Schematics
& Synthesis
500k gates
Simulation,
Emulation,
Synthesis,
Formal equivalence
2.5 million gates
New Design Paradigm
SoC!
SoC!
3.0μ 1.0μ 0.5μ 0.2μ
Source: ICE
KTH/ESD/HT 02/04/2008 3

System Implementation – Option 1: SoC
SoC (System-on-Chip):
– A single chip integrated system or a system platform, including system hardware
(digital, analog/RF) and embedded software/OS
– Based on Deep Submicron (DSM) CMOS technology
KTH/ESD/HT 02/04/2008 4

System Implementation – Option 2: SoP
SoP (System-on-Package):
– A convergent microsystem integrated (assembly) on an interconnect microboard; also a
platform based system, including hardware (digital, analog/RF, MEMS) and embedded
software/OS
– Based on advanced packaging and assembly technologies;
– Overcome formidable integration barriers without compromising individual chip or
component technologies
KTH/ESD/HT 02/04/2008 5

The Electronic Package Evolution: The Future, from MCM to SoP
System-on-Package
Multi-Chip Module
• Integrated L,R,C instead
of embedded L,R,C
• Low inductance bonding
instead of wire bonding
• Technology fusion (RF,
Digital, MEMS, Optical)
KTH/ESD/HT 02/04/2008 6

SoP
(Bi)CMOS RF
ASIC
Mixed-signal CMOS
ASIC
MEMS
MCM-D interconnect
technology
- glass substrate, etc
- Cu interconnections
MCM substrate
antenna
MCM-D passives
1nF/mm 2
Q factors up to 50,
frequencies up to 30 GHz
lowpass
3dB = 12 GHz
f -3dB
KTH/ESD/HT 02/04/2008 7

Is the performance of SoC better than SoP ?
???
L=0.12µm
Wires in SoC: small and
resistive, signal speed 30-
70ps/mm
Wires in SoP: fat and lower
resistive (LC transmission lines),
signal speed 10-20ps/mm
Performance of SoC is not necessary better!
KTH/ESD/HT 02/04/2008 8

System Implementation – Option 3: SiP
Advanced technology to incorporate
multiple components into a single
package.
You can mix a variety of components
such as CPU, logic, analog and memory
functions, Heterogeneous Integration
Reducing overall system size.
KTH/ESD/HT 02/04/2008 9

Research Results: Single Level Integrated Packaging Module
Decoupling Capacitor High-Q Inductance
Power distribution
Signal distribution
RF IC
Digital IC
Digital IC
Analog IC
Dielectrics (10~20μm)
Base-Substrate
Prototype Modules
~GHz off-chip data rate
per pin measured
L. -R. Zheng et al, IEEE Trans-AVP, no4. 2001
KTH/ESD/HT 02/04/2008 10

3D-Integration Options
KTH/ESD/HT 02/04/2008 11

3D integration methods
3D Die Stacking
(System in Package)
3D Wafer-Level-Processing
3D-W2W bonding
3D-D2W bonding
KTH/ESD/HT 02/04/2008 12

The need of Cost Analysis: Design Process
System Specification
Performance
Estimation
Cost Analysis
Initial Synthesis
System Partitioning
2D
3D
Implementation:
Interconnection and
Technology Mapping
Meigen Shen et.al.
SoC
SoP
Chip design
SiP W2W D2W
Prototyping
Software Design
Resource and
Design Library
KTH/ESD/HT 02/04/2008 13

Noise: A Key Stopper in Mixed-Signal Systems
KTH/ESD/HT 02/04/2008 14

Why Power Distribution – An ITRS View
Chip power for future ULSI
Chip technology 0.25um 0.18um 0.13um 0.10um 0.07um
Chip Frequency (MHz) 450 600 800 1000 1100
Max. Chip Power (W) 100 120 140 160 180
Max current (A) 40.3 66.7 93.3 133.3 180.0
Power Supply (V) 2.5 1.8 1.5 1.2 0.9
Current density (A/cm2) 13.4 18.5 21.8 25.6 29.0
Power Loss:
DC voltage drop: ΔV=RI
Switching noise: ΔV=L dI/dt
Technology Scaling of Power Distribution
Parameters
Wire Pitch x 0.87
Chip Edge y 1.06
IR/V 1/x 1.15 y 2 /x 3 1.71
(L/V)dI/dt (package) 1/x 1.15 y 2 /x 3 1.71
(L/V)dI/dt (on-chip) 1/x 2 1.32 y 2 /x 4 1.96
Device Per year Chip Per year
The future Challenge:
how to delivery 100A current at ~1V from board to chip ?
KTH/ESD/HT 02/04/2008 15

Task of Power Distribution Design: Zs< Ztarget (in Freq
domain)
System level power
delivery network
Impedance
(ohms)
0.025
0.020
0.015
0.010
0.005
Target
Impedance
Zs
Low-Frequency
Power Regulator
Mid-Frequency
SCM/MCM on Board
High-Frequency on-chip global
and semi-global lines
High-Frequency
Chip on SCM/MCM
0.000
10
0
10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10
Frequency (Hz)
KTH/ESD/HT 02/04/2008 16

Substrate Noise in SoC
Generation
-+
in
GENERATION MECHANISMS
1. Impact Ionization
2. Source/Drain Coupling
3. Ground Bounce
Vss
out
Vdd
p+
n+
- - - - +++
-
n+
p+ p+ n+
+
p-well
n-well
P- substrate
Impact
Propagation
Three aspects: Generation, propagation, impact
TO ANALOG & RF
CIRCUITS
KTH/ESD/HT 02/04/2008 17

Trade-off analysis methodology
KTH/ESD/HT 02/04/2008 18

Challenges in Trade-off Analysis
KTH/ESD/HT 02/04/2008 19

The Design Flow
Summary:
Step 1: Estimate Area of Each Module: IP
modules, Memory, Analog/RF
Step 2: Make Implementation Plans: System
Partition Plan, Placement Plan,
Interconnect and Package Plan, Mixed-
Signal Isolation Plan; (also compute the
total area of each chip)
Step 3: Compute Mixed-Signal Performance; if
isolation YES, go to Step 4; if NOT,
change a new isolation and do Step 3
again.
Step 4: Compute the Cost for this
implementation Plan
Step 5: Do the Step 2-4 for other Possible
Implementation Plans
Step 6: Select one low cost Implementation Plan
as the Target Implementation for the
System
Design entry
( Technolgy Description, System Description,
Interconnect Description,Packaging Description )
Constraint
(isolation,dB)
System partitioning
plan
Placement plan
Constraint
satisfied?
Cost estimation
All partitions
placements
generated
End
KTH/ESD/HT 02/04/2008 20
1
Area estimation
Mixed signal system
isolation estimation
Yes
Yes
No
No
2
3
4
5
6

How to Estimate the Module Size?
1. If It was Provided by the IP vendors or A Re-Used Module:
- Use technology scaling and map to the target foundry
2. Otherwise, use Rent’s Rule based Technique
-The module size can be either interconnection dominated (with
high interconnectivity) or transistor dominated (less
interconnectivity).
3. Analog/RF modules are not scalable.
- Full-custom design experience are needed (estimated from
expertise or obtained directly from real designs)
KTH/ESD/HT 02/04/2008 21

Performance Estimations
Size estimation= (wirleng demand , standard library cell)
wire limited chip:
A
die
=
N
g
⋅ d
2
g
f
R
e
g avg w
2
d g = Asub
= Nc
⋅ Fp
w w
n
P
Power estimation=dyanmic power+leakage power+shor-circuit power
F
p
F c R
=
F c + 1 ewn
mN pP
w
w
P
dynamic
2
= αCV
dd f Pstat Ilekage ∗Vdd
tr + tf
= Pdp = ∗Vdd
∗ Ipeak ∗ f
2
Delay estimation= logic delay(critical path)+global delay
T
cycle
T
=
log ic
+ T
global
+ Tset
_
1 − skew
up
+ T
latch _ delay
Noise isolation in Mixed-Signal System
KTH/ESD/HT 02/04/2008 22

Mixed-Signal
Performance Estimation: Noise Isolation
Step 1: Make a Placement Plan, Interconnect and Package Plan
Step 2: Make an Isolation Plan. In this paper, we considered (1) the distance
(between analog-digital), guard rings, IC substrate materials, chip partition
Step 3: Creat Substrate Circuits (3D meshes) and Assign L,R, C Values
Step 4: Compute Substrate Noise (only the noise isolation level over a certain range of
frequency, difficult to estimate the resonance peaks of the substrate noise at this stage,
because the accurate power supply currents are too early to be estimated)
KTH/ESD/HT 02/04/2008 23

Noise isolation technolgy in Mixed-Singl System
1:Distance
2:Guarding ring
3:SOI
Relation between isolation and distance
Guard ring of heavily-doped substrate
Guard ring of Lightly-doped substrate
SOI technology
KTH/ESD/HT 02/04/2008 24

Equivalent Circuit for Substrate
If the distance increased,
we insert more meshes
Kirchoffs current law at node j:
∑
j
⎡(
V − Vj)
i
⎢
+ Cij
⎣ Rij
R ij
= ρh ij
/w ij
d ij
C ij
=ε w ij
d ij
/ h ij
∂V
(
∂t
i
∂Vj
⎤
− )
⎥
= 0
∂t
⎦
If the substrate is partitioned into two chips here, set
the R of this column to infinitely large and C to zero.
KTH/ESD/HT 02/04/2008 25

SoC vs. SoP Cost Models
Cost Consideration in This Paper: Chip Area and Yield, Technology Fusion, Mixed-
Signal Isolation, Packaging and Substrate Cost, Rework and Repair
More Factors Need to be Considered in the Future: Components Design and Reuse, Test
and Verification, ...
SoC Cost:
SoP Cost:
C
soc
=
C
wafer
Y
d
( raw,
process , mask )
N
die
( A , A )
wafer
KTH/ESD/HT 02/04/2008 26
die
( raw,
process , mask )
N
C wafer
C
∑
substrate
+ + C assembly + C rework
Yd
N die ( Awafer
, Adie
) Ys
C sop = 1 Ya
where
C wafer:
the cost of processed wafer, it is a function of raw substrate, fabrication process type, and mask layers;
N die
:the number of chip per wafer, it is a function of wafer area and die area;
C assembly
:the cost of chip assembly;
C substrate
:the substrate cost per unit module;
C rework
: the cost of rework;
N : the number of partitions in the SoP,
Y d
, Y s
, and Y a
: yield of die, substrate, and assembly, respectively.

SoC vs. SoP Cost Models: cont’
Chip Yield:
where D o is the average density of electric defects, N is the number of mask layers in the fabrication process, and A is the area
of chip. S is the shape factor of (what is assumed to be) the Gamma distribution of electrical defect density.
Yield Improvement Due to Re-Work/Repair in SoP:
The total chip area due to mixed-signal
isolation and technology fusion of A, B, C, …
Where α , β, γ are the factors for chip area increase due to circuits A, B, C merge
Example: in UMC 0.l8µm CMOS technology, cell size of a 6T-SRAM is 4.0um 2 for logic and SRAM
intensive produce, but it becomes 5.6um 2 for embedded memory produce. So, here we get α=1.4.
The total mask layers due to merge of different circuits A, B, C:
KTH/ESD/HT 02/04/2008 27

Chip-Packaging co-design for mixed signal system integration
DSP
RISCM
PU
bridge
PCI
PCI
Timer
Ethernet
Controller
ROM
Memory
Controller
UART Watchdog
IP modules
SSP
SSP
UART
DSP
API
Timer
RAM
ROM
bridge
RAM
API
SSP
SSP
RISCM
PU
Watchdog
VCO
Radio
ASIC
Loop
filter
Balun
Switch
Antenna
Filter
Custom modules
RF components
Memory
Controller
Ethernet
Controller
Balun
Radio
ASIC
Antenna
Filter
Switch
VCO
Loop
filter
M. Shen et al: this meeting
COMSI: Cost-performance analysis of Mixed
Signal Implementation
Algorithm COMSI: Cost (Isolation _dB, f _Hz)
Substrate=[lightly-doped-substrate, heavily-opedsubstrate,
high-resistivity-substrate, SOI-substrate]
For i=1:1:4
Loop1: Change distance and obtain isolation
If (isolation>Isolation_dB) then
Calculate cost1(i)
Exit
Elsif (distance >Max_Distance) then
Cost1(i)= ∞
Exit
End
Loop2: Using guard ring than change distance
If (isolation>Isolation_dB) then
Calculate cost2(i)
Exit;
Elsif (distance >MaxDistance) then
Cost2(i)= ∞
Exit
End
End
Cost= min {Cost1(i), Cost2(i)} (i=1,2,3,4)
KTH/ESD/HT 02/04/2008 28

Results and Discussions
To simplify the presentation, the results will be demonstrated through
two case studies in the following mixed-signal wireless system
KTH/ESD/HT 02/04/2008 29

Model Parameters Used for Case Studies
KTH/ESD/HT 02/04/2008 30

Case Study 1
•The system includes 2Mbit DRAM, 200K logic, and 400K ASIC and 1mm 2 analog/RF.
•Noise isolation constraint is –40dB under the maximum frequency of 1GHz.
•Target design foundry is a 0.18µm CMOS, standard cell library, 6 wiring levels
•0.56µm lower-level wire pith, peripheral in line pad and wire-bond packaging.
In this case, SoC
integration is much
cheaper !
SoC!
KTH/ESD/HT 02/04/2008 31

Case Study 2
The same system as in Case 1, but the memory capacity increased to 16Mbit, and
the isolation requirement is –80dB (up to 1GHz)
SoP!
In this case, SoP
integration (with three
chips) is much cheaper !
KTH/ESD/HT 02/04/2008 32

System-on-Chip vs. System-on-Package ?
Reasons for System-on-Chip:
High performance (single chip integration/short interconnection)
Low cost (single chip integration)
Passive components (L, R, C) integration on-chip possible
Mixed signal integration (analog/RF, digital, memory)
Application example: single chip radio
Reasons for System-on-Package:
Single-chip integration is not necessary to be an optimal solution,
usually not possible to yield a complete system integration
- Mixed technologies in one complex system: Si, GeSi, GaAs, Ceramic, MEMS
- Some passive components always stay off-chip: Balun, BF, switches, antenna
- Mixed signal coupling through substrate
-Low Q for on-chip passives (2-12 c.f. 20-100 for off-chip counterparts)
-Application example: a single module radio
KTH/ESD/HT 02/04/2008 33

2D or 3D Integration ?
- Future Opportunities -
KTH/ESD/HT 02/04/2008 34

3D-Integration Options
KTH/ESD/HT 02/04/2008 35

2D vs. 3D cost models
KTH/ESD/HT 02/04/2008 36

Additional Model Parameters Used
KTH/ESD/HT 02/04/2008 37

2D and 3D Cost Models
3D-SiP Integration
3D-W2W Integration
3D-D2W Integration
Cost for the Package
KTH/ESD/HT 02/04/2008 38

Electrical Performance Model
Wire Parameters
KTH/ESD/HT 02/04/2008 39

Example: Cost Driven Design for Bluetooth Terminal
2Mbit DRAM, 200K logic, and 400K ASIC and
1mm2 analog/RF.
Noise isolation constraint is –40dB under the
maximum frequency of 1GHz.
Target design foundry is a 0.18µm CMOS,
standard cell library, 6 wiring levels
0.56µm lower-level wire pith, peripheral in line
pad and wire-bond packaging.
Parameter
SoC
2D-SoP
3D-SiP
3D-W2W
3D-D2W
Area
1
2.42
1.54
0.72
0.72
Yield(%)
91
95
95
92
96
cost
1
2.47
2.42
0.98
1.48
Max. Delay (ps)
443
536
491
419
419
* Delay – from one corner to the farthest corner
Roshan Weerasekera et.al. ”Peformance and Cost tradeoffs for 2D and 3D Integration of Mixed-Signal Systems”, In manuscript
KTH/ESD/HT 02/04/2008 40

Example: Cost Driven Design for Mobile Terminal
16Mbit DRAM, 200K logic, and 400K ASIC and
1mm2 analog/RF.
Noise isolation constraint is –40dB under the
maximum frequency of 1GHz.
Target design foundry is a 0.18µm CMOS,
standard cell library, 6 wiring levels
0.56µm lower-level wire pith, peripheral in line
pad and wire-bond packaging.
Parameter
SoC
2D-SoP
3D-SiP
3D-W2W
3D-D2W
Area
1
1.54
0.97
0.52
0.52
Yield(%)
76
98
98
86
96
cost
1
0.82
0.80
0.48
0.53
Max. Delay (ps)
512
554
505
429
429
* Delay – from one corner to the farthest corner
Roshan Weerasekera et.al. ”Peformance and Cost tradeoffs for 2D and 3D Integration of Mixed-Signal Systems”, In manuscript
KTH/ESD/HT 02/04/2008 41

Summary
ASIC, DSP, μP
Memory
Analog, RF
SoC &
MCM
SoC &
SoP
SoC &
SoP
SSoC
SoC&
3DSoP
SSoC
SoP
MEMS
OEIC
year
2001 2008
2015?
SoC: from system-on-chip to subsystem-on-chip
SoP: from subsystem-on-package to system-on-package
KTH/ESD/HT 02/04/2008 42

Thank you !
KTH/ESD/HT 02/04/2008 43

List of refererences
P. A. Sandborn and H. Moreno, Conceptual Design of Multichip Modules and Systems. Kluwer Academic Publishers,
1994.
M. Shen, L.-R. Zheng, and H. Tenhunen, “Cost and performance analysis for mixed-signal system implementation:
System-on-chip or systemon-package,” Electronics Packaging Manufacturing, IEEE Journal of,vol. 25, no. 4, pp. 262–
272, October 2002.
D. Ragan, P. Sandborn, and P. Stoaks, “A detailed cost model for concurrent use with hardware/software co-design,” in
Design Automation Conference, 2002. Proceedings of IEEE/ACM, 2002, pp. 269–274.
S. Kuhn, M. Kleiner, and W. Weber, “Performance modeling of the interconnect structure of a 3-dimensionally
integrated risc processor/cachesystem,” in Electronic Components and Technology Conference, 1995. Proceedings.,
45th, 1995, pp. 592–599.
KTH/ESD/HT 02/04/2008 44