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N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s
beginning and much more will be discovered and
understood in up-coming years. The only thing to
avoid with 3D Integration is to continue thinking
based on the past experiences of downscaling.
Applying Moore’s law based on scaling to a More
than Moore approach such as 3D Integration TSV is
not necessary at all. The application should help in
the roadmap definition.
Printed on recycled paper
Fig 4 - Application Roadmap for 3D integration in wireless products (Courtesy of ST-Ericsson)
wires by connections coming from the backside of
the die would gain them a reduction in the camera
volume and its cost. However, in this example, we
can’t speak about TSV enabling 3D configuration
because, in fact, no chips are connected along the
vertical axis. The top layer is only a glass carrier, not
an active die; this can be called 2.5D but definitively
not 3D.
Power Amplifiers (PA) built in SOI are likely to use
TSV technology in the future in order to improve
performance and reduce die size. For PA, TSV is
only used for parasitic and each is connected to a
common ground on the metallized backside of the
chip. Wires remain for I/O. In that case, a very low
cost TSV technology is compulsory. Thermal
dissipation improvement is foreseen as well.
The first true 3D ICs using TSV are forecasted for
2012. New partitioning of chips with IP in the best
techno node will appear. Logic dice would be from
different techno node generations (N generation,
N+1, N+2…). A smart split of functions will be done
in order to achieve the right cost/performance tradeoff
with TSV as the new enabler. An intermediate
step based on a silicon interposer for the bottom die,
containing only routing and few functions, is likely to
happen. It will help in bridging the gap toward 3D
SoC and a full readiness of design tools. With 3D IC
and TSV, new topics will need to be considered.
Numbers of options in silicon wafers, such as the
type of ESD protection and test strategy are a few. A
key advantage of 3D IC for this scheme of integration
is clearly the time reduction of critical IP development
in an advanced techno node. With a smart
partitioning, complexity will be reduced and no
longer on the critical path.
A memory / logic stack using TSV is a type of
application the industry often refers to. The main
reason for this is the increased bandwidth required
by the final applications (driven by video features
such as 1080p30 playback, 1080p30, 60, 120
Camcorder, 3D gaming…). With a new memory /
logic interface architecture, based for instance on a
wide I/O approach, this bandwidth challenge might
be overcome. Furthermore, this new wide I/O
interface with parallel access to the memory will
enable lower power consumption in the memory bus.
For cellular phones, this bandwidth bottleneck might
come after the Low Power DDR2 memory
generation. However, many challenges are rising.
Thermal management is definitively a critical point in
this approach. In effect, the power dissipation of the
logic die, typically an application processor or a
digital baseband, can heat the memory directly
stacked on top. As memories have a lower Tj than
logic die (85°C or 105°C), the memory will receive
too much heat and won’t work correctly. Power
dissipation of the bottom die will be range from 1 to 3
W from low to high end 3G platforms.
Another main issue with the wide I/O memory is the
standardization and supply chain. Most of the time,
the memory and logic die will come from different
companies. Standardization will be required to
enable the final OEM integrator to source different
memory types or any double sourcing.
Conclusions
Roadmaps will mature during the next few years as
people begin to understand all the capabilities of 3D
Integration. As of today, only the emerging part of the
iceberg is visible. 3D thinking is only at its early
It is crucial to differentiate 3D packaging and 3D at
the IC level using TSV. TSV by itself is not a
packaging technology apart from some few
exceptions. Consequently, 3D TSV and 3D
packaging do not have to be considered as
competitors but more as complementary areas. In
recent years, the semiconductor industry has
expressed some growing interest in these ideas and
put some significant efforts in allowing the
emergence of these new breakthrough technologies.
Still, some challenges remain ahead for a wide
adoption. Most of them are cost, a shift in the design
method paradigm, system co-design, new CAD
tools, new architectures, and more new challenges.
The 3D IC TSV combined with the 3D eWLB TM
appears as the next wave for future integration and
should initiate some new integration schemes. We
expect to expand the innovation landscape through
lower cost and better electrical and thermal
performances enabled by new partitioning and
architectures, higher flexibility, better integration with
easier software implementation and a shorter time to
market.
Yann Guillou
New Technology Marketing - ST-Ericsson
Yann.Guillou@stericsson.com
+33 476 58 58 77
Yann Guillou is currently
in charge of New
Technology Marketing
activities for the Wireless
Multimedia Group of ST-
Ericsson. His main interest is in 3D Integration
and Advanced Packaging. He started his
career at CEA-LETI before joining
STMicroelectronics and successively worked
at ST-NXP Wireless and ST-Ericsson. He
holds a MSc degree in Materials and
NanoTechnology from INSA (National
Institute of Applied Sciences, France) and a
Specialized Master in Management of
Technology and Innovation from Grenoble
Business School (France).
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