Flip-Chip - I-Micronews

Flip-Chip 

Understand the new requirements and technologies that are reshaping 

the world’s highest value semiconductor packaging platform 

April 2011 - Report SAMPLE 

FC BGA 

PCB 

© 2011 

Copyrights © Yole Développement SARL. All rights reserved.

Content of the full report 

• Scope of the report and definitions………………3 

• Executive summary…………………………………9 

• Market forecasts (2010-2016)………….………….63 

– Top-down analysis: 2010 Flip Chip market value 

and 2010-2016 forecasts…………........…………….65 

– Bottom-up analysis: 2010 Flip Chip industry status 

& wafer processing capacities……………………104 

• Process flow and technologies………………..127 

– Flip-chip package platforms……........……….…...128 

– Bumping technologies…………………….....…….132 

– Copper pillars……………………………..........….…160 

– Substrates………………………………………...…...194 

– Pick, flip and place………………………......………211 

– Underfilling………………………………..…………..214 

– Fluxing…………………………………..……….…….235 

– Thermal Interface Materials………………..……...239 

• Applications and drivers of flip-chip………….244 

– End-Market drivers for flip-chip 

• Computing / Handsets / Telecom & Network servers / 

Consumer / Medical / Automotive / Military & Aerospace 

– Application focus for: 

• Microprocessors (MPU’s, CPU’s) 

• Graphical processor units (GPU’s) 

• Chipsets 

• ASICs 

• FPGAs 

• DDR memories 

• Application processors (APE’s) 

• Baseband ICs 

• Transceivers 

• Radio Front-end modules 

• High power LEDs 

• LCD display drivers 

• CMOS image sensors, MEMS 

• DSPs 

• SAW + BAW filters 

• Costs structure, flip-chip manufacturing & 

assembly …………………….……..………….…..273 

• Supply chain analysis……………………………284 

• Roadmaps and perspectives……………………301 

• Conclusions………………………………………..307 

© 2011 • 2 


Market Status and Forecast Charts (1) 

• Top down analysis 

– 2010 Flip Chip market value 

– Split by main process steps (substrate, 

wafer bumping, assembly, test) 

– Split by end package type (flip chip in 

package versus chip on flex, chip on 

glass 

– 2010-2016 Flip Chip market value 

forecast 

– Total Flip Chip, split by main process 

steps 

– Flip Chip in Package end use type, split 

by main process steps 

– 2010-2016 Flip Chip unit forecast 

– Total Flip Chip, by end application area 

• Flip Chip in Package 

– by end application area 

– For the « Plated bumps/Rigid Organic 

Substrate » category 

– For the telecom application area, by IC 

type 

– For the Computing application area, by 

IC type 

– 2010 Flip Chip Wafer Bumping 

– Total Flip Chip, by IC type 

– Flip Chip in Package (FCiP) by IC type 

– 2010-2016 Flip Chip wafer forecasts 

• Total Flip Chip 

– split by end use type (FCIP vs 

COF/COG) 

– Split by application area 

– By IC type 

– By bumping technology/metallurgy 

(lead free solder vs eutectic solder vs 

gold vs copper,…) 

– Lead free vs leaded 

– Solder alloys vs non solder metals 

• Flip Chip in Package (FCiP), 

– by IC type 

– For the Telecom application area, by IC 

type 

– For the Computing application area, by 

IC type 

© 2011 • 3 


Market Status and Forecast Charts (2) 

• Bottom-up (Wafer Bumping) 

– 2010 wafer bumping capacity for Flip 

Chip 

• Total (all technologies) 

– By technology (solder plus copper 

versus gold) 

– By player 

– By region 

– By wafer size 

• Solder plus copper bumping 


versus gold) 

– By player 

– By region 


– Player profile (OSAT vs captive IDM vs 

foundry vs bumping house) 

distribution by wafer size 

• Gold bumping 


versus gold) 

– By player 

– By region 


– Player profile (OSAT vs captive IDM vs 

foundry vs bumping house) 

distribution by wafer size 

– 2010 Wafer bumping value for Flip 

Chip 

– By player 

– By player profile (OSAT vs captive IDM 

vs foundry vs bumping house) 

• Bottom-up (substrates) 

• Rigid Organic Substrates for the Flip- 

Chip Market 

– Split by supplier 

– Split by region 

• Bottom-up (underfills) 

– 2010 Flip Chip & Circuit board 

assembly underfill materials market 

– 2010 Flip Chip underfill materials by 

Process Flows, Techniques and Uses 

© 2011 • 4 


Scope of this report 

in Yole’s Advanced Packaging Research 

PANEL / Wafer-Scale-Packaging Platforms 

Wafer-Level 

Interface / Encapsulation 

Wafer-Level 

Electrical Redistribution 

Flip-chip & Wafer-Level 

Stacking / Integration 

Systems 

with 

Fluidic 

LED & 

Sensors 

Optics 

MEMS & 

Sensors 

Capping 

WL-CSP 

‘Fan-in’ 

FOWLP 

‘Fan-Out’ 

Embedded IC 

in PCB / laminate 

3D IC 

& TSV 

Glass / Silicon 

2.5D 

interposers 

Flip-chip 

© 2011 • 5 

Copyrights © Yole Développement SARL. All rights reserved. 

FOCUS of 

this new 

research 

report!

Why this report on Flip-chip ? 

• This is the first report of Yole Developpement on Flip-chip technology, the 

world’s highest value semiconductor packaging technology: 

– The so-called “mid-end” infrastructure consisting in foundries for wafer-level packaging operations 

have developed at an unprecedented pace over the past 3 years to meet the growing demand for 

Wafer-Level Chip-Scale Packaging (or “fan-in WLCSP”) and wafer processing for flip-chip. These new 

facilities, half way between front-end foundries and regular assembly and packaging facilities, now 

support high volume manufacturing on large size wafers, thus permitting economies of scale. 

– Initially driven by high speed/high IO count computer processors , FPGA’s and ASiCs, flip-chip BGA 

has more recently extended its reach to mobile handsets and is becoming a leading package platform 

in the semiconductor industry 

– From a specialty package for small size ESD/EMI protection integrated devices in 2000, Wafer-Level 

Chip-Scale-Package has become one of the most popular packages throughout the industry in just 10 

years totaling 9 billion units per year and still growing at a sustained rate higher than 20%. Yole 

Développement issued a report fully dedicated to WLCSP (WLP 2009), as well as another one fully 

dedicated to the emerging embedded wafer level packages in 2010 (fan-out WLCSP and embedded 

chip in substrate). Yole Développement has also consistently followed up 3D wafer level packaging 

technologies with regular market and technology reports on 3D ICs, silicon interposers, as well as 

equipment and materials for 3D WLP. This report on flip-chip completes our report offer on waferlevel 

“mi-end” technologies. 

– For the first time ever, the complete wafer level packaging supply chain infrastructure is being 

addressed by a market research and technology analysis company, covering the industry status, 

technologies, markets and forecasts for fan-in and fan-out WLCSP, embedded ICs, 3D TSVs and ICs, 

silicon & glass interposers, and now flip-chip. 

© 2011 • 6 


Who should buy this report? 

• Integrated semiconductor device manufacturers and fabless semiconductor companies 

– Visualize the drivers and expected benefits by application of flip-chip as well as the alternative options 

– Benchmark the industry status of flip-chip 

– Identify possible partnership /or second source packaging subcontractors for your forthcoming 

developments 

• Assembly and test service companies 

– Benchmark the industry status of flip-chip. Evaluate your market and technology position 

– Screen possible new applications and technologies to support diversification strategy with flip-chip 

technologies 

• Silicon wafer foundries 

– Screen possible new applications and technologies to support diversification strategy in wafer bumping 

• Equipment and material suppliers 

– Understand the differentiated value of your products and technologies in this large and fast growing market 

– Identify new business opportunities and prospects 

• Electronic module makers and Original Equipment Makers 

– Evaluate the benefits of using flip-chip devices in your end system 

– Monitor different suppliers to adjust your sourcing strategy 

• PCB and IC substrate manufacturers 

– Monitor the evolution of IC packaging, assembly and test, especially linked to the emerging 3D silicon/glass 

interposers and other 3D silicon technologies. Evaluate opportunities and threats for the flip-chip substrate 

market. 

– Screen possible new applications and technologies to support diversification strategy with flip-chip 

substrates 

© 2011 • 7 


Definition of Flip-chip 

• A chip packaging technique in which the active area of the chip is "flipped over" 

facing downward. Instead of facing up and bonded to the package leads with 

wires from the outside edges of the chip, any surface area of the flip chip can be 

used for interconnection, which is typically done through metal bumps. These 

"bumps" are soldered onto the package and underfilled with epoxy. The flip chip 

allows for a large number of interconnects with shorter distances than wire, which 

greatly reduces inductance. (source “thefreedictionary.com”) 

• Metal bumps can be made of 

– solder (tin, or tin-lead or lead-free 

alloys) 

– copper 

– gold 

– Copper-tin or gold-tin alloys 

• Package substrates are 

– Epoxy-based (organic substrates) 

– Ceramic based 

– Copper based (leadframe substrates) 

– Silicon or glass based 

Courtesy of Amkor Technologies 

© 2011 • 8 


Foreword – This first report emphasizes on… 

• Even though we wanted this report to be as exhaustive as possible on all 

aspects of flip-chip, we decided to emphasize specifically on: 

– Who does what? 

• supply chain, flip-chip « families » of companies working together, influences, … 

– Markets 

• 2010 market shares and production levels of wafer bumping, flip-chip substrates 

and underfills 

• 2011-2016 wafer bumping market forecasts: 

‣ by application area (computing, telecom, industrial,…) 

‣ by IC type (GPU, CPU, chipset, application processor, FPGA, DDR,…) 

‣ by technology (bumping metallurgy, flip-chip package type) 

– Technologies, with a special focus on 

• Copper pillar bumping 

• Underfills 

Which we deem are both key to defining the next generation flip-chip 

technologies, especially to achieve lower costs 

© 2011 • 9 


Foreword - This Report Does Not Address/Cover …. 

• We chose to not address the following side topics, so as to focus on what we 

think is representative of « mainstream flip-chip »: 

– 2 nd level interconnects, since we preferred to focus on the fast evolving 

technologies for the 1 st level « flip-chip » interconnect and because 2 nd level 

interconnects are not specific to flip-chip 

– WLCSP, fan-in or fan-out. These technologies are the subject of separate Yole 

Développement reports. Even if they utilize bumping and wafer level packaging 

techniques like flip-chip, we consider them as separate from flip-chip as they do 

not use « flip-chip substrates » 

– Thermal Interface Materials are not covered exhaustively throughout this report: 

they will be addressed in the upcoming report dedicated to « power packaging and 

thermal management of ICs » 

– Silicon to silicon Micro-bumping, or « zero-level » interconnect: this part will be 

added to the 2012 flip-chip report, after the « 3D TSV business update » report is 

updated, so as to get the most accurate forecast 

– High Power LEDs: some of them are packaged with flip-chip, however , since this 

is still an emerging market with specific technologies, their study will be 

exhaustively carried out in our upcoming « LED Packaging report » 

© 2011 • 10 


Difference between Flip-Chip packages 

and the Wafer-Level Chip-Scale Package (WLCSP) 

• With WLCSP, the bumped integrated circuits can be directly mounted onto the Printed 

Circuit Board of of the end equipment by the Original Equipment Maker 

• Flip-Chip packages utilize an intermediate “high density interconnect” (HDI) printed 

circuit board 

• Throughout this report, we do not address WLCSP, which is the object of a dedicated 

market research report 

Flip-Chip 

UBM 

Underfiller 

WL CSP 

Bump 

Package 

substrate 

PCB / PWB 

© 2011 • 11 


Wafer Bumping definitions 

WAFER BUMPING 

FLIP CHIP 

WAFER LEVEL PACKAGING 

Chip on Board Silicon on silicon 

FC BGA FC CSP FAN IN FAN OUT 

COF/COG micro-bumping 

CHIP 

EMBEDDING 

Bump 

characteristics 

Plating, screen 

printing 

pitch : < 

180µm 

Bump 


Plating, screen 

printing, stud 

pitch : < 

150µm 

Bump 


Plating 

pitch : < 

150µm 

Bump 


Plating 

pitch : < 60µm 

Bump characteristics 

Ball dropping 

pitch : 400-500µm 

Courtesy of Statschippac 

Courtesy of 3M 

Courtesy 

of SPIL 

Courtesy of 

NXP and FCI 

Scope of the 

2011 Flip-Chip report 

Part of the 2011 

3D IC market report 

Scope of the 2011 

WLCSP report 

Scope of the 2011 

fan-out/embedded report 

© 2011 • 12 


The Evolution of Semiconductor Packaging 

A bridging technology between ICs and PCBs 

Feature sizes of PCBs 

Feature sizes of CMOS transistors 

100µm 

Organic interposers 

3D integration 

Bumping 

28nm 

© 2011 • 13 

1970 

through 

hole 

technology 

1980 

Surface mount 

devices 


1990 

CSPs/BGAs 

SiPs 

2000 

WLCSP 

more SiPs 

Flip-chip BGA 

PoP 

2010 

3DIC 

TSV 

Fan-out WLCSP 

Cu pillars 

Silicon interposers

The Evolution of Semiconductor Packaging 

a bridging technology between ICs and PCBs 

• The evolution of semiconductor packaging 

technologies over the past 40 years had been driven 

by the need to bridge the increasing « IO 

interconnect gap », between the fast decreasing 

silicon geometries (Moore’s law) and the slower 

shrink of the Printed Circuit Board technologies 

Feature sizes of PCBs 

Feature sizes of CMOS transistors 

100µm 

• Flip-Chip emerged as the mainstream solution over 

the 2000-2010 decade to match the requirements of 

the high-IO count and high IO-density devices. 

Organic interposers 

3D integration 

Bumping 

• We estimate that because of this gap, a silicon size 

increase usually translates to a 3 to 4 times 

necessary increase of the package size for high IO 

density devices 

PCB pitch (mm) 

Bond pad 

opening/pitch 

(µm) 

28nm 

1970 

through 

hole 

technology 

1980 

Surface mount 

devices 

1990 

CSPs/BGAs 

SiPs 

2000 

WLCSP 

more SiPs 

Flip-chip BGA 

PoP 

2010 

3DIC 

TSV 

Fan-out WLCSP 

Cu pillars 

Silicon interposers 

130/100 

1.27 

1 

65/65 

45/45 

0.5 

0.4 

wireless 

© 2011 • 14 

2005 

2010 


CMOS 130nm 

(2000) 

CMOS 40nm 

(2007) 

CMOS 28nm 

(2009)

© 2011 • 15 

Flip-chip technology - drivers and key benefits 

• The drivers for using flip-chip are: 

– No alternative solution for High (and increasing) IO density with need for large die-topackage 

fan-out area, Interconnection to fine-pitch substrate (to bridge the IO 

interconnect gap) 

• Especially true for application processors in fcCSP, GPUs, CPUs, chipsets in fcBGA, for display 

drivers in COG, COF 

– Electrical performance / interface bandwidth requirements 

• In particular for Application processors, GPUs, FPGAs, ASICs, Power Management Units, RF 

transceivers 

– Thermal dissipation requirements 

• CPUs, GPUs, Power amplifiers 

– Hermeticity 

• SAW filters 

– Ergonomics, topology: 

• CMOS Image Sensors and LEDs 

• Cost is GENERALLY NOT a primary driver of using flip-chip 

– Flip-Chip accounts for less than 10% of all semiconductor packages, and for 27% of the 

total semiconductor assembly and packaging market in value. 

– However, due to an all time high gold price (for wire bonding), and thanks to economy of 

scale with increasing flip-chip volumes, the flip-chip cost impact is being considerably 

reduced. 


A Wide Technology Diversity 

Single Chip Flip-Chip Package Types 

fcCSP (flip chip Chip Scale Package family) 

fcBGA/PBGA (flip chip Ball/Pin Grid Array 

Package family) 

Molded PoP 

Bare die PoP 

Molded 

exposed 

die 

TMV PoP 

2-piece 

lid 

Cu pillar with 

molded underfill 

Cu pillar 

1-piece 

lid 

Solder bump fcCSP 

Log (IO count) 

200 1000 3000 

© 2011 • 16 


A Wide Technology Diversity 

Single Chip Flip-Chip Package Types 

fcCSP with cavity fcCSP Bare die fcBGA High-end fcBGA 

Applications 

SAW filters, BAW filters, 

MEMS, sensors 

handheld phones 

(application processors, 

baseband ICs, transceivers, 

PMUs) 

PC chipset, GPU, low end 

ASIC 

FPGA, high-end ASIC, PC 

processor, chipset and GPU, 

networking or storage 

processor 

Bumps 

solder bumps (eutectic or 

lead free) or Cu pillars 

solder bumps (eutectic or 

lead free) or Cu pillars 

solder bumps (Eutectic or 

lead free) 

solder bumps (Eutectic or Pb 

free) 

pitch 

2 nd interconnect: 0.4mm to 

1mm 

1 st interconnect:80µm 

peripheral / 150µm area 

array 

2 nd interconnect: 

0.4mm to 1mm BGA ball 

pitches 

Package side size 1mm to 3mm 3mm to 17mm 

(max. die size = 10x10mm²) 

Specific characteristics 

Lidded, hermetically sealed, 

ceramic substrates, no 

underfill 

Overmolded or bare die 

Regular or PoP bottom 

package 

Assembly on substrate strips 

Capillary or molded underfill 

1 st interconnect: 200µm min 


0.8mm or 1mm or 1.27mm 

13mm to 40mm 

(max. die size = 17x17mm²) 

Capillary underfill 

SMT passives 

Assembly on singulated 

substrates 

1 st interconnect: 150µm min 


0.8mm or 1mm or 1.27mm 

13mm to 55mm 

(max. die size: max. 

26x26mm²) 

1 or 2 piece(s) lid or 

exposed die mold 

Capillary underfill or molded 

underfill 

SMT passives 

Assembly on singulated 

substrates 

© 2011 • 17 


Emergence of Copper Pillars in Flip-Chip ? 

• Wafer bump and assembly processing are critical for copper pillars as they are in all FC technologies. 

“Pillars” of copper are typically plated on the chip in wafer form through photo lithography techniques. 

Solder bumps have fixed aspect ratios lower than one, whereas copper pillars offer aspect ratio flexibility, 

and therefore can increase IO bump densities for many applications in addition to other advantages… 

• Pitch limited to 150µm min, 120µm at best, due 

to spherical aspect and need for sufficient z- 

height gap for underfill flow 

• Risks of electrical shorts by bridging 

• Limited spacing between adjacent bumps for 

signal routing 

• Limited spacing between adjacent bumps 

prevents the underfill from flowing causing 

underfill voids 

• Reduced pitch leads to lower bump height (due 

to 1:1.3 aspect ratio) causing 

– Reliability issue by lack of bump elasticity 

– Reduced stand-off height making it more difficult for the 

underfill to flow. 

© 2011 • 18 

from solder bumps 


to copper pillars 

• Finer possible pitches down to 20µm 

• Reduced risk of shorts between adjacent bumps 

• Larger spacing between adjacent bumps for 

signal routing and easier underfill flow 

• High bump aspect ratio allows for higher standoff 

height (easier underfill flow) 

• Copper pillars are a reliable lead-free bumping 

option 

• Copper offers higher electrical conductivity than 

solder: 25% lower resistance than SnPb 

– Lower R DS allows for increaded power 

ON 

delivery 

• Higher current density capability (better 

resistance to electromigration) 

• But higher elastic modulus (stress during attach 

process)

Shipments (in Munits) 

Flip Chip packages 2010-2016 unit forecasts 

25 000 

20 000 

Flip-Chip package unit shipments Forecast 

by end marke area (in Munits) 

Yole Developpement © April 2011 

15 000 

10 000 

5 000 

0 

2010 2011 2012 2013 2014 2015 2016 

automotive 8 11 13 17 24 30 35 

aerospace and defense 12 13 14 16 18 19 21 

industrial & medical 48 54 60 69 80 92 105 

consumer 4 301 4 380 4 434 4 460 4 446 4 636 4 816 

telecommunications 7 212 8 194 8 678 9 206 9 662 10 054 10 425 

computing 5 447 5 728 6 180 6 676 7 187 7 679 8 024 

• Flip Chip is primarily driven by computing, telecom / mobile and home consumer related applications 

• Flip Chip accounted for > 17 billion units as of 2010, i.e. 11% of all packaged Ics, with a CAGR limited to 5.5% 

– This low rate does not reflect the strong dynamism of flip-chip technology currently happending in the digital CMOS 

space. Indeed, we expect the 2010-2011 Flip-Chip in package of large digital CMOS ICs CAGR to be 20% ! 

– However, overall CAGR is actually lowered by the massive move of RF filters from flip chip to full wafer level CSP (Fan-in 

WLP), as well as the slower growth of display LCD drivers 

© 2011 • 19 


Flip-Chip Market Value 

Split by cost-of-ownership segments (Substrate, Assembly, Packaging and test) 

2010 Total Flip-Chip Market Value 

split by cost-of-ownership supply chain segments - Total = B$ 16 

(substrates for LCD drivers excluded, service margin included) 

Yole Développement, April 2011 

16% 

17% 

34% 

Substrate (rigid substrates, no flex for 

display) 

Wafer repassivation, redistribution and 

bumping 

14% 

19% 

Assembly (dicing, pick & place, 

underfilling, molding, marking, packing) 

Wafer probe test 

Final test 

• In 2010, the total Flip Chip Assembly, Packaging and Test Market totaled B$ 16 

© 2011 • 20 


About Yole’s Advanced Packaging Analysts 

Jean-Marc Yannou 

– Jean-Marc joined Yole 

Développement as technology and 

market expert in the fields of 

advanced packaging and 

Integrated Passive Devices. He 

has 15-years of experience in the 

semiconductor industry. He 

worked for Texas Instruments & 

NXP semiconductors where he 

was Innovation Manager for 

System-in-Package technologies 

Contact: yannou@yole.fr 

Jerome Baron 

– Jerome is leading the MEMS & 

Advanced Packaging market 

research at Yole Developpement. 

He has been following the 3D 

packaging market evolution since 

its early beginnings at device, 

equipment and material levels. He 

was granted a Master of Science 

degree in Nanotechnologies from 

the National Institute of Applied 

Sciences in Lyon, France 

Contact: baron@yole.fr 

Phil Garrou 

– Phil recently joined Yole 

Développement forces as senior 

technical advisor in the fields of 

advanced packaging. Phil as 

more than 20 years extensive 

experiences in the 

semiconductor industry where he 

mainly served as global 

marketing manager for DOW 

Chemical’s BCB polymer 

business 

Contact: garrou@yole.fr 

Christophe Zinck 

– Christophe joined Yole 

Developpement after several 

positions in the wafer fab and 

packaging environments of CEA- 

Leti, STMicroelectronics and then 

Triquint Semiconductor, where 

he was lead manager for flip-chip 

and wafer-level-packaging 

technologies implementation 

Contact: zinck@yole.fr 

© 2011 • 21 


© 2009 

Osram 

IR 

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