VME SIROCO

VME SIROCO
Caution: This document was scanned
and converted to word using optical
character recognition. Some
typographic errors remain.

VME slave board with standard addressing (24 bits) and single transfer mode (16 bits).
1 Adjustments
1.1 Jumper settings
1.1.1 Viking SIROCO (IDC clock input)
Virtual earth S1
S2
S3
S9
S12
1.1.2 Felix SIROCO (Lemo clock input)
S1
S4 left
S6 left
S7 right
S9
S10
S11
1.2 Potentiometer adjustment
POT1: adjust for reference voltage to be +10V at M7 pin 6.
POT2: adjust for 820Q between MI pin 6 and M2 pin 3 (no power-on).
POT3: adjust for DAC = FFF, m9 pin 6 = +10v.
POT4: adjust for -1V M10 pin 45
POT5: adjust for +1V M10 pin 53
POT6: adjust for -2V M10 pin 39
1.3 Component corrections
Important: Replace devices M28 and M29 with 74ALS245-1 (they should not be HCT devices).
For correct balancing of the reference voltages the following resistors should be changed: R28 =
9K1, R30 = 20K.
2 Address Space
$2008 bytes organised in 16 bit words.
The I/O address window base address is set by means of switches SW1 (A[23:20]) and SW2
(A[19:16]). The address map is shown in Table 1.
Table 1 Address map
Address Description R/W
0-$1FFE ADC mount memory R/W

$2000 Register 1 R/W
$2002 Register 2 R/W
$2004 Register 3 R only
$2006 Register 4. Bit 0 = 0 resets SIROCO. Bit 0 = 1 starts SIROCO. W only
2.1 ADC Count Memory
Read/write.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ovf
ADC count
Up to 4096 11 bit ADC values (10 bits + overflow) can be stored in this memory. The memory
address corresponds to the sample number. Bit 10 contains the overflow state.
The TDC1020 Flash ADC produces 10-bit data plus 1-bit overflow. The ADC’s output coding is
switchable by means of jumpers S2 and S3 as shown in Table 2. Example output for true binary
encoding is given in Table 3.
Table 2 ADC output coding modes
SW2 SW3 Output Coding
0 0 Inverted binary
0 1 True offset 2's complement
1 0 Inverted offset 2's complement
1 1 True binary (default).
2.2 Register 1
Read/write.
Table 3 Output for true binary encoding
Input Output MSB-LSB (OVF)
>2.0V 0000000000(1)
2.0V 0000000000(0)
1.996V 0000000001(0)
0.000V 1000000000(0)
-1.998V 1111111110(0)
-2.000V 1111111111(0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clk Cnv Lemo Frame length

Bits 3-0 contain the one’s complement of the sample frame length in units of 256. The minimum
number of samples that are selectable are 256, the maximum is 4096. The samples are segmented
into groups of 256 therefore allowable group selections are 256, 512, 768, 1024 etc. up to 4096.
E.g. for a frame length of 256, 512, …, 4096, write $F, $E,…$0 to REGISTER1[3:0].
Table 4 REGISTER1[5:4], Lemo mode encoding
bit 5 bit 4 Lemo Modes
0 0 Disabled
0 1 External start. The Lemo signal starts the ADC conversion. Memories are set
in write mode and, if selected (see below), the internal clock is stopped.
1 0 External stop. The Lemo signal stops the SIROCO ADC conversion.
Memories are disabled and, if selected (see below), the internal clock is
stopped.
Table 5 REGISTER1[6], convert mode
Bit 6 Convert mode
0 Conversion stops after selected frame length.
1 Conversion is continuous.
Table 6 REGISTER1[7], clock mode
Bit 7 Clock mode
0 External clock (differential or Lemo input).
1 Internal (VME SYSCLK) clock.
2.3 Register 2
Read/write.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clock skip
DAC baseline value
Bits 15-12 contain the number of clock pulses skipped at the beginning of the conversion. The
default value must be greater than or equal to 4. It is the complemented value which must be loaded
in the register. E.g. to skip 0, 1, …, 15 clock pulses, write $F, $E, …, $0 to REGISTER2[15:12].
The address counters are enabled on receipt of the last skipped clock pulse.
The 12bit AM6012 DAC is configured for unipolar operation. The output from the DAC is
subtracted from the SIROCO analogue input (this is effectively a base line restorer). The DAC
baseline value encoding is given in Table 7.

Table 7 DAC encoding
Data Vout
Positive full scale FFF 9.9976
Positive full scale – LSB FFE 9.9951
LSB 001 0.0024
Zero scale 000 0.0000
2.4 Register 3
Read only.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOC
Last addressed memory
Bits 11-0 contain the address of the last accessed memory cell at conversion time.
Bit 15 Conversion status
0 Conversion ended.
1 Conversion in progress.
2.5 Register 4
Write only.
Bit 0 Description
0 Stop data collection (reset).
1 Start data collection
Bit 0 controls the starting and stopping of data collection.
3 Test programs
3.1 SIROCO data collection RAM test
Data $155 is written to each individual address and read back. It is then tested with the original data
to check its integrity. If the data read back is incorrect the CPU will cycle continuously at $7012.
Upon completion of the above (successful) test, the data bits are now inverted to $2AA and the
above process repeated.
Upon successful completion, data is transferred from the SIROCO RAM to the CPU to allow
further examination of the data if required.
0000 7000 207C 0010 0000 MOVE.L #0010 0000,A0

0000 7006 303C 0155 MOVE #0155,D0
0000 700A 3080 MOVE D0 (A0)
0000 700C 3210 MOVE (A0),D1
0000 700E B240 CMP 00,D1
0000 7010 6702 BEQ.S 0000 7014
0000 7012 60FE BRA.S 0000 7012
0000 7014 DlFC 0000 0002 ADD.L #0000 0002,A0
0000 701A B1FC 0010 2000 CMP.L #0010 2000,A0
0000 7020 66E8 BNE.S 0000 700A
0000 7022 207C 0010 0000 MOVE.L #0010 0000,A0
0000 7028 303C 02AA MOVE f02AA,D0
0000 702C 3080 MOVE D0,(A0)
0000 702E 3210 MOVE (A0),Dl
0000 7030 B240 CMP D0, D1
0000 7032 6702 BEQ.S 0000 7036
0000 7034 60FE BRA.S 0000 7034
0000 7036 D1FC 0000 0002 ADD.L #0000 0002,A0
0000 703C B1FC 0010 2000 CMP.L #0010 2000,A0
0000 7042 66E8 BNE.S 0000 702C
0000 7044 267C 0010 0000 MOVE.L #0010 0000,A3
0000 704A 287C 0000 8000 MOVE.L #0000 8000,A4
0000 7050 341B MOVE (A3)+,D2
0000 7052 38C2 MOVE D2,(A4)+
0000 7054 87FC 0010 2000 CMP.L #0010 2000,A3
0000 705A 66F4 BNE.S 0000 7050
0000 705C 60FE BRA.S 0000 7050
3.2 SIROCO test routine
Instructions are given below on the operation of the VME SIROCCO FLASH, a simple test routine
is also included. The test is simply composed of linearly ramping up the on-board DAC and
sampling the produced voltage at the ADC input. The sampling rate is fixed due to the selection of
the internal clock. In this test the incremental change to the DAC is 1 (data written to the DAC is
$090 - $FFF).
This test program configures the SIROCCO to write data to 4096 samples, disables Lemo mode,
uses the VME SYSCLK (internal clock) for generating converts, sets ‘SKPD CLK PULSES’ to
zero. The on-board DAC is ramped-up from $090 to $FFF, each incremental change in DAC value
is sampled by the ADC and stored in data collection RAM. Only one address location is actually
transferred to the CPU for data analysis.
5500 CLR.W D0 SET SIROCCO
5502 MOVE.L #$0010 0000,A0 DATA COLLECTION
5508 MOVE.W D0,(A0)+ RAM TO ZERO
550A CMP.L #$0010 2000,A0
5510 BNE.S $5508 TEST FOR END RAM
5512 MOVE.L #$0000 8000,A0 SET CPU
5518 MOVE.W D0,(A0)+ DATA COLLECTION
551A CMP.L #$0000 A000,A0 RAM TO ZERO
5520 BNE.S $5518 TEST FOR END OF RAM

5522 MOVE.L #$0000 8000,A1 CPU RAM POINTER = 8000
5528 MOVE.L #$0010 0000,A3 SIROCCO RAM POINTER = 100000
552E MOVE.W #$0080,$0010 2000 NOTE 1
5536 MOVE.W #$0090,D1 INITIAL DAC DATA = 90
553A OR.W #$F000,D1 NOTE 2
553E MOVE.W D0,$0010 2006 SIROCCO RESET D0 = 0
5544 MOVE.W D1,$0010 2002 WRITE DAC DATA
554A MOVE.W #$0000,D4 TIME DELAY
554E ADD.W #$0001,D4 TO ALLOW FOR DAC
5552 CMP.W #$0550,D4 SETTLING TIME
5556 BNE.S $554E
5558 MOVE.L #$0001,0010 2006 START SIROCCO D0 = 1
5560 MOVE.L #$0010 2004,A2 READ REGISTER 2
5566 MOVE.W (A2),D2 THIS TESTS FOR BIT 15
5568 AND.W #$8000,D2 TO INDICATE
556C CMP.W #$0000,D2 END OF CONVERSION (EOC)
5570 BNE.S $5566 LOOP TILL EOC
5572 MOVE.W (A3),D3 YES EOC, READ DATA FROM
5574 AND.W #$07FF,D3 SIROCCO (1000000) AND TRANSFER
5578 MOVE.W D3,(Al)+ TO CPU RAM
557A ADD.W #$0001,Dl INCREMENT DAC DATA
557E CMP.W #$FFFF,Dl TEST FINAL DAC DATA
5582 BNE.S $553A NO, REPEAT ABOVE CYCLE
5584 BRA.S $5584 END!
3.2.1 Notes
SIROCO data collection RAM: $100000 - $102000
CPU data collection RAM $8000 – $A000
Note 1:
The bit pattern wrote to this address (register 1)
Initialises the following:
4096 strips selected
Lemo mode disabled
Conversion authorised
Internal clock selected
To configure the SIROCO to accept external clocks (converts), this is achieved by setting bit 7
register 1 ($102000) to a 1.for example to retain the above initialisation except that the clock
selected will be external, the bit pattern will be $0000 not $0080.
Note2:
The DAC data is 12-bits wide, the logical OR is required to retain the top 4-bits to 1111, this is
necessary so that the ‘skpd clk pulses’ = 0.