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22lA UTOMOTIVE 2008l SPECIAL EDITION FLEXRAY
Fig. 2: A valid whitelist has to be within the validity span of a buffer.
can be assigned to each slot, independent of the frame
received in that slot. The buffer then needs to be read in
each communication cycle, and the number of buffers is an
upper limit for the number of nodes in a communication
cluster, because a buffer is not allowed to be assigned to
more than one slot. This relaxes constraints quite a bit: we
may have hundreds of frames, but only dozens of slots and
the number of buffers typically is sufficient for this strategy.
But is it always possible?
Validity Spans and Grouping of FrIf Jobs
The following example illustrates how the buffer allocation
can support the optimal FlexRay Interface layer configuration
with respect to CPU load. For demonstration we choose
a single-channel FlexRay network schedule with 8
cycles (instead of the full 64) and 8 static slots (instead of
the several dozens that large FlexRay schedules have). As
shown in the figure 1, there are 2 PDUs sent in this slot –
the first one (green) is sent every odd cycle and the other
one (blue) is sent every even cycle. Initially, all frames of
one static slot for transmission (or reception) could share
one buffer. The disadvantage with this approach is that one
FlexRay Interface interrupt has to be raised in every communication
cycle to copy the PDUs from the system
memory into the controller buffers for transmission (or the
other way round, for reception).
If the real-time constraints for the PDUs allow, one FlexRay
Interface interrupt per two cycles would be sufficient. For
this, two buffers have to be used, and FlexRay controller
configuration specifies when (i.e. in which slot and cycle)
which buffer is to be sent. Such a “cycle filtering” configuration
is specified by a “base cycle” parameter (the first
transmission will occur in cycle N of the 64 cycles) and a
“cycle repetition” parameter (the transmission will reoccur
every N cycles throughout the 64 cycles) for each
buffer. One FlexRay Interface job can now be executed in
the beginning of every odd cycle, copying both PDUs to the
corresponding buffers.
In this example configuration, the “validity span” of each
of these two buffers is “two cycles”: Each buffer can be
updated in a time interval lasting two cycles, before the
transmission is performed by the FlexRay controller, and
new data needs to be provided. It is easier to compute a
schedule for the jobs of a FrIf to operate on buffers with
large validity spans, just as it is easier for humans to enter
a slow-moving merry-go-round than a fast-moving one. And
larger validity spans usually mean that more FrIf jobs can
be grouped together, resulting in lower CPU usage for FrIf
activations/context switches.
Application Constraints and Automatic
Scheduling
A more sophisticated buffer allocation algorithm is required
when the application has additional timing constraints
about “when does the communication have to take place”.
We assume a communication schedule where several relevant
PDUs are transmitted in a single slot (X). As shown in
figure 2,
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PDU_A is transmitted with base cycle 0 and cycle
repetition 4,
PDU_B is transmitted with base cycle 0 and cycle
repetition 1,
PDU_C is transmitted with base cycle 1 and repetition
2.
Therefore, each frame in slot X contains 2 PDUs (in one
case, one PDU is missing; this is “currently unused” frame
space that can be used for later extensions to the schedule).
In cycle 0 (with repetition 4), the frame contains PDUs
A and B, in cycle 1 (with repetition 2!) the frame contains
PDUs B and C, and in cycle 2 (with repetition 4), the frame
contains just PDU B. Assuming an application is concerned
with data in PDU_A and PDU_C, FlexRay data for this application
will be received in 3 out of every 4 cycles. However,
let’s say the application requires – here is the additional
constraint (in complex systems there will be several of
these) – that the AUTOSAR COM functions are only executed
at the end of every second communication cycle.
(Such a constraint is typically defined to ensure that legacy
applications are not interrupted by basic software activations).
Allocating one buffer for slot X is now forbidden,
because we get new data in three out of four cycles, but
we are not allowed to schedule one FlexRay Interface activation
per cycle. Hence a smart buffer allocation algorithm
is necessary to maximize the validity span of buffers: two