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A Decimal-to-Decimal Antilogarithmic Converter
Dongdong Chen, Yu Zhang, Li Chen, Daniel Teng, Khan Wahid and Seok-Bum Ko
Department of Electrical and Computer Engineering
University of Saskatchewan, Saskatoon, Canada
Abstract— This paper presents a novel design and
implementation of a 7-digit fixed-point decimal-to-decimal
antilogarithmic converter. A linear approximation algorithm is
proposed and simulated in MATLAB models. The maximum
absolute error of the proposed decimal antilogarithmic
converter is in the range of -0.000999 E absolute 0.000857 and
the maximum percent error is in the range of -0.000715 E percent
0.000691. The proposed decimal-to-decimal antilogarithmic
converter is modeled in VHDL and implemented using a Xilinx
Virtex-II Pro P30 FPGA device. The converter is implemented
using combinational logic only and it computes decimal
antilogarithms results in a single clock cycle, running at 53.1
MHz.
Index Terms – Decimal-to-decimal Antilogarithmic Converter,
FPGA
I. INTRODUCTION
The logarithm and antilogarithm are useful arithmetic
concepts in several areas of science and engineering. Some
applications of digital signal processing, such as 3-D graphics
processing and image segmentation algorithm, are
implemented by using logarithmic and antilogarithmic unit to
replace the normal computer arithmetic, due to its capability
of reducing the heavy arithmetic calculation requirement and
high power consumption. For instance, the multiplication and
division can be simplified to the level of addition and
subtraction.
Nowadays, despite the widespread use of binary
arithmetic, decimal computation still plays an important role
in many areas such as some commercial, financial and
Internet-based applications [1]. Recently, decimal hardware
arithmetic unit is attracting more and more researchers’
attention and the specifications for it has been added to the
draft revision of IEEE-754 standard for Floating-Point
arithmetic (IEEE-754r) [2]. In this paper, a straight-line
approximation algorithm-based approach is proposed and
analyzed to calculate antilogarithms of a 7-digit fixed-point
decimal number. The 7-digit decimal number is compliant
with the mantissa region of the decimal-32 floating point
number in IEEE-754r. Furthermore, the hardware
implementation of this decimal antilogarithmic unit is
described. To our knowledge, this paper is the first publication
for the decimal-to-decimal antilogarithmic converter which is
compliant with IEEE-754r standard.
The paper is organized as follows: Section II describes the
straight-line approximation algorithm approaches for decimal
antilogarithms calculation. In section III, a method for decimal
CCECE/CCGEI May 5-7 2008 Niagara Falls. Canada
978-1-4244-1643-1/08/$25.00 2008 IEEE
linear approximation is described. Section IV depicts an
overview of the architecture of the proposed decimal
antilogarithmic units; Section V presents the implementation
results on FPGA. Section VI gives the conclusions.
II. DECIMAL ANTILOGARITHMIC ALGORITHM
Mitchell firstly described a methodology to obtain
antilogarithms of a binary number ( 2 ( bin ) ) based on a straightline
approximation to the antilogarithms function [3]. Based
on the Mitchell’s algorithm, several methodologies to obtain
antilogarithms of a binary number based on a straight-line
approximation and VLSI implementation are described in [4]-
[5]. However, it is obvious that the method described above is
error-prone because many fractions such as 0.1 can not be
exactly represented as binary numbers. Using binary based
approach, the errors generated by conversion between decimal
and binary format can not be avoided. Therefore, there is a
need for a new decimal antilogarithmic algorithm which is
error-free in conversion between decimal and binary format.
The decimal antilogarithm calculations are based on
piecewise approximations to the antilogarithm curve of the
decimal logarithm. A linear approximation algorithm to
( )
calculate 10 dec is summarized as follows: Let M is the
logarithm of a decimal number in which the characteristic of
the logarithm is represented by k and the mantissa is
represented by am + b . M is represented as equation (1).
M = log ( dec) = k + 1+ 1 og ( m)
= k + am + b . (1)
( )
10 10
The antilogarithm of M is approximated by Anti log
10(
M ) ' .
Anti log
10( M ) = 10 M , (2)
10 M log( ) 10 k 10
am +
= Anti M = b . (3)
To achieve the antilogarithmic approximation, 10 k is obtained
by shifting the result since characteristic k is the 1-digit
integer. The approximation of logarithm am + b is the 6-digit
fraction bounded by 0≤ am + b < 1, so 10 am+ b is obtained by
approximation.
k
Anti log
10( M )' = 10 ( cm + d ) . (4)
The absolute error is defined as:
k am+
b
Eabs
= 10 (10 − ( cm+ d))
. (5)
The percent error is defined as:
cm + d
E
per
= 1− . (6)
10
am+
b
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For example, a decimal logarithm M is assumed
as M = 4.514562 , which represents the logarithm of a 7-digit
fixed-point number, and it is consistent with the mantissa
region of the decimal-32 floating point number in IEEE-754r.
According to the algorithm described above,
4 0.514562
10 M log( ) 10 k 10 am +
= Anti M = b = 10 10 in which
10 am+ b is achieved by a linear approximation and 10 k is
obtained by a shift operation.
The mean-squared error is defined as (7), here, 1>m 2 mm 1 0
2
2 1 m2
am+
b
E = { 10 − ( cm+
d)
} dm
m − m
. (7)
m1
To minimize
2 1
2
E with respect to c and d, it is necessary that
2
∂E
2
+
= 0= −2 {(10 ) − ( + )}
∂
m am b
m cm d dm, (8)
c
m1
2
∂E
2
+
= 0= −2 {(10 ) − ( + )}
∂
m am b
cm d dm . (9)
d
m1
Thus, according to (7), (8), and (9), the coefficients c and
d can be determined to achieve the minimal mean-squared
error for any partition of the interval [0,1) . The minimal
mean-squared error was used to determine c and d in binary
antilogarithms [6]. However, to guarantee certain accuracy,
the maximal absolute error is the better parameter than the
mean squared error and the percent error. Thus, tuning the
obtained coefficients is proposed as a means to achieve the
minimum absolute error. Figure 1 demonstrates the
optimization of linear approximation for minimum absolute
error in 1 partition, in which the curve of the original absolute
error is moved and the optimized absolute error is reduced
from the original linear approximation’s 1.945 to 1.214.
the same dynamic range of 9-bit binary accuracy, is
sufficiently accurate for some DSP applications. This method
determines the bound of partition regions as well as the
coefficients of linear approximation in each region. The
optimized coefficients can guarantee minimum absolute error
with relative small mean-squared error with least partition
region numbers.
First, the absolute error restriction for achieving 10 -3
accuracy of antilogarithm, and the initial bound of partition
region are set. Second, a tuning region for coefficients
optimization is manually defined, in which the determined
coefficients according to (7), (8) and (9) are adjusted and the
partition region is corrected simultaneously to keep maximal
absolute errors smaller than the absolute error restriction.
Thus, the bound of partition regions and coefficients can
acquire the minimum error. After optimization, the decimal
logarithmic curve is divided into 36 partition regions. To
minimize the complexity of the implementation of the
antilogarithmic unit while keeping the accuracy of 10 -3 , the
coefficients, c and d are truncated to 5 digits, respectively. In
doing so 45 partition regions are obtained. The result of
c(5digits)×m(5digits)+d(5digits) gives the result for
implementing linear approximation of the decimal
antilogarithmic unit and guarantee 10 -3 accuracy for any 7-
digit fixed-point decimal number. Table I shows the
coefficients and bound of partition regions, maximal positive
and negative absolute errors of the proposed decimal-todecimal
antilogarithmic unit.
NO
YES
Y=1?
START
Determine the bound of partition
[X, Y] , Initial X=L_min, Initial Y=L_min+STEP
STEP=0.001
Decide the coefficients c and d
for mean-squared error
NO
YES
Y=1?
10
8
6
Linear Approxmation Analysis of Decimal Antilog
10 m curve
Original Linear Approxmation
Adjusted Linear Approximation
Original Absolute Error
Optimized Absolute Error
Original Max Absolute Error
Optimized Max Absolute Error
X=X
Y=Y+STEP
Define the Tuning Range manually and
adjust the coefficients for minimum error
YES
Minimum
Error

TABLE I.
PARAMETERS OF LINEAR APPROXIMATION FOR A DECIMAL ANTILOGARITHMIC CONVERTER
Partition Region c d Max +Abs Error Max –Abs Error
1 [0.000 0.039] 2.4248 0.99930 0.684317E-3 -0.930285E-3
2 [0.040 0.084] 2.6616 0.98923 0.798574E-3 -0.809191E-3
3 [0.085 0.129] 2.9496 0.96463 0.856913E-3 -0.867725E-3
4 [0.130 0.172] 3.2627 0.92397 0.844411E-3 -0.872633E-3
5 [0.173 0.211] 3.5844 0.86844 0.679335E-3 -0.853829E-3
6 [0.212 0.249] 3.9171 0.79815 0.841876E-3 -0.893172E-3
7 [0.250 0.286] 4.2745 0.70872 0.756582E-3 -0.799898E-3
8 [0.287 0.322] 4.6438 0.60283 0.823262E-3 -0.865506E-3
9 [0.323 0.356] 5.0362 0.47630 0.846450E-3 -0.923869E-3
10 [0.357 0.387] 5.4275 0.33669 0.671638E-3 -0.732032E-3
11 [0.388 0.417] 5.8208 0.18416 0.644767E-3 -0.855853E-3
12 [0.418 0.446] 6.2299 0.01338 0.738941E-3 -0.897674E-3
13 [0.447 0.476] 6.6694 -0.18309 0.829339E-3 -0.913325E-3
14 [0.477 0.500] 7.1005 -0.38826 0.696594E-3 -0.754848E-3
15 [0.501 0.520] 7.4799 -0.57838 0.406162E-3 -0.530416E-3
16 [0.521 0.546] 7.8739 -0.78415 0.718181E-3 -0.868334E-3
17 [0.547 0.569] 8.3263 -1.0313 0.677309E-3 -0.602936E-3
18 [0.570 0.590] 8.7566 -1.2764 0.534182E-3 -0.575841E-3
19 [0.591 0.612] 9.2010 -1.5389 0.656037E-3 -0.618655E-3
20 [0.613 0.635] 9.6902 -1.8387 0.718669E-3 -0.742884E-3
21 [0.636 0.653] 10.164 -2.1397 0.375793E-3 -0.632906E-3
22 [0.654 0.672] 10.618 -2.4367 0.476620E-3 -0.797813E-3
23 [0.673 0.692] 11.078 -2.7462 0.603285E-3 -0.729004E-3
24 [0.693 0.711] 11.590 -3.1006 0.574145E-3 -0.661232E-3
25 [0.712 0.728] 12.101 -3.4645 0.655445E-4 -0.961083E-3
26 [0.729 0.748] 12.628 -3.8487 0.622556E-3 -0.701621E-3
27 [0.749 0.765] 13.150 -4.2394 0.364906E-3 -0.812337E-3
28 [0.766 0.779] 13.632 -4.6080 0.289514E-3 -0.544311E-3
29 [0.780 0.791] 14.046 -4.9308 0.000000E-3 -0.717038E-3
30 [0.792 0.803] 14.464 -5.2614 0.288500E-3 -0.463958E-3
31 [0.804 0.818] 14.900 -5.6123 0.173857E-3 -0.825859E-3
32 [0.819 0.833] 15.424 -6.0409 0.477911E-3 -0.554259E-3
33 [0.834 0.848] 15.966 -6.4928 0.347947E-3 -0.720727E-3
34 [0.849 0.863] 16.527 -6.9689 0.269096E-3 -0.837693E-3
35 [0.864 0.878] 17.108 -7.4705 0.376626E-3 -0.767618E-3
36 [0.879 0.893] 17.717 -8.0057 0.258218E-3 -0.958477E-3
37 [0.894 0.905] 18.289 -8.5168 0.176663E-4 -0.931448E-3
38 [0.906 0.919] 18.844 -9.0196 0.324158E-3 -0.658204E-3
39 [0.920 0.932] 19.439 -9.5669 0.271120 E-3 -0.883869E-3
40 [0.933 0.947] 20.098 -10.182 0.504407E-3 -0.855058E-3
41 [0.948 0.961] 20.756 -10.806 0.268748E-3 -0.821870E-3
42 [0.962 0.972] 21.338 -11.365 0.547859E-3 -0.295290E-3
43 [0.973 0.983] 21.883 -11.895 0.526360E-3 -0.350400E-3
44 [0.984 0.994] 22.438 -12.441 0.287008E-3 -0.644965E-3
45 [0.995 0.999] 22.878 -12.878 0.206594E-3 -0.226477E-3
1.5 x 10-3 Decimal Linear Approximation Absolute Error Analysis
Absolute Error
Max.+ Absolute Error
1 Max. - Absolute Error
1.5 x 10-3 Decimal Linear Approximation Percent Error Analysis
Percent Error
Max.+ Percent Error
1 Max. - Percent Error
0.5
0.5
Absolute Error
0
Percent Error
0
-0.5
-0.5
-1
-1
-1.5
10 0 10 1 10 2 10 3 10 4 10 5
The N value
-1.5
10 0 10 1 10 2 10 3 10 4 10 5
The N value
Figure 3. Absolute Error Analysis of Decimal Antilogarithmic Converter
Figure 4. Percent Error Analysis of Decimal Antilogarithmic Converter
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IV. HARDWARE IMPLEMENTATION
Figure 5 shows the architecture of the proposed 7-digit
fixed-point decimal antilogarithmic converter. It takes one
clock cycle to achieve the approximation result of the
antilogarithms of a 7-digit fixed-point decimal number. The
hardware implementation of this antilogarithmic converter
includes three parts. The first part consisted of a characteristic
decoder tells the shifter register how many digits should be
shifted according to the characteristic part of logarithms; the
second part mainly composed of a size of 2 7 × 20coefficients
ROM and the linear approximation logic completes the
decimal linear approximation of antilogarithms; the third part
is a shifter which can shift the linear approximation result to
correct antilogarithm.
detail in [7], and then the linear approximation is achieved by
the carry-save-tree and carry-propagation-addition. The
decimal antilogarithmic converter is implemented only using
combinational logic so that antilogarithm results can be
obtained in a single clock cycle.
V. IMPLEMENTATION RESULTS
The proposed architecture based on decimal linear
approximation algorithm for decimal-to-decimal
antilogarithmic converter is modeled in VHDL and
implemented using a Xilinx Virtex2p XC2VP30 FPGA board
with package ff1517 and speed -7. The implementation results
of this decimal-to-decimal antilogarithmic convert are shown
in Table II.
TABLE II. IMPLEMENTATION RESULTS
Xilinx Virtex2p XC2VP30 Device Utilization Summary
Logic Utilization Used Available Utilization
Number of occupied Slices 1077 13696 7%
Maximum Frequency
53.1 MHz
Latency
1 clock cycle
7
2 × 20
Figure 5. Architecture of Proposed Decimal Antilogarithmic Converter
At the beginning, a 7-digit fixed-point number is
represented by 28-bit BCD code. The 28-bit BCD code
includes 4-bit characteristic or integer part and 24-bit mantissa
part which are format of decimal logarithm result. The shifter
detector determines how many digits should be shifted in
shifter register according to the characteristic part of
logarithms. The mantissa part of logarithms is sent to the
coefficients detector and the corresponding coefficients are
chosen from the ROM (realized by dual port BRAM IP
provided by XILINX) according to the 4-bit signal from
coefficients detector. The coefficient c is multiplied with 5-
digit of MSB of m and then added to the coefficient d. Finally,
the result of c(5digits)×m(5digits)+d(5digits) is shifted
according to the signal from shifter detector. The results from
shifter register are used for linear approximation for decimal
antilogarithmic unit.
The linear approximation logic can be realized by a
combinational decimal multiplication and a decimal addition.
To reduce the circuit complexity and improve the performance
of Antilogarithmic converter, the architecture of linear
approximation logic is designed according to the literature [7]-
[8]. A 1-digit decimal carry-look-ahead adder is designed
according to the literature [8], and this decimal carry-lookahead
adder is used to create a carry-save-adder tree. When
the 5-digit coefficients and 5-digit m are sent to the linear
approximation logic, the partial product is firstly generated in
the block of partial product generation which is presented in
VI. CONCLUSIONS
The proposed decimal antilogarithmic converter based on
decimal linear approximation algorithm can guarantee 10 -3
accuracy for any 7-digit fixed-point decimal number. It a) is
error-free in conversion between decimal and binary format,
and b) uses the optimization process of linear approximation
for minimal absolute error. The decimal antilogarithmic
converter takes one clock cycle to achieve the approximation
result. We believe, the presented architecture can be modified
to reduce complexity and in turns, achieves higher speed and
less area.
ACKNOWLEDGMENT
The authors would like to acknowledge the Natural
Science and Engineering Research Council of Canada
(NSERC) for its support to this research work.
REFERENCES
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