Scan design techniques – solutions to recommended exercises

Introduction to DFT Techniques in Digital Circuits - ©2002 jmf@fe.up.pt
Scan design techniques – solutions to recommended exercises
1- Yes, since an error signal (F=0/1) will be present at the primary output,
between the first and second clock pulses.
(initial value > after 1st CLK pulse > after 2nd CLK pulse)
D
Q
0 > 0 > 1
0 > 0 > 1
CLK
1 > 1 > 0
F
1/1 > 0/1 > 1/1
A=1
CLK
D
CLK
Q
0 > 1 > 1
X s@1
1/1 > 0/1 > 0/1
1/1 > 0/1 > 0
Exercise 1
2- Set A=1 and apply one clock pulse.
F
0/0 > 1/0
A=1
D
Q
0/0 > 1/0 X s@0
D
Q
0 > 0
CLK
CLK
/Q
CLK
/Q
1 > 1
Exercise 2
3- No, because A=0 does not activate the fault (a 0 is driven to node X s@0, and as
such we’ll never know whether or not it could be driven to 1).
4- Exercise 4-a): set (A,B)=(0,1) and apply one clock pulse. The initial state is not
relevant, since the proposed test procedure enables fault activation and error
signal propagation regardless of the initial value present at the FF output.
Exercise 4-b): Assuming that the initial state is Q=0, set (A,B)=(0,0) and apply
one clock pulse. If the initial state is Q=1, the error signal does not propagate
through the lower AND gate. However, the application of one clock pulse will
reset the FF (since D=0 when Q=1), and the previous procedure will be
applicable once again: simply set (A,B)=(0,0) and apply another clock pulse.
Scan design techniques – solutions to recommended exercises Page 1 / 3

Introduction to DFT Techniques in Digital Circuits - ©2002 jmf@fe.up.pt
A=0
B=1
X
0/1
X s@1
0/1
D
Q
F=0/1
0
X
0
CLK
CLK
/Q
Exercise 4-a)
A=0
1
0
B=0
1/0
D
Q
F=1/0
X
s@0
1/0
1
1
1/0
CLK
CLK
/Q
Exercise 4-b)
5- (Entrada primária: Primary input; Saída primária: Primary output; Estado seguinte:
Next state; Estado actual: Present state; Modo de teste: Test mode; Entr. série: Serial
input; Saída série: Serial output) Setting (X,Y)=(0,0) and (Q1,Q0)=(X,1) will
activate the fault and propagate the error signal to the output of the OR gate.
As such, the following sequence may be used:
- Set (Y,X)=(0,0), so that the fault is activated when we get to state
(Q1,Q0)=(X,1)
- Set (serial input, test mode)=(1,1) to move into scan mode and prepare to
scan 1s
- Apply two clock pulses (the fault will be activated when the second clock
pulse is applied)
- Set (serial input, test mode)=(X,0) to capture the error signal into Q1
- Apply one clock pulse (to capture the error signal present at the OR gate
output)
- Set (serial input, test mode)=(X,1) to move into scan mode (so that the
error signal may be shifted out)
- Apply one clock pulse: this will bring the error signal into the serial output
Scan design techniques – solutions to recommended exercises Page 2 / 3

Introduction to DFT Techniques in Digital Circuits - ©2002 jmf@fe.up.pt
6- Applying a 0 to primary input A is sufficient, since this is enough to activate the
fault and propagate the error signal to primary output D0 (no clock pulses are
required).
0
A
X s@0
0
1
1/0
0
0
0
D1
0
1/0
1/0
1
0
0
1/0
D0
0
0
Q1
Q
D
D1
1
/Q1
Q
CLK
0
Q0
Q
D
D0
1
/Q0
Q
CLK
CLK
Exercise 6
Scan design techniques – solutions to recommended exercises Page 3 / 3