ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ...

4. MODELING OF PROPOSED DVR Mustafa İNCİ
In the proposed phase freezing method, load side voltage is used to generate
phase information shown in Figure 4.19. The phase angle of load side voltage is
written to an array by two periods which each perios is 1000 sample. When sag
occurs at a time, EPLL detects sag and sends enable signal (i1); then the phase
information of one period before sag initiated is used as output phase. So, the phase
is freezed and used during the sag. When sag finishes, instant phase information is
used as output again. This process repeats itself for every sample time (Köroğlu,
2012). The proposed system is simulated using presag compensation method. Phase
freezing process is shown in Figure 4.20. The system in Figure 4.21 has a fault 30%
sag with 12 o angle jump initiates at 0.3s with a duration of 0.1s. It explains to
achieve phase freezing process between ϑ andϑ .
s presag
Figure 4.20. Block diagram of the phase freezing in DVR control
Figure 4.21. Reference voltages generated with In-Phase and Pre-Sag methods
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