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4. MODELING <strong>OF</strong> PROPOSED DVR Mustafa İNCİ • Inverter Circuit • Output Filter • DC-DC Converter 4.2.1. Design of Inverter Circuit The inverter circuit is used to inject controlled voltage and maintain the desired output voltage. The injected voltage is generated by accurately controlling the switches in the inverter. The most common inverter topologies are the two- or three-level three-phase converter used in DVR. Another popular converter topology is the H-bridge cascade inverter. For higher power applications, the use of two-level voltage converters becomes difficult to perform because of switch ratings and efficiencies. One solution is to use multilevel voltage-source converters which allow high power-handling capability than the two level and H-bridge inverters. Figure 4.3. Single phase symmetrical five level diode clamped inverter 47
4. MODELING <strong>OF</strong> PROPOSED DVR Mustafa İNCİ Among the different topologies of multilevel converters, the most popular are: diode clamped inverters, flying-capacitor inverters, and cascade H-bridge inverters(Patil et al., 2012). An m-level diode-clamped multilevel inverter typically consists of m-1 capacitors on the dc bus and produces m levels of the phase voltage(Ozdemir et al., 2007). Figure 4.3 presents a single-phase diode-clamped inverter with two three-level legs. In this case, the dc-link is composed of two capacitors. For proper modulation and to avoid excessive voltage on switches, the voltage on the dc-link capacitors should be the same(Stala,2011). V p = V N (4.1) Proposed topology consists of two capacitors on dc bus and generates fivevoltage levels of phase voltage in inverter. Inverter structure consists of three single phase five level diode clamped inverter for each phases. In this wise, it can compensate balanced and unbalanced voltage sag/swell. Also, each diode clamped inverter generates five voltage level (-Vdc, -0.5Vdc, 0, 0.5Vdc,Vdc). The voltage levels and their corresponding switch states of inverter for each five level diode clamped inverter are shown in Table 4.2. State condition 1 means the switch is ON, and state 0 means the switch is off. 48
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ÇUKUROVA UNIVERSITY INSTITUTE OF N
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ABSTRACT MSc THESIS MODELING AND AN
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ACKNOWLEDGEMENTS First and foremost
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3.2.2.1. Inverters ................
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VII
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LIST OF FIGURES PAGES Figure 1.1. D
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Figure 5.3. Injected voltages by us
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Page 18 and 19: LIST OF ABBREVATIONS A AC APF ASD C
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5. SIMULATION RESULTS AND CASE STUD
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6. CONCLUSION Mustafa İNCİ 6. CON
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6. CONCLUSION Mustafa İNCİ • En
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DELFINO, B., FORNARI, F., PROCOPIO,
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KARIMI-GHARTEMANI M., IRAVANI M.R.
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OĞUZ, G., 2004. Performance Of A D
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TESTA A., AKRAM M.F., BURCH R., CAR
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BIOGRAPHY Mustafa İNCİ was born i
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APPENDIX 123
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LIST OF PUBLICATIONS International
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