ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ...
ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ... ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ...
LIST OF FIGURES PAGES Figure 1.1. DVR structure (Vilathgamuwa et al, 2002) ............................................... 2 Figure 2.1. Basic disturbances: (a) Causes at customer side, (b) Causes at utility side and (c) Affected equipment (Köroğlu,2012)..................... 7 Figure 2.2. Percentage occurrences of PQ disturbances in equipment interruptions (Köroğlu,2012) .................................................................. 7 Figure 3.1. The Basic Structure of Dynamic Voltage Restorer (Vilathgamuwa et al, 2002) ................................................................................................... 14 Figure 3.2. DVR connected in a medium voltage level power system ...................... 16 Figure 3.3. H-Bridge Inverter..................................................................................... 18 Figure 3.4. DVR with no energy storage and supply-side-connected rectifier .......... 20 Figure 3.5. DVR with no energy storage and load-side-connected rectifier .............. 20 Figure 3.6. Location of a DC-DC Converter in a DVR ............................................. 21 Figure 3.7. System-level requirements for DVR with ac/ac converter. ..................... 22 Figure 3.8. (a), (b) and (c) Equivalent circuit of system shown in Figure 3.1 ........... 26 Figure 3.9. Location of inverter-side and line-side filters in DVR ............................ 28 Figure 3.10. Inverter-side filter in DVR..................................................................... 29 Figure 3.11. Scheme of the protection mode ............................................................. 32 Figure 3.12. Scheme of the standby mode ................................................................. 32 Figure 3.13. Vector diagram of pre-sag compensation .............................................. 34 Figure 3.14. Vector diagram of in-phase compensation ............................................ 35 Figure 3.15. Phasor diagram of the phase advance compensation method ................ 36 Figure 3.16. Open Loop Control Method .................................................................. 37 Figure 3.17. Block diagram representation of DVR system with openloop controller(Vilathgamuwa et al., 2002) .......................................... 38 Figure 3.18. Block diagram representation of DVR system with closed loop controller(Vilathgamuwa et al., 2002). ......................................... 40 Figure 4.1. The proposed multilevel inverter based DVR structure with full bridge DC-DC Converter ........................................................................ 45 Figure 4.2. Three-phase uncontrolled six pulse rectifier............................................ 46 Figure 4.3. Single phase symmetrical five level diode clamped inverter .................. 47 X
Figure 4.4. Equivalent Circuit for Inverter Side Filter ............................................... 50 Figure 4.5. Block Diagram of Single Phase PWM-VSI............................................. 51 Figure 4.6. The Frequency Response of the Inverter Side Connected Filter ............. 53 Figure 4.7. Phase Plot of the Inverter Side Connected Filter ..................................... 54 Figure 4.8. Circuit diagram of full bridge DC–DC Converter ................................... 55 Figure 4.9. Timing diagram and basic waveforms for isolated full-bridge dc-dc converter ........................................................................................ 56 Figure 4.10. Structure of Enhanced Phase Locked Loop ........................................... 61 Figure 4.11. Conventional SRF based detection ........................................................ 65 Figure 4.12. Proposed SRF based phase detection (a) Phase A, (b) Phase B, (c) Phase C .................................................................... 66 Figure 4.13. Block diagram of the orthogonal signals generator based on SOGI-PLL ............................................................................................. 68 Figure 4.14. Block diagram of proposed method based on EPLL, SRF and SOGIPLL(Köroğlu,2012) ..................................................................... 69 Figure 4.15. (a) Busbar, (b) magnitude(sag depth) and (c) sag detection signals ..... 70 Figure 4.16 Phasor diagram of Pre-Sag Compensation methods ............................... 71 Figure 4.17. Conventional phase freezer unit(Köroğlu,2012) ................................... 72 Figure 4.18. Phasor subtraction .................................................................................. 73 Figure 4.19. Flow chart of proposed phase freezing (Köroğlu, 2012) ....................... 74 Figure 4.20. Block diagram of the phase freezing in DVR control ........................... 75 Figure 4.21. Reference voltages generated with In-Phase and Pre-Sag methods ...... 75 Figure 4.22. Proposed multiloop control method....................................................... 77 Figure 4.23. Comparison of Closed Loop and Open Loop in proposed DVR ........... 78 Figure 4.24. Generation of gate signals for each multilevel five level diode clamped inverter .................................................................................................. 79 Figure 4.25. The flow chart of DC-DC Controller..................................................... 80 Figure 4.26. Carrier and reference signals generated by PI controller....................... 81 Figure 4.27. Generation of gate signals for full bridge dc-dc converter .................... 82 Figure 5.1. PSCAD/EMTDC model of proposed DVR System ................................ 83 Figure 5.2. (a) Source side busbar voltages, (b) Voltage sag inception time and (c) Magnitude information for three sag detection methods ........................ 86 XI
- Page 1 and 2: ÇUKUROVA UNIVERSITY INSTITUTE OF N
- Page 3 and 4: ABSTRACT MSc THESIS MODELING AND AN
- Page 5 and 6: ACKNOWLEDGEMENTS First and foremost
- Page 7 and 8: 3.2.2.1. Inverters ................
- Page 9 and 10: VII
- Page 14 and 15: Figure 5.3. Injected voltages by us
- Page 16 and 17: LIST OF SYMBOLS C : DC Link Capacit
- Page 18 and 19: LIST OF ABBREVATIONS A AC APF ASD C
- Page 20: 1. INTRODUCTION Mustafa İNCİ 1. I
- Page 23 and 24: 1. INTRODUCTION Mustafa İNCİ 4
- Page 25 and 26: 2. POWER QUALITY Mustafa İNCİ 2.1
- Page 27 and 28: 2. POWER QUALITY Mustafa İNCİ 2.2
- Page 29 and 30: 2. POWER QUALITY Mustafa İNCİ 2.2
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Figure 4.4. Equivalent Circuit for Inverter Side Filter ............................................... 50<br />
Figure 4.5. Block Diagram of Single Phase PWM-VSI............................................. 51<br />
Figure 4.6. The Frequency Response of the Inverter Side Connected Filter ............. 53<br />
Figure 4.7. Phase Plot of the Inverter Side Connected Filter ..................................... 54<br />
Figure 4.8. Circuit diagram of full bridge DC–DC Converter ................................... 55<br />
Figure 4.9. Timing diagram and basic waveforms for isolated full-bridge<br />
dc-dc converter ........................................................................................ 56<br />
Figure 4.10. Structure of Enhanced Phase Locked Loop ........................................... 61<br />
Figure 4.11. Conventional SRF based detection ........................................................ 65<br />
Figure 4.12. Proposed SRF based phase detection (a) Phase A,<br />
(b) Phase B, (c) Phase C .................................................................... 66<br />
Figure 4.13. Block diagram of the orthogonal signals generator based on<br />
SOGI-PLL ............................................................................................. 68<br />
Figure 4.14. Block diagram of proposed method based on EPLL, SRF and<br />
SOGIPLL(Köroğlu,2012) ..................................................................... 69<br />
Figure 4.15. (a) Busbar, (b) magnitude(sag depth) and (c) sag detection signals ..... 70<br />
Figure 4.16 Phasor diagram of Pre-Sag Compensation methods ............................... 71<br />
Figure 4.17. Conventional phase freezer unit(Köroğlu,2012) ................................... 72<br />
Figure 4.18. Phasor subtraction .................................................................................. 73<br />
Figure 4.19. Flow chart of proposed phase freezing (Köroğlu, 2012) ....................... 74<br />
Figure 4.20. Block diagram of the phase freezing in DVR control ........................... 75<br />
Figure 4.21. Reference voltages generated with In-Phase and Pre-Sag methods ...... 75<br />
Figure 4.22. Proposed multiloop control method....................................................... 77<br />
Figure 4.23. Comparison of Closed Loop and Open Loop in proposed DVR ........... 78<br />
Figure 4.24. Generation of gate signals for each multilevel five level diode clamped<br />
inverter .................................................................................................. 79<br />
Figure 4.25. The flow chart of DC-DC Controller..................................................... 80<br />
Figure 4.26. Carrier and reference signals generated by PI controller....................... 81<br />
Figure 4.27. Generation of gate signals for full bridge dc-dc converter .................... 82<br />
Figure 5.1. PSCAD/EMTDC model of proposed DVR System ................................ 83<br />
Figure 5.2. (a) Source side busbar voltages, (b) Voltage sag inception time and (c)<br />
Magnitude information for three sag detection methods ........................ 86<br />
XI
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