ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ...

ÇUKUROVA UNIVERSITY 

INSTITUTE OF NATURAL AND APPLIED SCIENCES 

MSc THESIS 

Mustafa İNCİ 

MODELING AND ANALYSIS OF MULTILEVEL INVERTER BASED 

DYNAMIC VOLTAGE RESTORER WITH DC-DC CONVERTER 

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING 

ADANA, 2013






MSc THESIS 


We certify that the thesis titled above was reviewed and approved for the award of 

degree of the Master of Science by the board of jury on 27/06/2013. 

……………….................................. ………………................ …………………...................... 

Assoc. Prof. Dr. K. Çağatay BAYINDIR Prof. Dr. Mehmet TÜMAY Assoc.Prof. Dr. Ramazan ÇOBAN 

SUPERVISOR 

MEMBER 

MEMBER 

This MSc Thesis is written at the Department of Institute of Natural And Applied 

Sciences of Çukurova University. 

Registration Number: 

Prof. Dr. Mustafa GÖK 

Director 

Institute of Natural and Applied Sciences 

This thesis was supported by the Scientific Research Project Unit of Çukurova University for 

my thesis (Project Number: MMF2012YL23). 

Note: The usage of the presented specific declerations, tables, figures, and photographs either in this 

thesis or in any other reference without citiation is subject to "The law of Arts and 

Intellectual Products" number of 5846 of Turkish Republic.

ABSTRACT 

MSc THESIS 







Supervisor : Assoc. Prof. Dr. K. Çağatay BAYINDIR 

Year : 2013, Pages 126 

Jury : Assoc. Prof. Dr. K. Çağatay BAYINDIR 

: Prof. Dr. Mehmet TÜMAY 

: Assoc. Dr. Ramazan ÇOBAN 

Voltage, current, frequency deviations and waveform distortions that causes 

equipment failure, economical loss and several negative effects are known as power 

quality problems. Among the power quality problems, voltage sags and swells are 

the most significant disturbances. The dynamic voltage restorer (DVR) is the most 

effective and economical custom power device applied to protect sensitive loads 

from voltage sags and swells. 

In this thesis, dynamic voltage restorer with dc-dc converter is modeled in 

PSCAD/EMTDC. DC-DC converter is used to maintain and control the dc voltage of 

the inverter during voltage sag. The developed topology permits to use in medium 

power systems. Multilevel inverter is used to allow high power-handling than the 

two-level inverter. EPLL, SRF and SOGI-PLL is used to detect and extract the 

voltage sag and swell. SOGI-PLL is a new method to extract voltage magnitude and 

phase angle simultaneously. The comparison results of EPLL, SRF and SOGI-PLL 

are presented in thesis. The performance of DVR is evaluated through simulations 

for compensation of balanced and unbalanced voltage sags. 

The main purpose of this thesis is analyzing and modeling of DVR, which 

protects a 1-MVA nonlinear load. The performance results of the proposed topology 

are presented with different cases by PSCAD/EMTDC program. 

Keywords: Dynamic Voltage Restorer, Voltage Sag and swell, Power Quality, DC- 

DC Converter, Multilevel Inverter 

I

ÖZ 

YÜKSEK LİSANS TEZİ 

DA-DA DÖNÜŞTÜRÜCÜLÜ ÇOK SEVİYELİ EVİRİCİ TABANLI DİNAMİK 

GERİLİM İYİLEŞTİRİCİNİN MODELLENMESİ VE ANALİZİ 


ÇUKUROVA ÜNİVERSİTESİ 

FEN BİLİMLERİ ENSTİTÜSÜ 

ELEKTRİK ELEKTRONİK MÜHENDİSLİĞİ ANABİLİM DALI 

Danışman : Doç. Dr. K. Çağatay BAYINDIR 

Yıl: 2013, Sayfa 126 

Jüri : Doç. Dr. K. Çağatay BAYINDIR 

: Prof. Dr. Mehmet TÜMAY 

: Doç. Dr. Ramazan ÇOBAN 

Ekipman bozulmaları, ekonomik kayıp ve çeşitli negatif etkilere sebep olan 

gerilim, akım ve frekans sapmaları ve dalga şeklindeki bozulmalar güç kalitesi 

problemleri olarak bilinir. Gerilim düşmeleri ve yükselmeleri, güç kalitesi 

problemleri içinde en önemli bozukluklardır. Dinamik gerilim iyileştirici hassas ve 

lineer olmayan yükleri gerilim düşme ve yükselmelerinden korumak için en etkili ve 

ekonomik özel güç cihazıdır. 

Bu tez çalışmasında, da-da dönüştürücülü dinamik gerilim iyileştiricinin 

PSCAD/EMTDC’de modellemesi yapılmıştır. Da-da dönüştürücü gerilim düşmesi 

esnasında eviricinin da geriliminin kontrolü ve korunması için kullanılır. Amaçlanan 

topoloji orta güç sistemlerde kullanıma izin vermektedir. İki seviyeli topolojilere 

gore daha yüksek güçlerde çalışma imkanı verdiği için çok seviyeli evirici 

kullanılmıştır. Gerilim düşme ve yükselmelerini sezmek ve tespit etmek amacı ile 

EPLL, SRF ve SOGI-PLL kullanılmıştır. Tezde; EPLL, SRF ve SOGI-PLL 

metodlarının karşılaştırma sonuçları yer almaktadır. Dengeli ve dengesiz gerilim 

düşmelerini gidermek için DGİ’nin performansı simülasyon çalışmaları ile 

değerlendirilmiştir. 

Bu tezin temel amacı, 1 MVA’l ık doğrusal olmayan yükü koruyan DGİ’nin 

analiz, modellenmesidir. Amaçlanan topolojinin performans sonuçları farklı 

durumlar için PSCAD/EMTDC programı ile sunulmuştur. 

Anahtar Kelimeler: Dinamik Gerilim İyileştirici, Gerilim Düşme ve Yükselmeleri, 

Güç Kalitesi, DA-DA Dönüştürücü, Çok Seviyeli Evirici 

II

ACKNOWLEDGEMENTS 

First and foremost I want to thank my supervisor, Assoc. Prof. Dr. K. Çağatay 

BAYINDIR. I appreciate all his contributions of time, ideas, and funding to make my 

MSc. Thesis. 

I am also grateful to Prof. Dr. Mehmet TUMAY, head of the Department, for 

his help and support during my study. 

I owe special thanks to Adnan TAN, Tahsin KÖROĞLU and Tuğçe 

DEMİRDELEN for his companionship and cooperation during my study. 

I would like also to thank and acknowledge the financial supported by 

Scientific Research Project Unit of Çukurova University for my thesis (Project 

Number: MMF2012YL23) 

I would like to thank to Fatih Elihoş, Ahmet Baykara, M. Selim AYGEN and 

all of my friends for everything. Lastly, I would like to thank my family for all their 

love and encouragement. 


III

CONTENTS 

PAGES 

ABSTRACT .................................................................................................................. I 

ÖZ ................................................................................................................................ II 

ACKNOWLEDGEMENTS ....................................................................................... III 

CONTENTS ............................................................................................................... IV 

LIST OF TABLES .................................................................................................. VIII 

LIST OF FIGURES .................................................................................................... X 

LIST OF SYMBOLS .............................................................................................. XIV 

LIST OF ABBREVATIONS .................................................................................. XVI 

1. INTRODUCTION .................................................................................................... 1 

1.1. Background ....................................................................................................... 1 

1.2. DVR .................................................................................................................. 1 

1.3. Outline of Thesis............................................................................................... 3 

2. POWER QUALITY ................................................................................................. 5 

2.1. Sources and Effects of Power Quality Problems .............................................. 6 

2.2. Power Quality Problems ................................................................................... 6 

2.2.1. Voltage Sag ............................................................................................ 8 

2.2.2. Voltage Swell ......................................................................................... 8 

2.2.3. Voltage Fluctuations .............................................................................. 8 

2.2.4. Harmonics .............................................................................................. 9 

2.2.5. Interharmonics........................................................................................ 9 

2.2.6. Transients ............................................................................................. 10 

2.2.7. Interruption ........................................................................................... 10 

2.3. Power Quality Standards ................................................................................. 11 

2.4. Solutions to Power Quality Problems .............................................................. 11 

3. FUNDAMENTALS OF DVR ................................................................................ 13 

3.1. Introduction..................................................................................................... 13 

3.2. Power Circuit and Topologies ........................................................................ 13 

3.2.1. Operation of DVR ................................................................................ 15 

3.2.2. Use of Converters in DVR ................................................................... 17 

IV

3.2.2.1. Inverters .................................................................................. 17 

3.2.2.2. Rectifier .................................................................................. 19 

3.2.2.3. DC-DC Converters ................................................................. 21 

3.2.2.4. AC-AC Converters ................................................................. 22 

3.2.3. Energy Storage ..................................................................................... 23 

3.2.4. Injection Transformer........................................................................... 24 

3.2.5. Filter ..................................................................................................... 27 

3.3. Control of DVR ............................................................................................... 31 

3.3.1. Sag/swell detection............................................................................... 31 

3.3.2. Operation Mode ................................................................................... 31 

3.3.2.1. Protection Mode ..................................................................... 32 

3.3.2.2. Standby Mode ......................................................................... 32 

3.3.2.3. Injection Mode ........................................................................ 33 

3.3.3. Voltage Injection Strategies ................................................................. 33 

3.3.3.1. Pre-sag compensation ............................................................. 34 

3.3.3.2. In-phase compensation ........................................................... 34 

3.3.3.3. Phase advance compensation .................................................. 35 

3.3.4. Reference Voltage Generation ............................................................. 36 

3.3.5. Voltage Control Methods ..................................................................... 37 

3.3.5.1. Open Loop .............................................................................. 37 

3.3.5.2. Closed Loop ............................................................................ 40 

3.3.6. Gate Signal Generation ........................................................................ 42 

4. MODELING OF PROPOSED DVR ...................................................................... 45 

4.1. Design of Grid and Load ................................................................................. 45 

4.2. Power Circuit Design of DVR Components ................................................... 46 

4.2.1. Design of Inverter Circuit .................................................................... 47 

4.2.2. Design of Inverter Filter ....................................................................... 50 

4.2.3. Design of DC-DC Converter ................................................................ 55 

4.3. Control System ................................................................................................ 59 

4.3.1. Sag Detection ....................................................................................... 60 

4.3.1.1. Enhanced Phase Locked Loop (EPLL) .................................. 60 

V

4.3.1.2. Synchronous Reference Frame (SRF) .................................... 64 

4.3.1.3. SOGI-PLL .............................................................................. 67 

4.3.1.4. Reference Generation Using Sag Detection Methods ............ 69 

4.3.2. Voltage Injection Strategy.................................................................... 71 

4.3.3. Voltage Control Strategy: Closed Loop ............................................... 76 

4.3.4. Gate Signal Generation ........................................................................ 78 

4.3.4.1. Inverter .................................................................................... 79 

4.3.4.2. DC-DC Converter ................................................................... 80 

5. SIMULATION RESULTS AND CASE STUDIES .............................................. 83 

5.1. Comparison of Sag Detection Methods (EPLL, SRF and SogiPLL) .............. 85 

5.2. Simulation Results for Open Loop and Closed Loop ...................................... 88 

5.2.1. Open Loop Voltage Control Method ................................................... 88 

5.2.1.1. Case 1: Single Phase Voltage Sag .......................................... 89 

5.2.1.2. Case 2: Two Phase Voltage Sag ............................................. 91 

5.2.1.3. Case 3: Three Phase Voltage Sag ........................................... 94 

5.2.2. Closed Loop Voltage Control Method ................................................. 97 

5.2.2.1. Case 4: Single Phase Voltage Sag .......................................... 98 

5.2.2.2. Case 5: Two Phase Voltage Sag ........................................... 100 

5.2.2.3. Case 6: Three Phase Voltage Sag ......................................... 103 

5.2.3. Comparison of Voltage Control Methods .......................................... 106 

6. CONCLUSION .................................................................................................... 109 

REFERENCES ......................................................................................................... 112 

BIOGRAPHY .......................................................................................................... 121 

APPENDIX .............................................................................................................. 122 

VI

VII

LIST OF TABLES 

PAGES 

Table 2.1. Typical characteristics of voltage disturbances ........................................ 11 

Table 4.1. Grid and load parameters of proposed system .......................................... 46 

Table 4.2. Switch states of five level diode clamped inverter ................................... 49 

Table 5.1. PSCAD/EMTDC Simulation Parameters ................................................. 84 

Table 5.2. System Parameters .................................................................................... 84 

Table 5.3. Simulated Load Parameters ...................................................................... 84 

Table 5.4. Simulation parameters of Voltage Source Inverter ................................... 84 

Table 5.5. Simulation parameters of Full Bridge DC-DC Converter ........................ 85 

Table 5.6. Injection Transformer Parameters ............................................................. 85 

Table 5.7. Sag inception and finish time for three methods....................................... 87 

Table 5.8. Comparison and RMS values of phase voltages in open loop and 

closed loop control method ................................................................... 107 

VIII

LIST OF FIGURES 

PAGES 

Figure 1.1. DVR structure (Vilathgamuwa et al, 2002) ............................................... 2 

Figure 2.1. Basic disturbances: (a) Causes at customer side, (b) Causes 

at utility side and (c) Affected equipment (Köroğlu,2012)..................... 7 

Figure 2.2. Percentage occurrences of PQ disturbances in equipment 

interruptions (Köroğlu,2012) .................................................................. 7 

Figure 3.1. The Basic Structure of Dynamic Voltage Restorer (Vilathgamuwa et 

al, 2002) ................................................................................................... 14 

Figure 3.2. DVR connected in a medium voltage level power system ...................... 16 

Figure 3.3. H-Bridge Inverter..................................................................................... 18 

Figure 3.4. DVR with no energy storage and supply-side-connected rectifier .......... 20 

Figure 3.5. DVR with no energy storage and load-side-connected rectifier .............. 20 

Figure 3.6. Location of a DC-DC Converter in a DVR ............................................. 21 

Figure 3.7. System-level requirements for DVR with ac/ac converter. ..................... 22 

Figure 3.8. (a), (b) and (c) Equivalent circuit of system shown in Figure 3.1 ........... 26 

Figure 3.9. Location of inverter-side and line-side filters in DVR ............................ 28 

Figure 3.10. Inverter-side filter in DVR..................................................................... 29 

Figure 3.11. Scheme of the protection mode ............................................................. 32 

Figure 3.12. Scheme of the standby mode ................................................................. 32 

Figure 3.13. Vector diagram of pre-sag compensation .............................................. 34 

Figure 3.14. Vector diagram of in-phase compensation ............................................ 35 

Figure 3.15. Phasor diagram of the phase advance compensation method ................ 36 

Figure 3.16. Open Loop Control Method .................................................................. 37 

Figure 3.17. Block diagram representation of DVR system with openloop 

controller(Vilathgamuwa et al., 2002) .......................................... 38 

Figure 3.18. Block diagram representation of DVR system with closed 

loop controller(Vilathgamuwa et al., 2002). ......................................... 40 

Figure 4.1. The proposed multilevel inverter based DVR structure with full 

bridge DC-DC Converter ........................................................................ 45 

Figure 4.2. Three-phase uncontrolled six pulse rectifier............................................ 46 

Figure 4.3. Single phase symmetrical five level diode clamped inverter .................. 47 

X

Figure 4.4. Equivalent Circuit for Inverter Side Filter ............................................... 50 

Figure 4.5. Block Diagram of Single Phase PWM-VSI............................................. 51 

Figure 4.6. The Frequency Response of the Inverter Side Connected Filter ............. 53 

Figure 4.7. Phase Plot of the Inverter Side Connected Filter ..................................... 54 

Figure 4.8. Circuit diagram of full bridge DC–DC Converter ................................... 55 

Figure 4.9. Timing diagram and basic waveforms for isolated full-bridge 

dc-dc converter ........................................................................................ 56 

Figure 4.10. Structure of Enhanced Phase Locked Loop ........................................... 61 

Figure 4.11. Conventional SRF based detection ........................................................ 65 

Figure 4.12. Proposed SRF based phase detection (a) Phase A, 

(b) Phase B, (c) Phase C .................................................................... 66 

Figure 4.13. Block diagram of the orthogonal signals generator based on 

SOGI-PLL ............................................................................................. 68 

Figure 4.14. Block diagram of proposed method based on EPLL, SRF and 

SOGIPLL(Köroğlu,2012) ..................................................................... 69 

Figure 4.15. (a) Busbar, (b) magnitude(sag depth) and (c) sag detection signals ..... 70 

Figure 4.16 Phasor diagram of Pre-Sag Compensation methods ............................... 71 

Figure 4.17. Conventional phase freezer unit(Köroğlu,2012) ................................... 72 

Figure 4.18. Phasor subtraction .................................................................................. 73 

Figure 4.19. Flow chart of proposed phase freezing (Köroğlu, 2012) ....................... 74 

Figure 4.20. Block diagram of the phase freezing in DVR control ........................... 75 

Figure 4.21. Reference voltages generated with In-Phase and Pre-Sag methods ...... 75 

Figure 4.22. Proposed multiloop control method....................................................... 77 

Figure 4.23. Comparison of Closed Loop and Open Loop in proposed DVR ........... 78 

Figure 4.24. Generation of gate signals for each multilevel five level diode clamped 

inverter .................................................................................................. 79 

Figure 4.25. The flow chart of DC-DC Controller..................................................... 80 

Figure 4.26. Carrier and reference signals generated by PI controller....................... 81 

Figure 4.27. Generation of gate signals for full bridge dc-dc converter .................... 82 

Figure 5.1. PSCAD/EMTDC model of proposed DVR System ................................ 83 

Figure 5.2. (a) Source side busbar voltages, (b) Voltage sag inception time and (c) 

Magnitude information for three sag detection methods ........................ 86 

XI

Figure 5.3. Injected voltages by using three sag detection methods .......................... 87 

Figure 5.4. Source side voltages by using EPLL, SRF and SogiPLL methods ......... 88 

Figure 5.5. Simulation results for Case 1 ................................................................... 89 

Figure 5.6. DC link voltage for Case 1 ..................................................................... 90 

Figure 5.7. RMS Characterisics for Case 1 ................................................................ 91 

Figure 5.8. Simulation results for Case 2 ................................................................... 92 

Figure 5.9. DC link voltage for Case 2 ...................................................................... 93 

Figure 5.10. RMS characteristics for Case 2.............................................................. 94 

Figure 5.11. Simulation results for Case 3 ................................................................. 95 

Figure 5.12. DC link voltage for Case 3 .................................................................... 96 

Figure 5.13. RMS characteristics for Case 3............................................................. 97 

Figure 5.14. Simulation results for Case 4 ................................................................. 98 

Figure 5.15. DC link voltage for Case 4 .................................................................... 99 

Figure 5.16. RMS characterisics for Case 4 ............................................................. 100 

Figure 5.17. Simulation results for Case 5 ............................................................... 101 

Figure 5.18. DC link voltage for Case 5 .................................................................. 102 

Figure 5.19. RMS characteristics for Case 5............................................................ 103 

Figure 5.20. Simulation results for Case 6 ............................................................... 104 

Figure 5.21. DC link voltage for Case 6 .................................................................. 105 

Figure 5.22. RMS characteristics for Case 6............................................................ 106 

XII

XIII

LIST OF SYMBOLS 

C : DC Link Capacitor Value 

DC 

C 

f 

: Filter Capacitor Value 

: Injection Transformer Rating 

e (t) : Difference of input and synchronized fundamental components of 

f 

0 

f 

s 

I dc 

I 

s 

I 

L 

Enhanced Phase Locked Loop 

: Cut-off frequency 

: Switching frequency 

: DC link Capacitor Current 

: Source-Side Current 

: Load-Side Current 

I Re 

: Rectifier Current 

ctifier 

K 

i 

L 

f 

m 

a 

: Turns ratio of the injection transformer 

: Filtre Inductor Value 

: Modulation index 

ms 

n 

N 

P 

N 

S 

: Miliseconds 

: Order of harmonics 

: Primary Winding of Transformer 

: Secondary Winding of Transformer 

S : Voltage Sag/Swell depth 

depth 

S 

c 

: Volt Amperes Rating of DC Link Capacitor 

u (t) : Input signal of Enhanced Phase Locked Loop 

V cappi 

V cap,ref 

V dclink 

V d 

: Error between Actual and Reference Values of DC link Capacitor 

Voltage 

: DC link Capacitor Voltage Reference Value 

: DC link Capacitor Voltage 

: D Component of SRF Transform 

XIV

̊ 

V dc,ref 

V q 

V l 

V presag 

V dclink,min 

error inphase 

: DC Link Reference Value 

: Q Component of SRF Transform 

: Calculated Line Value 

: Calculated Presag Value 

: Minimum Value of DC link Capacitor Voltage 

V 

, 

: The magnitude of the injected voltage with In-Phase Compensation 

V 

error , presag 

: The magnitude of the injected voltage with Pre-Sag Compensation 

V : Output Voltage of hybrid cascade diode clamped inverter 

output 

V : Output voltage of LC Filter 

filter 

V : Injected Voltage by DVR 

inj 

V 

inv 

V 

inv (n) 

V 

L 

V 

o( n) 

V 

p 

V 

sag 

V 

source 

: Output voltage of the PWM inverter 

: nth order harmonic voltages on the input of inverter 

: Load Voltage 

: nth order harmonic voltages on the output of inverter 

: Voltage on the high voltage side of the injection transformer 

: Magnitude of Sagged Voltage 

: Source Voltage 

y (t) 

: Synchronized fundamental component of EPLL 

∆ ω (t) : Frequency deviation of EPLL 

θ (t) : The phase angle of Synchronized fundamental component of EPLL 

θ : The angle of the injected voltage with In-Phase Compensation 

error,inphase 

θ : Phase angle of Sagged Voltage 

sag 

θ : The angle of the injected voltage with Pre-Sag Compensation 

error, presag 

θ presag 

δ Vload 

μ 

: Pre-Sag Angle 

: Phase information of System Voltage 

: Micro 

: Degree 

XV

LIST OF ABBREVATIONS 

A 

AC 

APF 

ASD 

CP 

D 

DVR 

dB 

DC 

EMI 

EPLL 

FC 

FFT 

FT 

HV 

Hz 

IEC 

IEEE 

IGBT 

IRPT 

LPF 

LL 

MV 

MVA 

NPC 

PAC 

PCC 

PD 

PI 

: Amper 

: Alternating Current 

: Active Power Filter 

: Adjustable Speed Drives 

: Custom Power 

: Duty 

: Dynamic Voltage Restorer 

: deciBel 

: Direct Current 

: Electro Magnetic Interference 

: Enhanced Phase Locked Loop 

: Flying Capacitor 

: Fast Fourier Transform 

: Fourier Transform 

: High Voltage 

: Hertz 

: International Electrotechnical Commission 

: International Electrical Electronics Engineering 

: Insulated Gate Bipolar Transistor 

: Instantaneous Reactive Power Theory 

: Low Pass Filter 

: Line-to-Line 

: Medium Voltage 

: Mega Volt Amperes 

: Neutral Point Clamped 

: Phase AdvanceCompensation 

: Point of Common Coupling 

: Phase Detector 

: Proportional-Integrator 

XVI

PLL 

: Phase Locked Loop 

PQ 

: Power Quality 

PU 

: Per Unit 

PSCAD/EMTDC : Power System Computer Aided Design / 

Electromagnetic Transient DC Program 

PU 

: Per Unit 

PWM 

: Pulse Width Modulation 

RDFT 

: Recursive Discrete Fourier Transform 

RMS 

: Root Mean Square 

SLGF 

: Single Line to Ground Fault 

SOGI-PLL 

: Second Order Generalized Integrator Phase Locked 

Loop 

SPWM 

: Sinusoidal Pulse Width Modulation 

SMES 

: Superconducting Magnetic Energy Source 

SMPS 

: Switched Mode Power Supplies 

SRF 

: Synchronous Reference Frame 

STS 

: Static Transfer Switch 

THD 

: Total Harmonic Distortion 

UPS 

: Uninterruptible Power Supply 

V 

: Volts 

VA 

: Volt Amperes 

VCO 

: Voltage Conrol Oscillator 

VSC 

: Voltage Source Converter 

VSI 

: Voltage Source Inverter 

XVII

1. INTRODUCTION Mustafa İNCİ 

1. INTRODUCTION 

The study in this thesis consists of the design and control of Dynamic Voltage 

Restorer in medium power systems. The content and aim of study is provided 

comprehensively below. 

1.1. Background 

Electrical power quality become an important issue because of the change in 

the characteristics of loads connected to power system due to development of 

technology and increase in electricity demand. Voltage, current, frequency deviations 

and waveform distortions that cause equipment failure, economical loss and several 

negative effects are known as power quality problems. 

The most severe power quality problems in electrical systems are called as 

voltage sag and swell. Voltage sag is known as short duration reductions in the rms 

voltage. Another problem, voltage swell is defined as an increase in the rms voltage. 

Several custom power devices such as UPS, DVR, static series compensator etc. 

have been improved to solve these problems. Among these several custom power 

devices, Dynamic Voltage Restorer (DVR) is an effective solution to solve these 

power quality problems. 

1.2. DVR 

The dynamic voltage restorer (DVR) is the most effective and economical 

custom power device applied to protect sensitive loads from voltage sags and swells. 

Dynamic voltage restorer is a series connected device located between sensitive load 

and grid in system, it both detects voltage sags/swell problems and injects controlled 

voltage to system. To perform this process, a conventional DVR consists of inverter, 

dc-link capacitor, filter and transformer which will be extensively explained in thesis. 

1


1.3. Outline of Thesis 

The thesis consists of the following chapters: 

After this first chapter, in Chapter 2 Power Quality Problems; Sources and 

effects of power quality problems, power quality problems and their explanation, 

Power Quality Standards and solution of power quality problems are explained. 

Chapter 3 The Fundamentals of DVR gives an overview of available DVR 

system, the function of converters in power circuit configuration, filter and 

transformer design. It also includes control methods in available literature. 

The power circuit design of multilevel inverter based DVR components, sag 

detection methods, voltage injection strategies used in proposed DVR are explained 

in Chapter 4 Modeling of Proposed DVR. 

Simulation results which consist of comparison of sag/swell detection 

methods, voltage injection strategies (presag, in-phase) and voltage control strategies 

are given in Chapter 5 Simulation Results and Case Studies. Also, this chapter 

includes analysis of full bridge dc-dc converter for voltage sag compensation. 

3


4

2. POWER QUALITY Mustafa İNCİ 

2. POWER QUALITY 

The term “Power Quality” is defined as “Set of parameters defining the 

properties of power quality as delivered to the user in normal operating conditions 

in terms of continuity of supply and characteristics of voltage (symmetry, 

frequency, magnitude, waveform) in IEC. In IEEE Std. 1100-1 999, “Power Quality” 

is defined as “The concept of powering and grounding electronic equipment in a 

manner that is suitable to the operation of that equipment in a manner that is suitable 

to the operation of that equipment and compatible with the premise wiring system 

and other connected equipment (Ise et al., 2000). 

Power Quality just meant the ability of utilities to provide electric power 

without interruption. However, in recent years, power quality becomes an important 

concern to customers as well as utilities and facilities. Customers require higher 

quality of power than ever before due to the increase in critical load and electronic 

device. Power quality is different from reliability in view of the duration of events it 

deals with. It treats very short events with a few cycles or seconds duration. New 

power quality problems such as sag, swell, harmonic distortion, unbalance, transient, 

and flicker may impact on customer devices, causes malfunctions and cost on lost 

production and downtime. These problems should be measured and assessed more 

accurately than before (Won et al., 2003). 

Recently, an increased number of sensitive loads have been integrated into 

the electrical power systems. Consequently, the demand for high power quality and 

voltage stability has increased significantly (Meyer et al., 2008). Some basic 

criterions for power quality are constant rms value, constant frequency, symmetrical 

three-phases, pure sinusoidal wave shape and limited THD. These values should be 

kept between limits determined by standards if the power quality level is considered 

to be high. Power quality covers several types of problems of electrical supply 

and power system disturbances. The cost of power interruptions and disturbances 

can be quite high as a result of the important processes controlled and maintained 

by the sensitive devices (Dong et al., 2004). Sources and effects of power quality 

problems can be summarized as follows in 2.1. 

5


2.1. Sources and Effects of Power Quality Problems 

Power distribution systems, ideally, should provide their customers with an 

uninterrupted flow of energy at smooth sinusoidal voltage at the contracted 

magnitude level and frequency. However, in practice, power systems, especially the 

distribution systems, have numerous nonlinear loads, which significantly affect the 

quality of power supplies. As a result of the nonlinear loads, the purity of the 

waveform of supplies is lost. This ends up producing power quality problems (Jena). 

The distortion in the quality of supply power can be occurred because of various 

devices; some of the primary sources of distortion can be identified as below: 

• Power Electronic Devices 

• IT and Office Equipments 

• Arcing Devices 

• Load Switching 

• Large Motor Starting 

• Embedded Generation 

• Electromagnetic Radiations and Cables 

• Storm and Environment Related Causes etc. 

The growth of the nonlinear loads like the devices with switching power 

supplies have increased the current harmonics, EMI problems, unnecessary reactive 

power and power losses which causes distortion, harmonics, flicker phenomena, sag 

and swell conditions on the line voltages and other problems (Hosseini et al., 2006). 

2.2. Power Quality Problems 

The importance of power quality (PQ) has risen very considerably over the 

last two decades due to a marked increase in the number of equipment which is 

sensitive to adverse PQ environments, the disturbances introduced by nonlinear 

loads, and the proliferation of renewable energy sources, among others. At least 50% 

6


of all PQ disturbances are of the voltage quality type, where the interest is the study 

of any deviation of the voltage waveform from its ideal form. The best well-known 

disturbances are voltage sags and swells, harmonic and interharmonic voltages, and, 

for three-phase systems, voltage imbalances (Roncero-Sanchez et al., 2009). 

A number of national and local surveys helped to quantify the statistical 

aspects of this problem. The most common disturbances and the most commonly 

affected equipments are illustrated in Figure 2.1 (Emanuel et al., 1997). 

Figure 2.1. Basic disturbances: (a) Causes at customer side, (b) Causes at 

utility side and (c) Affected equipment (Köroğlu,2012) 

Another survey result is given in Figure 2.2 which shows the percentage 

occurrences of PQ disturbances in equipment interruptions (Köroğlu , 2012). 

Figure 2.2. Percentage occurrences of PQ disturbances in equipment interruptions 

(Köroğlu,2012) 

7


2.2.1. Voltage Sag 

Voltage sags are now one of the most important power quality problems in 

the distribution system. A voltage sag is a momentary decrease in the RMS ac 

voltage (10%–90% of the nominal voltage), at the power frequency, of duration from 

0.5 cycles to a few seconds. Voltage sags are normally caused by short-circuit faults 

such as a single-line-to-ground fault in the power system or by the starting up of 

induction motors of large rating. Voltage sags may cause the malfunction of voltagesensitive 

loads in factories, buildings, and hospitals (Kangarlu et al., 2010). 

Voltage sags can cause tripping of contactors, motor starters, relays, restarting 

expense of computers and shutdown of an entire production line. The sources of 

voltage sags are basically faults on adjacent feeders, lighting, short circuit event, start 

up of heavy loads, transformer energizing and motor starting (Bollen, 2001). 

2.2.2. Voltage Swell 

Voltage swell is defined as a short duration increasing in RMS supply with 

increase in voltage ranging from 1.1 pu to 1.8 pu of nominal supply. The main causes 

for voltage swell are switching of large capacitors or removal of heavy loads 

(Kangarlu et al., 2010). 

Voltage swells might not be as common as voltage sags, however are much 

more harmful and disruptive to static power converters. In fact, they may severely 

damage or trip them, causing shutdowns of entire processes. This overall situation 

has become even more critical given the recent industrial trend to increase operating 

voltages of power converters (a practice that has pushed semiconductor devices up to 

their limit. A closer look to this phenomenon is, hence, required (Burgos et al., 

2005). 

2.2.3. Voltage Fluctuations 

8


Voltage fluctuations are systematic variations of the voltage envelope or a 

series of random voltage changes. Arc furnaces are the most common cause of 

voltage fluctuations on the transmission and distribution system (Martinez, 1998). 

The voltage fluctuation is one of the major power quality problems in a weak power 

system, which feeds fluctuating loads, such as electric arc furnaces and arc welders. 

In general, the flicker components exhibit frequencies in the range 0.1 Hz to 30 Hz 

and are especially important due to visual irritation. Many reports indicate that a 

small voltage fluctuation from 0.3% to 0.5% in the frequency range of 6-10 Hz will 

cause visible incandescent lamp flickering and let people feel uncomfortable (Wu et 

al., 2006). 

2.2.4. Harmonics 

Harmonics can be defined as the spectral components at frequencies 

that are integer multiples of the ac system fundamental frequency (Testa et al., 

2007). The harmonic voltage and current distortion are strongly linked with 

each other because harmonic voltage distortion is mainly due to non-sinusoidal 

load currents. Current harmonic distortion requires overrating of series components 

like transformers and cables. As the series resistance increases with frequency, a 

distorted current will cause more losses than a sinusoidal current of the same rms 

value (Bollen, 2001). 

2.2.5. Interharmonics 

Interharmonics are spectral components at frequencies that are not integer 

multiples of the system fundamental frequency. Interharmonics can be observed 

in an increasing number of loads in addition to harmonics. The main sources of 

interharmonics are static frequency converters, cycloconverters, high voltage direct 

current(HVDC) transmission systems, induction motors, welding machines, arc 

furnaces, and all loads not pulsating synchronously with the fundamental power 

system frequency (Tayjasanant et al., 2005;Yacamini, 1996) 

9


2.2.6. Transients 

A transient is “that part of the change in a variable that disappears 

during transition from one steady state operating condition to another”. Another 

word in common usage that is often considered synonymous with transient is 

“surge” (Dugan et al, 2003). Transients can be be classified into two categories: 

“impulsive” and “oscillatory”: 

• Impulsive transients: Sudden, non-power frequency change in the steady 

state condition of the voltage, current or both 

• Oscillatory transients: Voltage or current whose instantaneous value 

changes polarity rapidly. 

2.2.7. Interruption 

In the European standard EN 50160 two terms are used (Nielsen et al., 2002): 

• Long interruptions: longer than three minutes. 

• Short interruptions: up to three minutes. 

Interruptions are typically caused by different types of faults e.g. malfunction 

of protection equipment or lightning. In a system without redundancy a fault often 

leads to a long interruption, which requires manual intervention. Short interruptions 

are often caused by automatic reclosing after a fault. Short interruptions below three 

minutes are normally considered a voltage quality problem. Interruptions are a severe 

power quality problem, but in a wide range of industrial countries interruptions occur 

very rare, because of redundancy and high maintenance of the grid (Nielsen et al., 

2002). 

10


2.3. Power Quality Standards 

The specific characteristics of supply voltage have been defined in 

standards, which are used to determine the level of quality with reference to: 

frequency, voltage level, wave shape and symmetry of the three-phase voltage 

(Mofty et al., 2001). The IEEE 519-1992 and IEEE 1159-1995 describe the 

compatibility level required by equipment connected to the network, as well as 

the limits of emissions from the devices (IEEE Std. 519, 1992; IEEE Std.1159, 

1995). The characteristic properties of disturbances are shown in Table 2.1. 

Table 2.1. Typical characteristics of voltage disturbances 

Disturbance Typical Voltage Typical Duration 

Type Magnitude 

Sag 0.1-0.9 pu 0.5-30 cycle 

Swell 1.1-1.8 pu 0.5-30 cycle 

Flicker 0-1 % Steady state 

Interruption


• Lightning and surge arresters 

• Thyristor Based Static Switches 

• Energy Storage Systems 

• Electronic tap changing transformer 

• Harmonic Filter 

12

3. FUNDAMENTALS OF DVR Mustafa İNCİ 

3. FUNDAMENTALS OF DVR 

3.1. Introduction 

Among the power quality problems, voltage sags and swells are the most 

significant disturbances. In order to overcome these problems, power electronic 

converter based custom power devices are introduced recently. Inside of these 

devices, the dynamic voltage restorer is the most efficient and economical device to 

protect sensitive loads from voltage sags and swells. 

3.2. Power Circuit and Topologies 

DVR is a series connected device located between sensitive load and grid in 

system, it both detects voltage sag/swell problems and injects controlled voltage to 

system. Additionally, it can be used for harmonics compensation and transient 

reduction in voltage and fault current limitations in available literature. To perform 

these processes, DVR injects a controlled voltage in series with the supply voltage in 

phase via injection transformer to restore the power quality. 

The basic structure of a conventional DVR is shown in Figure 3.1. It can be 

divided into four categories: inverter, dc-link capacitor, filter and injection 

transformer. An inverter system is used to convert dc storage into ac form. Passive 

filter is responsible for eliminating the unwanted harmonic components generated in 

inverter. In this way, it converts inverter pwm output to sinusoidal waveform. 

Another component, energy storage unit such as batteries, supercapacitors, SMES 

etc. is used to provide energy requirement in DC form. Lastly, transformer injects 

controlled voltage and provides isolation between load and the system. 

13


3.2.1. Operation of DVR 

Dynamic voltage restorers (DVRs) are considered effective custom power 

devices for mitigating the impacts of upstream voltage disturbances on sensitive 

loads. The disturbances include voltage distortions and/or sudden changes in loadterminal 

voltage, in the form of sags or swells. By injecting a compensating voltage 

in series with the sensitive load terminal voltage during the disturbances, a DVR can 

maintain the load voltage at the desired amplitude and waveform. In the course of the 

compensation, however, a DVR will inevitably inject (absorb) a certain amount of 

active power to (from) the external system. The amount of the power exchange will 

dictate the severity of the sag/swell that can be ridden through by the load and the 

rating of the energy storage device required to undertake the task. In fact, by 

choosing an appropriate amplitude and phase angle of the DVR output injection 

voltage, one can control the injected/absorbed power such that compensation with 

zero or minimum power injection can be realised. This means either the minimum 

power-rating energy storage device can be incorporated into the design or the 

maximum load ride-through can be achieved with the given energy-storage capacity 

(Li et al., 2007). 

The intention is only to protect one consumer or a group of consumers with 

value added power. Applying a DVR in the medium or low voltage distribution 

system would often be possible and a radial grid structure is the only type of system 

considered here. In Europe three wire systems are common in the medium voltage 

systems and four wires in low voltage systems. In both systems the main purpose is 

to inject synchronous voltages during symmetrical faults and in some cases inject an 

inverse voltage component during non-symmetrical faults (Oğuz et al., 2004). A 

typical DVR connected system circuit at medium voltage (MV) distribution network 

is shown in Figure 3.2. The DVR essentially consists of a series connected injection 

transformer, a voltage source inverter (VSI), inverter output filter and an energy 

storage device connected to the dc link. The high voltage (HV) power system 

upstream to the DVR is represented by an equivalent voltage source which is 

transformed to MV level by a step-down transformer. The basic operation principle 

15


of the DVR is to inject an appropriate voltage in series with the supply through 

injection transformer when a PCC voltage sag is detected. MV loads or low voltage 

(LV) loads connected downstream after another step-down transformer are thus 

protected from the PCC voltage sag (Li et al., 2007). 

Figure 3.2. DVR connected in a medium voltage level power system 

Implemented at medium voltage level, the DVR can be used for high power 

applications or to protect a group of MV or LV consumers who would expect 

reduced costs per MVA by operating at MV level. But this implementation at 

medium voltage level also subjects the DVR to more frequent faults in the 

downstream load side. Large fault currents will flow through the DVR during a 

downstream fault before the opening of a circuit breaker. This large fault current will 

cause PCC voltage drop, which would affect the MV or LV loads on the other 

feeders connected to PCC (Figure 3.2). Furthermore, if not controlled properly, DVR 

might also contribute to the PCC voltage sag in the process of compensating the 

missing voltage, thus further worsening the fault situation. During downstream 

faults, passive control methods are often used to protect the DVR by enabling a 

bypass circuit (usually a slow mechanical bypass together with a fast solid-state 

switch), while allowing a large fault current to flow which could cause PCC voltage 

to drop. Compared to the passive protection of DVR, active control of DVR during a 

downstream fault makes the additional protection circuits unnecessary and the 

implementation easy. But the disadvantage is the requirement of higher 

compensation capacity from the DVR (Li et al., 2007). 

16


3.2.2. Use of Converters in DVR 

Numerous circuit topologies which are used for different functions are 

available for the DVR. These are: inverters, rectifiers, AC-AC converters and DC- 

DC converters. 

3.2.2.1. Inverters 

The most common inverter topologies are the two- or three-level three-phase 

converter where the dc-side capacitor(s) is connected alternately to all ac phases. The 

purpose of this capacitor is to mainly absorb harmonic ripple and, hence, it has a 

relatively small energy storage requirement, particularly when operating in balanced 

conditions. The size of this capacitor has to be increased, if needed, to provide 

voltage support in unbalanced conditions. Also, since the capacitor is shared between 

the three phases, sag on only one phase may cause a distortion in the injected current 

waveforms on the other phases (Al-Hadidi et al., 2008). 

Another popular converter topology is the H-bridge cascade inverter. A single 

phase of this converter is shown in Figure 3.3. Converters with this topology are 

suitable in power systems applications due to their ability to synthesize waveforms 

with reduced lower order harmonics and to attain higher voltages with a limited 

maximum device rating. The principal of operation for this topology is that each 

capacitor can be connected by means of the insulated-gate bipolar transistor (IGBT) 

switches so that its voltage contributes positively or negatively or not at all to the 

output waveform. This makes the control more complex in comparison with 

conventional two- or three-level converters. However, in contrast to such 

conventional topologies, the multilevel offers the following significant advantages 

(Al-Hadidi et al., 2008). 

1) Modularized circuit layout and packaging are possible because each level 

has the same structure. Increasing or reducing the number of modules permits the 

converter to be designed for any arbitrary voltage level in a straightforward manner. 

17


This also allows for the removal of the series transformer, thereby reducing size and 

cost. 

2) Each bridge can be controlled independently permitting efficient singlephase 

voltage compensation. 

3) The aspect of particular interest in this paper is the inherent energy storage 

capability of the capacitors which makes this topology ideal for the transient 

injection of real power. It is true that the H-bridge cascade topology requires larger 

capacitors due to second harmonics ripple on the capacitors, which could be seen as a 

disadvantage in comparison with traditional two- or three-level three-phase 

converters. However, the larger capacitors also provide additional energy storage 

capability which, if exploited, could turn this disadvantage into an advantage. The 

principle contribution of this paper is to devise a new control method that exploits 

the inherent stored energy of the capacitors in the most efficient manner to prolong 

the duration over which large unbalanced sags can be compensated (Al-Hadidi et al., 

2008). 

Figure 3.3. H-Bridge Inverter 

A multilevel converter was proposed to increase the converter operation 

voltage, avoiding the series connection of switching elements. However, the 

multilevel converter is complex to form the output voltage and requires too many 

back-connection diodes or flying capacitors (Han et al., 2006). 

For higher power applications, power-electronic devices are usually 

connected to the medium-voltage (MV) grid and the use of two-level voltage 

18


converters becomes difficult to justify owing to the high voltages that the switches 

must block (Roncero-Sánchez et al., 2009). 

One solution is to use multilevel voltage-source converters which allow high 

power-handling capability with lower harmonic distortion and lower switching 

power losses than the two-level converter (Roncero-Sánchez et al., 2009). 

Among the different topologies of multilevel converters, the most popular 

are: neutral-point-clamped converters (NPC), flying-capacitor converters (FC), and 

cascaded-multimodular H-bridge converters. NPC converters require clamping 

diodes and are prone to voltage imbalances in their dc capacitors. The H-bridge 

converter limitations are the large number of individual inverters and the number of 

isolated dc voltage sources required. The main drawback of FC converters is that the 

number of capacitors increases with the number of levels in the output voltage. 

However, they offer more flexibility in the choice of switching combinations, 

allowing more control of the voltage balance in the dc capacitors. Furthermore, the 

extension of a converter to a higher level one, beyond three levels, is easier in FC 

converters than in NPC converters, which makes the FC topology more attractive 

(Roncero-Sánchez et al., 2009). 

3.2.2.2. Rectifier 

AC to DC converter is used to convert AC into DC form. The topology used 

in dynamic voltage restorer is diode rectifier. Installation of a diode-bridge rectifier 

circuitry to the DVR provides an economical means for the dc-link to negotiate 

active power. Unfortunately, this DVR configuration only allows unidirectional 

power flow from the diode-bridge rectifier circuitry to the inverter. When swell or 

overvoltage occurs in the power distribution lines, the conventional in-phase and 

phase-invariant voltage injection schemes cause inverters to absorb active power 

from the lines, which charges up the dc storage capacitors and increases their voltage 

levels. Excess dc-link voltage rise will damage the dc storage capacitors and 

switching devices. Moreover, the rise in dc-link voltage will nonlinearly increase 

switching loss and lowers the DVR’s system efficiency (Lam et al., 2008). 

19


Figure 3.4. DVR with no energy storage and supply-side-connected rectifier 

Figure 3.5. DVR with no energy storage and load-side-connected rectifier 

The following significant difference exists in operation between rectifiers in 

Figs. 3.4 and 3.5 during the occurrence of voltage sags. In Figure 3.4, a voltage drop 

appears at the source side or at the ac terminals of the rectifier. As a result, the 

rectifier losses its rectification capability when the maximal source voltage gets 

lower than the dc-link voltage. Therefore, the series converter requires a large dc 

capacitor as an energy-storage element intended for feeding electric dc power to the 

series converter (Jimichi et al., 2008). 

On the other hand, no voltage drop appears at the load side or at the ac 

terminals of the rectifier in Figure 3.5, because the series converter compensates for 

voltage sags. This makes it possible to keep the rectifier active in regulating the dclink 

voltage, even for the duration of voltage sags. In this case, the electric power 

required for voltage-sag compensation comes from the rectifier to the series 

converter. In other words, the dc capacitor does not play any role in feeding the 

electric power required for compensation to the series converter. Thus, the DVR in 

20


phase itself further worsens the severity of the sag. Additionally, these schemes 

cannot provide phase correction, as sags are generally accompanied by phase jumps 

(Subramanian et al., 2010). 

3.2.3. Energy Storage 

Energy storage is required to provide real power to the load when large 

voltage sags take place. Examples of energy storage are lead-acid batteries, flywheel, 

superconducting magnetic energy storage (SMES), etc. For SMES, batteries and 

capacitors, which are dc devices, solid-state inverters are used in the power 

conversion system to accept and deliver power. For flywheels, which have rotating 

components, ac-to-ac conversion is performed. The energy storage devices used for 

this study are lead-acid batteries. Batteries provide rapid response for either charge or 

discharge, but the discharge rate is limited by chemical reaction rates so that the 

available energy depends on the discharge rate. Generally, the DVR has several 

operating states (Zhan et al., 2001). 

1) When a voltage sag/swell occurs on the line, the DVR responds by 

injecting three single-phase voltages in synchronism with the network voltages. Each 

phase of the injected voltages can be controlled independently or together in 

magnitude and phase. The DVR draws active power from batteries and supplies this 

together with reactive power to the load (Zhan et al., 2001). 

2) When the voltage supply is operating under normal conditions, the DVR 

operates in a standby mode if the battery is fully charged; or the DVR operates in the 

self-charging control mode if the batteries need to be recharged (Zhan et al., 2001). 

3) In the event of a fault or short circuit downstream, the DVR (specifically, 

the VSI) must be protected against overcurrent flowing through the power 

semiconductor switches. The rating of the DVR inverters is the limiting factor for 

normal load current seen in the primary windings and reflected in the secondary 

windings of the series insertion transformer. For line currents exceeding the inverter 

rating, a bypass scheme is incorporated to protect the power electronics (Zhan et al., 

2001). 

23


3.2.4. Injection Transformer 

The main purpose of the injection transformer is to boost the voltage supplied 

by the filtered VSC output to the desired level while isolating the Series 

Compensator circuit from the distribution network (Perera et al., 2006). The 

injection transformers not only reduce the voltage requirement of the inverters, 

but also provide isolation (Ghosh et al., 2002). In addition, the injection 

transformer is a special purpose transformer that has the ability to limit the 

coupling of noise and transient energy from the primary side to the secondary 

side (Zhan et al., 2001). 

The MVA rating is determined by using power calculation equation by 

(3.1) and (3.2). VDVR 

is the primary voltage of the injection transformer and V 

DVR, max 

is the voltage rating of injection transformer. 

DVR = V 

VA, rating dvrIload 

(3.1) 

V 

DVR 

VA, 

rating 

dvr, max 

= (3.2) 

Iload 

By using (3.1) and (3.2), the depth of voltage sag which can be compensated 

is calculated in (3.3) 

V 

V 

dvr,max 

sag, pu 

= 0 ≤ 

sag, pu 

≤ 1 

Vsource 

V (3.3) 

During a voltage sag compensation, the load voltage is maintained at 1 p.u. 

The maximum DVR injected voltage (defined by the DVR VA rating) is 

V 

DVRVA, 

rating 0.4 

= = 0. pu 

(3.4) 

I 0.1 

DVR, max 

= 4 

load 

24


This is more than the DVR voltage rating (0.5p.u.), therefore the device is 

voltage limited i.e. V DVR , max 

= 0. 5pu 

. The lower limit of the retained supply=0.9p.u.– 

0.4p.u.=0.5 p.u. (Ramachandaramurthy et al., 2004). 

The equivalent circuit of the conventional DVR shown in Figure 3.1 is 

illustrated using Figure 3.8. From Figure 3.1, it is quite clear that the voltage on the 

load side of the DVR is given by 

V = V + V 

(3.5) 

L 

S 

DVR 

i 

f 

s s p p 

inv 

f 

filter 

M 

DVR 

S 

Load 

(a) 

L 

filter 

transformer 

n 2 R i 

n V inv 

n 2 L f 

n 2 Rs n 2 Ls Rp 

Lp 

n 2 C 

ZM 

f 

n V filter 

V DVR 

V S 

Load 

(b) 

V L 

25


Load 

Figure 3.8. (a), (b) and (c) Equivalent circuit of system shown in Figure 3.1 

(c) 

By using equivalent circuit, the injected voltage 

can be written as 

V 

DVR 

Z 

= M 

nV 

filter 

Req 

+ jωL 

(3.6) 

eq 

The relationship between and can be expressed as 

V 

filter 

Z 

1 

jωC 

= C 

f 

= 

Vinv 

= 

ZC 

+ Ri 

+ Z 1 

L + Ri 

+ jωL 

2 

f 

jωC 

f 

V 

inv 

( 1− 

ω L 

f 

C 

f 

) + jRiωC 

f 

(3.7) 

By using (3.6) and (3.7), can be rearranged in (3.8) and (3.9) 

V 

Z 

V 

ω + 

= M 

DVR 

n 

Req 

+ j L 

2 

eq 

inv 

( 1− 

ω L 

f 

C 

f 

) jωRiC 

f 

Z 

M 

V 

( R + jω L )( [ 1− 

ω L C ) + jωR C ] inv 

= n 

2 

eq eq 

f 

f 

i 

f 

(3.8) 

V 

DVR 

= NV inv 

(3.9) 

26


In (3.10), actual voltage ratio between and can be explained 

N 

Z 

= n 

2 

eq eq 

M 

( R + jω L )( [ 1− 

ω L C ) + jωR C ] 

f 

f 

i 

f 

(3.10) 

When the source voltage varies, is maintained by the injection voltage 

from the DVR. As effective DVR voltage sag periods, the load current I 

L 

will 

be maintained constant. Considering that the magnetization impedance 

Z 

M 

of the 

series transformer is much larger than the transformer is much larger than the 

transformer series resistance and leakage reactance, it can be concluded that the 

voltage drop 

∆Vp 

caused by the transformer is ∆ V p 

= ( R eq 

+ jωL 

eq 

) I L 

, where 

R 

eq 

2 

2 

= Rp 

+ n Rs 

, Leq 

Lp 

+ n Ls 

= . The magnitude of the voltage drop is 

( R eq 

+ jωL 

eq 

) I L 

∆ V p 

= 

. Clearly, ∆Vp 

will contribute toward a reduction in the load 

voltage. Also the associated active power loss due to the transformer 

I 2 

eq L 

R exists at 

all time. Hence to reduce the voltage drop and power loss due to the transformer it is 

desirable that its short-circuit impedance 

means a more costly transformer (Li et al., 2002). 

R 

eq 

+ jωL 

is kept as low as possible. This 

eq 

3.2.5. Filter 

The semiconductor switching devices are used in wide variety of industrial 

loads. The non-linear characteristics of semiconductor devices cause distorted 

waveforms associated with harmonics. To overcome this problem and providing 

clean electrical supply filter unit is used (Choi et al., 2002; Li et al., 2001). The 

purpose of any of the filtering schemes is for the attenuation of the high-order 

harmonics due to the inverter switching (Choi et al, 2000). Two filtering methods are 

presented in literature: line side and inverter side. 

27


V 

V 

load 

inv 

2 

= 1/ L 

f 

C 

f 

ω f 

= 

2 

2 

s + sR / L + 1/ L C s + 2ξ 

ω s + ω 

(3.11) 

f 

f 

f 

f 

f 

f 

2 

f 

Figure 3.10. Inverter-side filter in DVR 

From (3.11), and can be written in (3.12): 

ξ 

f 

= 

R 

C 

f f 

2 L 

f 

, 

1 

ω 

f 

= 

(3.12) 

C L 

f 

f 

The resistance 

R 

f 

is a sum of the series resistance of the filter inductor 

and the equivalent resistance of the inverter switches. For a given filter cutoff 

frequencyω , infinite combinations of the filter inductance and the filter capacitance 

f 

L 

f 

are possible. When the proportion of 

C / L is designed large, the filter damping 

f 

f 

coefficient 

ξ 

f 

can be increased, and the disturbance rejection against the load 

current may be also increased. However, the inverter current may contain high 

ripples which results in larger inverter size. Therefore, the proportion of C / L has 

certain limitation (Kim et al., 2004). 

Figure 3.10 shows the single line equivalent circuit of inverter side LC filter 

in DVR. V 

inv 

and V 

load 

represents the voltage on the output of inverter and load. Z 

L 

f 

f 

is equivalent impedance in section of load and its equivalent value is 

R + jωL 

. 

L 

L 

29


The basic principle behind the design of the filter is to provide a shunt path 

for the harmonic current and a series impedance to carry the harmonic voltages. To 

achieve this goal, the capacitor should be chosen to satisfy (Choi, et al., 2002): 

Z = K Z , K >> 1 

(3.13) 

Load ( m) 

f Cf ( m) 

f 

Where Z − j ( m C) 

( 

>> / ω andω 0 

= 2πf 

0, 

f0 

, represents the fundamental 

cf m) 

0 

frequency, and 

is the order of the lowest harmonics to be attenuated. From Figure 

3.10, let V 

inv(n) 

and V 

L(n) 

represent the respective nth order harmonic voltages on the 

inverter and load-side of the L-C filter and n=m,m+1,m+2,m+,,,,,M. M is the order of 

the highest harmonics to be attenuated. By using (3.13), we can obtain the following 

relationship: 

V = K V 

(3.14) 

load ( n) 

( n) 

inv( 

n) 

2 

Where = 1/ ( n ) LC 1) 

K n 

ω . Thus, 

( ) 

0 

− 

1 

1+ 

K( 

n) 

L = (3.15) 

2 

( nω 

) C 

0 

From (3.13), it is obvious that for a given 

Z 

load 

, C is directly proportional to 

K 

f 

. Thus, a suitable value for C can be obtained by the selection of an appropriate 

value for K . Furthermore, (3.14) means that, in order to reduce the nth order 

f 

harmonic voltage with rms value from V 

inv(n) 

to V 

load (n) 

, the inductor of the filter can 

be chosen according to (3.15) once the capacitor value C is given and K 

(n) 

is chosen 

according to (3.14). Indeed, it will be shown in the next section that the voltage 

30


harmonic distortions on the load-side of the DVR can be reduced to a permissible 

level with a properly selected value of K 

(n) 

, where n=m(Choi, et al., 2002). 

3.3. Control of DVR 

The main purpose of the control system is to maintain a constant voltage 

magnitude at the side where a sensitive load is connected, under sag/swell 

conditions. The control strategy is a fairly critical issue in DVR. All control 

strategies consist of five stages which are called as sag/swell detection, operation 

mode, voltage injection strategy, reference voltage generation and gate signal 

generation. 

3.3.1. Sag/swell detection 

In control strategy, for the calculation of reference signals to achieve voltage 

sag/swell compensation, instantaneous voltage signals need to be measured. 

Instrumentation transformers and Hall-effect sensors are used to measure the voltage 

signals in system. Then, these measured signals are used to generate the reference 

signals for sag/swell compensation. 

3.3.2. Operation Mode 

The phase angle and amplitude of the injected voltage are variable 

during sag. This will allow the control of active and reactive power exchange 

between the DVR and the distribution system. Generally , the operation of the 

DVR can be categorized into three operation mode: protection mode, standby 

mode (during steady state) and injection mode (during sag) (Teke, 2005). 

31


3.3.2.1. Protection Mode 

If the current on the load side exceeds a permissible limit due to a short 

circuit on the load or large inrush current, the DVR will be isolated from the systems 

by using the bypass switches as shown in Figure 3.11, S2 and S3 will open and S1 

will be closed to provide an alternative path for the load current (Shazly et al., 2013). 

Figure 3.11. Scheme of the protection mode 

3.3.2.2. Standby Mode 

In the standby mode, the injection transformer’s secondary winding is shorted 

through the converter. The structure of standby mode is shown in Figure 3.12. This 

mode is preferred in steady-state conditions due to the voltage drops born of 

transformer reactance. 

Figure 3.12. Scheme of the standby mode 

32


If the distribution circuit is weak there is need to inject small compensation 

voltage to operate correctly. During short circuit operation, the injected voltages and 

magnetic fluxes are virtually zero thereby full load current pass through the primary. 

The DVR will be most of the time in normal mode operation. During standby mode 

normal operation), the short circuit impedance of the injection transformer 

determines the voltage drop across the DVR (Teke, 2005). 

3.3.2.3. Injection Mode 

The primary function of Dynamic Voltage Restorer is compensating voltage 

disturbances on distribution system. To achieve compensation, three single-phase ac 

voltages are injected in series with required magnitude, phase and wave shape. The 

types of voltage sags, load conditions and power rating of DVR will determine the 

possibility of compensating voltage sag (Teke, 2005). 

3.3.3. Voltage Injection Strategies 

The way in which the dynamic voltage restorer (DVR) is used during the 

voltage injection mode depends upon several limiting factors such as: DVR power 

rating, load conditions, and voltage-sag type. For example, some loads are sensitive 

to phase-angel jumps, some others are sensitive to a change in voltage magnitude and 

some others are tolerant to all these disturbances. Therefore the control strategies to 

be applied depend upon the load characteristics (Shazly et al., 2013). There are four 

different methods of DVR voltage injection strategies: 

• Pre-sag compensation 

• In-phase compensation 

• In-phase advanced compensation 

33


3.3.3.1. Pre-sag compensation 

The pre-sag compensation method tracks supply voltage continuously load 

voltage during a fault to restore the pre-fault condition. Figure 3.13 shows the singlephase 

vector diagram of the pre-sag compensation. In this method, the load voltage 

can be restored ideally, but injected active power cannot be controlled and is 

determined by external conditions such as the type of faults and load condition (Quirl 

et al., 2006). 

Figure 3.13. Vector diagram of pre-sag compensation 

3.3.3.2. In-phase compensation 

As already mentioned, the pre-sag compensation does not lead to a minimized 

voltage amplitude. This can be realized with the in-phase strategy, which is designed 

to control the DVR with a minimum output voltage. In Figure 3.14, the voltages for 

this strategy are depicted. In contrast to the pre-sag version, the voltage is now 

compensated in phase to the grid voltage after the sag. Hence, the required voltage 

amplitude is minimized, but the phase jump is not compensated (Meyer et al., 2008). 

34


Figure 3.14. Vector diagram of in-phase compensation 

In most cases, a voltage sag leads to a phase jump, therefore the distortions 

due to phase changes are not minimized. As a consequence, a phase jump will be 

applied to at the load, leading to transients and circulating currents. Thus, if a 

sensitive load must be secured, the in-phase compensation cannot be used, be-cause 

it could lead to the tripping of sensitive loads. Note that, to realize this strategy, the 

PLL has to be synchronized to the grid voltage itself, and therefore, must not be 

locked to the pre-sag grid voltage during the compensation (Meyer et al., 2008). 

3.3.3.3. Phase advance compensation 

In this method the real power spent by DVR is minimized by decreasing the 

power angle between the sag voltage and the load current. In the two previous cases, 

namely pre -sag and in-phase compensation, active power is injected into the system 

by the DVR during disturbances. Moreover, the active power supplied is limited to 

the stored energy in the DC link and this part is one of the most expensive parts of 

the DVR. The minimization of injected energy is achieved by making the injection 

voltage phasor perpendicular to the load current phasor (Shazly et al., 2013). 

35


Figure 3.15. Phasor diagram of the phase advance compensation method 

In this method the values of load current and voltage are fixed in the system 

so one can change only the phase of the sag voltage. In short, PAC method uses only 

reactive power and unfortunately, not all the sags can be mitigated without real 

power, as a consequence, this method is only suitable for a limited sag range (Shazly 

et al., 2013). 

3.3.4. Reference Voltage Generation 

Reference signals are generated using time domain and frequency domain 

methods in literature. Frequency domain methods use Fourier Transform (FT) to 

generate reference signals. Even though it enables selective harmonic elimination 

and provides to generate reference signals rapidly, it has main drawbacks such as 

requirement at least one cycle to estimate the reference current and control 

complexity compared to control methods in time domain. Synchronous Reference 

Frame (SRF) and P-q-r (IRPT) are the most common and popular control techniques 

to determine the reference signals based on time-domain. RMS (Average) Magnitude 

Detector, Recursive Weighted Least Square Method, Modified Delta Rule Method, 

Kalman Filter, EPLL are another methods to generate reference voltages in dynamic 

voltage restorer. Besides, SOGIPLL is performed and analyzed to extract reference 

36


signal firstly. In this thesis, EPLL, SRF and SOGI-PLL methods which are 

comprehensively expressed in Chapter 4 are used to generate reference values. 

3.3.5. Voltage Control Methods 

The accuracy and dynamic behavior of the pulse width modulation and 

voltage drop due to switching devices and passive components in DVR directly 

affects the injected voltage generated by DVR. In available literature, there are two 

voltage control systems used in the DVR applications: open loop and closed loop. 

3.3.5.1. Open Loop 

Usually, the control voltage of the DVR is derived by comparing the 

incoming supply voltage against a desired reference voltage. Although system 

stability is guaranteed in this type of control, damping is poor, and the stability 

margin may not be sufficient in the presence of inverter-side filter (Vilathgamuwa et 

al., 2006). In this method, the control signal , is simply compared supply voltage 

against a reference voltage. 

Figure 3.16. Open Loop Control Method 

V 

i 

i 

( V −V 

) 

= k 

(3.16) 

ref 

s 

In this control system, the voltage at source side of the DVR is compared with 

the voltage at load-side reference voltage. Error between source-side and load-side 

voltages is used to compare with a triangle signal in PWM module. 

37


For a practical DVR system, it can be shown that the nondominant real root 

3 2 

(pole) of the system characteristics equation a1 os 

+ a2os 

+ a3 

os 

+ a4o 

is 

2 

2 

approximately located at − ( r + n r )/( L + n L ) 

equation can be factorized as (Vilathgamuwa et al., 2006). 

l 

t 

L 

t 

. Therefore the characteristics 

a 

2 

2 2 

( L + n L ) s + ( r + n r ) ( s + b s ) 

3 2 

1 o 

s a2os 

+ a3os 

+ a4o 

≈ b10 

l t l t 

} 

20 

+ 

+ { b (3.20) 

30 

and by equating the coefficients on both sides, the coefficients b 

10 

, b20, 

b30 

, , 

and b40 

can be determined. They are given in the Appendix (Vilathgamuwa et al., 

2006). 

The expressions for b 

10 

, b20, 

b30 

reveal that the locations of the remaining two 

complex and dominant poles depend on the filter, load, and the series transformer 

parameters. Indeed further analysis will show that the real part of the poles is equal 

to 

− r / 2L 

f 

f 

. As a safeguard against voltage sag, the DVR is expected to be on-line 

at all time so that there is minimal delay in providing the voltage support as and 

when it is needed. Hence it is desirable that the restorer has low loss and thus the 

filter resistance r(f) is kept to as low a value as practicable. This could mean that the 

dominant complex poles are located very close to the imaginary axis. Therefore the 

transient response of the distribution system following a sag behaves very much like 

a second-order system with natural damping frequency of ω 

n0 

given by 

(Vilathgamuwa et al., 2006). 

r + n r + n r 1 

ω (3.21) 

2 2 

l t f 

n0 = 

≈ 

2 

( rl 

+ n rt 

) L 

f 

C 

f 

L 

f 

C 

f 

As 

r 

l 

2 

2 

>> n rt 

and rl 

n rf 

>> . 

39


V 

i 

i 

[ k ( V −V 

) + k k ( V −V 

) − i ] 

= k 

{ } 

(3.22) 

f 

ref 

s 

c 

v 

ref 

l 

c 

The load side voltage for this control configuration is given by (3.23) 

Vload 

Gclose 

1 

Vref 

+ Gclose2 

= V 

(3.23) 

s 

Where G 

close1 

is the closed-loop transfer function from the reference signal 

V 

ref 

to V 

load 

while G 

close2 

is the closed-loop transfer function from the supply voltage 

V 

s 

to V 

load 

. These transfer functions (3.24) and (3.25) (Vilathgamuwa et al., 2002) : 

G 

( nk k k + nk )( L s + r ) 

i c v i l l 

close1 ( s) 

= (3.24) 

3 

2 

a1 

ncvs 

+ a2ncvs 

+ a3ncvs 

+ a4ncv 

G 

close 2 

( s) 

LL C s + 

2 

( L r + Lr + kk L ) C s + ( r rC + (1− 

nk) 

L + kk rC ) s+ 

( 1−nk) 

3 

l f f f l l f i c l f f l f i l i c l f 

i l 

= (3.25) 

3 2 

a1 

ncvs 

+ a2 

ncvs 

+ a3 

ncvs 

+ a4 

ncv 

r 

Following a similar analysis as in open loop control method, it can be seen 

the real root of the characteristics equation can be approximately located at 

− 

2 

2 

( r + n r )/( L + n L ) 

l 

t 

L 


t 

. Factorization of the characteristics equation yields 

2 

2 2 

( L + n L ) s + ( r + n r ) ( s + b s bncv) 

3 2 

a1 ncv 

s + a2ncvs 

+ a3 

ncvs 

+ a4ncv 

≈ b1 

ncv{ l t l t 

} 

2ncv 

+ (3.26) 

Where 

b b ncv 2ncv 

1 

, and b 3 ncv 

are given in the Appendix. 

The expressions for the coefficients 

b b ncv 2ncv 

1 

, and b 3 ncv 

show that the two 

dominant complex poles depend largely on the values of the filter inductance, filter 

resistance as well as the capacitor current loop gain k 

c 

. Furthermore it can be shown 

that the real part of these poles is − ( rf 

+ kikc 

)/ 

2L 

f 

. This is a very useful feature 

41


because there is now an additional flexibility in the design introduced by the factor 

k 

c 

. For a given 

k 

i 

, the value of 

k 

c 

can be chosen such that 

k k >> r and a 

corresponding increase in the real part of the complex poles is obtained. Thus the 

damping level can be increased with an increase of the capacitor current gain 


The resulting system can be seen to have the natural damping frequency ω 

nncv 

i 

c 

f 

r + n r + n r + nk k k r 

1 

2 2 

l t f i c v l 1+ 

nk k k 

ω 

nncv 

= 

≈ 

== 1+ 

nk k k . (3.27) 

i c v 

2 

i c v 

( rl 

+ n rt 

) Lf 

C 

f 

Lf 

C 

f 

Lf 

C 

f 

The natural damping frequency of the closed loop system is therefore 

approximately 

1 + nk k k times filter resonance frequency(Vilathgamuwa et al., 

i 

c 

v 

2002). 

System damping and stability margin can be improved by properly selecting 

the gains k 

c 

and k 

v 

. These gains are determined for a given design specification by 

deriving transfer function between load and the reference voltage. Further analysis 

reveals that the increase of current gain 

tends to increase the damping level while 

the increase of voltage gain k 

v 

, tends to decrease it. As the feed forward gain 

presents only in the numerator of the transfer function it does not contribute to 

improve system damping and stability margin. However it can be independently 

adjusted to decrease steady state error of compensated load voltage. However it can 

be independently adjusted to decrease steady state error of compensated load voltage 


k 

f 

, 

3.3.6. Gate Signal Generation 

Gate signals are used to control of the electrical switches in inverter. The rms 

value of output voltage in inverter is controlled by turning the solid-state devices. 

42


There are several techniques to generate firing signals for solid-state devices in 

inverter. These techniques play important role in effective performance of dynamic 

voltage restorer. Pulse Width Modulation and Space Vector Modulation are the most 

common techniques which are used to generate gate signals. 

43


44

4. MODELING OF PROPOSED DVR Mustafa İNCİ 

Table 4.1. Grid and load parameters of proposed system 

Grid Parameters 

Source 

Frequency 

Load Parameters 

Type 

Power rating 

Voltage rating 

Value 

11 kV three phase 

50 Hz 

Value 

Nonlinear six pulse rectifier 

1 MVA 

8 kV (dc) 

Figure 4.2. 

The circuit structure of six pulse rectifier used in proposed DVR is shown in 

Figure 4.2. Three-phase uncontrolled six pulse rectifier 

4.2. Power Circuit Design of DVR Components 

The power circuit of the proposed Dynamic Voltage Restorer (DVR) 

topology in a three phase system is shown in Figure 4.4. It connected between 

three phase sources and nonlinear load. As seen from the Figure 4.2, there are three 

main elements, which are considered in the design of a DVR. 

46


• Inverter Circuit 

• Output Filter 

• DC-DC Converter 

4.2.1. Design of Inverter Circuit 

The inverter circuit is used to inject controlled voltage and maintain the 

desired output voltage. The injected voltage is generated by accurately controlling 

the switches in the inverter. The most common inverter topologies are the two- or 

three-level three-phase converter used in DVR. Another popular converter topology 

is the H-bridge cascade inverter. For higher power applications, the use of two-level 

voltage converters becomes difficult to perform because of switch ratings and 

efficiencies. One solution is to use multilevel voltage-source converters which allow 

high power-handling capability than the two level and H-bridge inverters. 

Figure 4.3. Single phase symmetrical five level diode clamped inverter 

47


Among the different topologies of multilevel converters, the most popular 

are: diode clamped inverters, flying-capacitor inverters, and cascade H-bridge 

inverters(Patil et al., 2012). An m-level diode-clamped multilevel inverter typically 

consists of m-1 capacitors on the dc bus and produces m levels of the phase 

voltage(Ozdemir et al., 2007). Figure 4.3 presents a single-phase diode-clamped 

inverter with two three-level legs. In this case, the dc-link is composed of two 

capacitors. For proper modulation and to avoid excessive voltage on switches, the 

voltage on the dc-link capacitors should be the same(Stala,2011). 

V 

p 

= V N 

(4.1) 

Proposed topology consists of two capacitors on dc bus and generates fivevoltage 

levels of phase voltage in inverter. Inverter structure consists of three single 

phase five level diode clamped inverter for each phases. In this wise, it can 

compensate balanced and unbalanced voltage sag/swell. Also, each diode clamped 

inverter generates five voltage level (-Vdc, -0.5Vdc, 0, 0.5Vdc,Vdc). The voltage 

levels and their corresponding switch states of inverter for each five level diode 

clamped inverter are shown in Table 4.2. State condition 1 means the switch is ON, 

and state 0 means the switch is off. 

48


Table 4.2. Switch states of five level diode clamped inverter 

State G1 G2 G3 G4 Vout 

1 0 0 0 0 0 

2 0 0 0 1 -0.5 

3 0 0 1 0 0 

4 0 0 1 1 -1 

5 0 1 0 0 0.5 

6 0 1 0 1 0 

7 0 1 1 0 0 

8 0 1 1 1 -0.5 

9 1 0 0 0 0 

10 1 0 0 1 0 

11 1 0 1 0 0 

12 1 0 1 1 0 

13 1 1 0 0 1 

14 1 1 0 1 0.5 

15 1 1 1 0 0 

16 1 1 1 1 0 

Node “0” indicates grounding, “P” indicates positive terminal and “N” is the 

negative terminal in inverter. Switches ( G , G , G G ) 

1 2 3, 

4 

are the main devices operating 

, , , 

as modulating switche for the PWM. Switches ( , G , G G ) 

, 

complementary switches of ( , G , G G ) 

1 2 3, 

4 

G are the 

1 2 3 

, 

G as shown in Figure 4.3. 

DC link capacitor voltage is calculated as in (4.2): 

4 

2 

= sdepth 

(4.2) 

n 3 

V 

dc,min 

Vl−l 

, rms 

49


In proposed system, and is determined to compensate voltage sag 

of 35% in (4.3): 

2 

V dc , min 

= 11kV 

× 0.4 ≅ 1. 572kV 

(4.3) 

2 3 

DC capacitor voltage V 

DC 

is determined as 1700 V; equivalent DC capacitor 

value is calculated as 25 mF. 

4.2.2. Design of Inverter Filter 

There are several types of filters. The simplest variant is filter inductor 

connected to the inverter's output. But also combinations with capacitors like LC or 

LCL can be used. The LC type inverter-side filter is used in this study and the 

equivalent circuit is depicted in Figure 4.4. It is second order filter and it has better 

damping behaviuor than L-filter. This simple configuration is easy to design and it 

works mostly without problems. The second order filter provides 12 dB per octave of 

attenuation after the cut-off frequency f 0 

, it has no gain before f 0 

, but it presents a 

peaking at the resonant frequency f 0 

(Lettl et al., 2011, Köroğlu, 2012). 

Figure 4.4. Equivalent Circuit for Inverter Side Filter 

50


In this equivalent circuit, 

L 

f 

and 

C 

f 

constitute the single section LC filter; 

R 

f 

is used to damp the filter at the resonant frequency f 0 

. V 

inv 

represents the output 

voltage of the PWM inverter, i is the input current, a 

i 

c 

is the capacitor current, i o 

and V 

o 

are the output current and the output voltage of inverter side filter. Transfer 

function of the LC filter is expressed as (Köroğlu, 2012); 

V 

1 

L 

f 

s + R 

f 

s) 

= V ( ) 

I ( s) 

2 inv 

s − 

o 

(4.4) 

L C s + R C s + 1 L C s + R C s + 1 

o 

( 

2 

f f f f 

f f 

f 

f 

Figure 4.5 shows the block diagram of single phase PWM inverter side filter 

according to the transfer function (Kim et al., 2000, Köroğlu, 2012). 

1 

L s + 

f 

R f 

1 

C f 

s 

Figure 4.5. Block Diagram of Single Phase PWM-VSI. 

In the conventional output filter design method, the output current i is 0 

treated as the disturbance and so it is neglected and the new transfer characteristic 

can be rewritten as (Kim et al., 2000, Köroğlu, 2012); 

Vo 

( s) 

H ( s) 

= = 

2 

V ( s) 

L C s 

inv 

f 

f 

1 

+ R C 

f 

f 

s + 1 

(4.5) 

While choosing the filtering system, the cut-off frequency f 

0 

of the filter 

should be minimally 10 times greater then grid frequency and simultaneously 

maximally one half of the converter switching frequency. The decrease of the power 

51


factor caused by the filter capacitance should be lower than 5% (Lettl et al., 2011, 

Köroğlu et, 2012). 

Cut off frequency f 

0 

should be between 500 Hz and 1500 Hz where grid 

frequency is 50 Hz and PWM inverter switching frequency is 3000 Hz (Köroğlu, 

2012). 

f 

o 

1 

= (4.6) 

2π L C 

f 

f 

In order to achieve the proper 

L 

f 

and 

C 

f 

values, this time below equations 

should be satisfied (Acar, 2002; Choi et al., 2002). 

K 

V 

THD P 

V 

T 

= (4.7) 

K 

i 

M 

∑ 

n= 

m 

M ⎛ 

2 

V inv n 

⎞ 

2 

( ) 

V ⎜ 

⎟ 

o( 

n) 

= ∑ 

< V 

2 

n m nwo L 

f 

C 

= ⎝ ( ) 

f 

−1⎠ 

2 

T 

(4.8) 

V 

inv 

4VDC 

( n) 

= (4.9) 

2 nπ 

In Equation 4.7, V 

T 

is the rms value of total harmonics voltage (per phase) on 

the high voltage-side of the injection transformer, K 

THD 

is the voltage THD for a 11 

kV system which can not be greater than 5.0%, K 

i 

is the turns ratio of the injection 

transformer, V 

p 

is the voltage on the high voltage side of the injection transformer. 

In Equation 4.6, V 

o( n) 

and V 

inv (n) 

are the n th order harmonic voltages on the 

output and input of inverter where n is the order of harmonics (n = m, m+1, m+2,...., 

M). V 

inv (n) 

can be obtained form Equation 4.6, in which VDC 

is the DC link voltage. 

52


L , C and 

f 

f 

R 

f 

values are determined according to above equations and 

using these values in the transfer characteristic obtained in Equation 4.6, bode plot is 

drawn. A Bode plot is a plot of the magnitude and phase of a transfer function or 

other complex valued quantity, vs. frequency. The magnitude plot is effectively a 

log-log plot, since the magnitude is expressed in decibels and the frequency axis is 

logarithmic (Erickson et al., 2000, Köroğlu, 2012). Bode plot for 

( L f 

= 1.25 

mH , C = 80 µ F and R = 0.04 Ω ) is shown in Figure 4.6. 

f 

f 

Figure 4.6. The Frequency Response of the Inverter Side Connected Filter 

Decibel values of some simple magnitudes are listed in Table 4.3. The 

magnitude of a dimensionless quantity G can be expressed in decibels as follows 

(Erickson et al., 2000): 

G dB 

= 20 log10 ( G ) 

(4.10) 

53


Table 4.3. Expressing Magnitudes in Decibels 

Actual Magnitude Magnitude in dB 

0.01 -40 

0.1 -20 

1 0 

2 6 

10 20 

100 40 

Figure 4.7 shows the phase plot of the inverter side filter, the phase tends to 

0 o at low frequency and tends to -180 o at high frequency, at cut off frequency f = f 

o 

, 

the phase is -90 o . 

Figure 4.7. Phase Plot of the Inverter Side Connected Filter 

54


4.2.3. Design of DC-DC Converter 

This topics presents the controller design procedures of the full bridge 

isolated dc/dc converter used in proposed DVR. Figure 4.8 shows the structure of 

proposed dc-dc converter. 

Figure 4.8. Circuit diagram of full bridge DC–DC Converter 

The main function of the dc-to-dc converter is to maintain and control the dc 

voltage of the inverter during voltage sag. Proposed DC-DC converter allows the 

DVR to compensate deep and long duration voltage sags(Jowder et al., 2009). 

Timing diagram with basic operating waveforms are presented in Figure 4.9. 

Gate signals (S1, S2, S3 and S4) are generated with comparison of reference signal 

with carrier. 

Primary switches, S1-S4, are hard switched and operated in pairs, S1-S2 and 

S3-S4 respectively. Drive signals are 180 degree phase shifted. Switch transistor duty 

cycle, D, is below 50 percent to avoid switch overlap and thus short circuit of input 

(Nymand et al., 2010). 

55


Figure 4.9. Timing diagram and basic waveforms for isolated full-bridge dc-dc 

converter 

2010). 

Basic converter operation can be divided into four main states(Nymand et al., 

State 1, First on-period, T1:A first converter on-period, T1, starts when switches, 

S1-S2, are turned on. Switches, S3-S4, and diodes, D3-D4, are off. Reflected 

inductor current flows from input capacitor, C1, through switch, S1, transformer, T1, 

diode, D1, and inductor, L1 to the output, and returns to input through diode, D2, and 

switch, S2. The period ends when switches, S1 and S2, are turned off again. Duration 

of the on-period is (Nymand et al., 2010): 

T = DT 

1 

(4.11) 

The plot for the secondary voltage Vs is shown on Figure 4.9, 

56


N 

= V nV 

(4.12) 

P 

V 

S 

in 

= 

N 

P 

in 

Where transformer turns ratio is defined as the ratio of secondary winding 

turn number to primary winding turn number. 

N 

N 

S 

n = (4.13) 

P 

The voltage across the output inductor L1 is given by 

V 

L 

N 

S 

= VS 

−VO 

= −VO 

(4.14) 

N 

P 

Assuming a constant output voltage Vo, the voltage across L1 is a constant, 

resulting in a linearly increasing current in L1. In the interval when S1, S2 or S3,S4 

is closed, the change in current in L1 is 

∆I 

L 

∆t 

∆I 

L 

= 

DT 

VL 

= 

L 

1 

= 

L 

1 1 1 

1 

1 

⎛ N 

⎜ 

⎝ N 

S 

P 

V 

in 

−V 

O 

⎞ 

⎟ 

⎠ 

(4.15) 

State 2, First off-period, T2: A first converter off-period, T2, starts when switches, 

S1 and S2, are turned off. All primary switches are off. Inductor current, iL1, is freewheeling 

through the two parallel branches, D1-D4 and D3-D2, to output. Inductor 

current is discharging. Transformer magnetizing current circulates in the transformer 

secondary winding and the diodes, D1-D3 and/or D2-D4. The period ends when 

switches, S3 and S4 are turned on (Nymand et al., 2010). 

⎛ 1 ⎞ 

T2 = ⎜ − D⎟T 

(4.15) 

⎝ 2 ⎠ 

57


The voltage across L1 is Vo, resulting in a linearly decreasing current in L1. 

The change in current while both switches are open is 

∆I 

∆t 

L1 

∆I 

L1 

V 

= = − 

T / 2 − DT L 

O 

1 

(4.17) 

State 3, Second on-period, T3: A second on-period similar to the first is initiated 

when switches, S3 and S4, are turned on. Reflected inductor current flows from input 

capacitor, C1, through switch, S3, transformer, T1, (in opposite direction compared 

to first on-period) diode, D3, and inductor, L1, to the output. Current returns to input 

through diode, D4, and switch, S4. The period ends when switches, S3 and S4, are 

turned off again. Period time is equal to the first on-period, (Nymand et al., 

2010). 

State 4, Second off-period, T4: Finally, a second off-period starts when switches, 

S3 and S4, are turned off. All primary switches are off. Inductor current, iL1, is freewheeling 

through the two parallel branches, D1-D4 and D3-D2, to output. Inductor 

current is discharging. Transformer magnetizing current circulates in the transformer 

secondary winding (in opposite direction to first off-period) and the diodes, D1-D3 

and/or D2-D4. The period ends when switches, S1 and S2, are turned on. Period time 

is equal to the first off-period time, T 

4 

= T 2 

. Duration of the off-period is (Nymand et 

al., 2010): 

Since the net change in inductor current over one period must be zero for 

steady-state operation, 

( ∆ ) + ( ∆I 

) 0 

I (4.18) 

L, closed L, 

open 

= 

1 

L 

1 

⎛ N 

S 

⎞ VO 

⎜ Vin 

−VO 

⎟DT 

+ ( T / 2 − DT ) = 0 

(4.19) 

⎝ N 

P ⎠ L1 

58


Solving for Vo, 

V 

O 

⎛ N 

S 

VS 

D 

N ⎟ ⎞ 

= 2 ⎜ 

(4.20) 

⎝ P ⎠ 

2011), 

It is also useful to express the ripple as a fraction of the output voltage(Hard, 

∆V 

V 

O 

O 

1− 

D 

= 

8LCf 

2 

(4.21) 

In design, it is useful to rearrange the preceding equation to express required 

capacitance in terms of specified voltage ripple(Hard, 2011): 

1− 

D 

C = (4.22) 

8L 

2 

( ∆V 

/ V ) f 

O 

O 

If the ripple is not large, the assumption of a constant output voltage is 

reason-able and the preceding analysis is essentially valid(Hard, 2011). 

Finally, the VA rating of the capacitor, denoted as , is (Li et al., 2001): 

S = k V I 

(4.23) 

C 

C 

C 

C 

Where 

1.2(Li et al., 2001). 

k 

C 

is an optional safety coefficient, typically ranging from 1.0 to 

4.3. Control System 

The control system of a DVR plays an important role, with the requirements 

of fast response and more accuracy. Many extraction and mitigation strategies is 

59


presented with different control algorithms and different topologies in dynamic 

voltage restorer. Voltage sag and swell must be detected fast and compensated 

accurately. SRF and EPLL are widely used for sag/swell detection and reference 

extraction. In addition to these controllers, SOGI-PLL is used to generate reference 

signals when sag/swell is detected. The DVR must inject the series voltage according 

to several criteria. In proposed system, it uses presage compensation method which 

prevent phase-jump problem and requires less power transfer compared to in-phase 

compensation method. Due to the lack of damping and poor dynamic performance in 

the open loop control, the closed-loop control is preferred in proposed method. 

4.3.1. Sag Detection 

Many sag detection methods are presented with different control algorithms 

in literature. Voltage sag and swell must be detected fast and compensated 

accurately. SRF and EPLL are widely used for sag/swell detection and reference 

extraction. In addition to these controllers, SOGI-PLL is a new method to generate 

reference signals when sag/swell is detected. This section is also to explain the 

structures of the EPLL, SRF, SogiPLL for three phase Dynamic Voltage Restorer for 

sag/swell compensation and consists of their comparison results. 

4.3.1.1. Enhanced Phase Locked Loop (EPLL) 

This section analysis Enhanced Phase-Locked Loop (EPLL) which is used to 

obtain signal magnitude and phase angle information in DVR systems. Conventional 

PLLs are used to extract phase angle of a signal. However, EPLL has a capability 

determination of amplitude and phase angle detection compared to conventional 

PLLs. 

The main building block of the system is an enhanced phase-locked loop 

(EPLL) which extracts the synchronised fundamental component of the input signal 

and its amplitude, phase angle and frequency(Karimi et al, 2005). When compared 

60


• The synchronized fundamental component, 

• The amplitude, A (t) 

, of y (t) 

• The phase angle θ (t) 

, of y (t) 

. 

• The frequency deviation, ∆ ω (t) 

; 

• Time-derivatives of the amplitude, phase and frequency. 

The error signal e(t)=u(t)-y(t) is the total distortion signal of the input and it 

can be expressed as a continuous time (Teke et al., 2011). 

∫ 

e ( t ) = u ( t ) − sinθ 

( t ) e ( t ).sinθ 

( t ). K . A 

dt 

(4.24) 

Here, and , located at the right hand side of (1), are assumed as a 

constant due to the value at the instant t that is equal to that of the instance (t-1). 

Hence, the final statement of (4.24) is given as 

∫ 

e ( t ) = u ( t ) − sinθ 

( t − 1) e ( t − 1).sinθ 

( t − 1). K . A 

dt 

(4.25) 

Considering that e(t-1) and sin(t-1) are constant, then 

∫ 

e ( t) 

= u ( t) 

− e ( t −1) 

sin 

2 θ ( t −1). 

K dt 

(4.26) 

A 

If the constants are assumed as 

sin θ ( t −1) 

= µ 

(4.27) 

1 

2 

( µ 

1 

) . K 

A 2 

e (4.28) 

2 

( t −1) 

sin 

θ ( t −1). 

K 

A 

= e ( t −1) 

= µ 

62


Then, the last statement of e(t) can be written as 

e t) 

= u ( t) 

− µ t 

(4.29) 

( 

2 

A (t) can be expressed as 

∫ 

A ( t ) = e ( t ) . s inθ 

( t ). K . A 

dt 

(4.30) 

In (5.30), 

is assumed as a constant due to the value at the instant t 

that is equal to that of the instance (t-1). Hence, the final statement of (4.32) is given 

in the following equations: 

A ( t ) = ∫ e ( t ) .sin θ ( t −1). 

K . A 

dt 

(4.31) 

Considering that sin θ ( t −1) 

= µ 

1 

and substituting e (t) 

into A (t) 

, A (t) 

can be 

rewritten as 

A ( t) 

= µ 

1. 

K 

A ∫[ u ( t) 

− µ 

2t]dt 

. 

(4.32) 

the input signal u ( t) 

= u.sin ( wt + α) 

and A (t) 

is organized as follows: 

A ( t) 

= µ 

1. 

K 

A ∫[ u sin(wt 

+ α) 

− µ 

2t]dt 

. 

(4.33) 

µ 

1. 

K 

A 

. u cos( wt + α) 

µ 

1µ 

2K 

A 2 

= − 

− 

(4.34) 

A ( t) 

t 

w 

2 

The speed of the response is determined by parameters K and 

. Rate of 

convergence is increased by increasing K and 

. Thus, these two parameters 

63


control transient as well as steady-state behavior of the filter. This feature of the 

filter, as it is shown in this paper, makes it suitable for a variety of 

applications(Karimi et al, 2002). 

4.3.1.2. Synchronous Reference Frame (SRF) 

This algorithm is based on obtaining the equivalent space vector of three 

phase quanitities(Meena et al, 2012).The three supply phases are converted into one 

phasor “ V S 

” which itself is comprised of two orthogonal components " Vα 

and V 

β 

" . 

A synchronous reference frame is locked to “ V S 

” via a PLL. The vectors are 

generated by the following formulas (4.35) and (4.36): 

⎡V 

⎢ 

V 

⎢ 

⎢⎣ 

V 

α 

β 

0 

⎤ 

⎥ 

= 

⎥ 

⎥⎦ 

⎡1 

2 ⎢ 

0 

3 ⎢ 

⎢⎣ 

0 

− 0.5 

0.866 

0 

− 0.5 ⎤⎡V 

− 0.866 

⎥⎢ 

V 

⎥⎢ 

0 ⎥⎦ 

⎢⎣ 

V 

a 

b 

c 

⎤ 

⎥ 

⎥ 

⎥⎦ 

(4.35) 

⎡V 

⎢ 

⎣V 

d 

q 

⎤ ⎡ cosϑ 

⎥ = ⎢ 

⎦ ⎣− 

sinϑ 

sinϑ 

⎤⎡V 

⎥⎢ 

cosϑ⎦⎣V 

α 

β 

⎤ 

⎥ 

⎦ 

(4.36) 

If the utility system operates under normal conditions, or if any balanced fault 

occurs, positive sequence d–q components (Vd and Vq) are DC components. If any 

unbalanced fault occurs, the resulting voltage sag/swell is unbalanced and contains 

both positive sequence and 100 Hz (for 50 Hz network frequency) negative sequence 

components(Tumay et al., 2009). For a positive sequence SRF, the positive sequence 

component can be named as DC, and 100 Hz negative sequence component can be 

named as ripple. Conventionally, to separate the DC component and ripples, a low 

pass filter (LPF) is used after 

p 

dq 

2 

d 

2 

q 

V = V = V + V operation. Nevertheless, the 

‘original positive sequence component’ cannot be obtained. The filter also causes a 

certain amount of delay in the error signal. Vp is used for error calculation after 

separation of DC components and ripples by disturbance filters(Tumay et al,2009). 

64


Figure 4.11. Conventional SRF based detection 

2 

d 

2 

q 

From Figure 4.11, V = V = V + V , this voltage varies with the grid 

p 

dq 

voltages then the voltage sags can be detected from value of V 

dq 

. This V 

dq 

is filtered 

by low-pass filter (LPF) for 

2ω 

or 100-Hz component elimination (for 50-Hz 

distribution systems). The filtered V 

dq 

or V 

dq , f 

is finally compared to a dc reference 

in comparator (i.e. 0.9 pu). The comparator output is a sag signal, which initiates a 

voltage sag compensation process when the voltage sag occurs(Sillapawicharn et 

al,2011). 

To compensate unbalance voltage sags, three-phase symmetric voltages can 

be constructed by a-phase voltage, which is carried into dq transform according to 

the equation(Jianwei et al,2011): 

V 

a 

= V 

ref 

n 

( iy + ϑ ) + 2u 

( ωiy 

+ ) 

n 

∑ u 

i= 

1 1i 

sin 

1i 

∑i 

= 

, a 

= 2 ω 

2i 

sin ϑ 

i 

(4.38) 

1 2 

It can be constructed for 

V 

ref , b 

= 

⎛ 2π 

⎞ 

⎛ 2π 

⎞ 

ω u ⎜ + + ⎟ 

= i i 

it 

1 1 

2 

1 2 

sin ω ϑ2i 

(4.39) 

⎝ 3 ⎠ 

⎝ 3 ⎠ 

n 

n 

∑ 2u1 

i 

sin⎜ 

it + ϑ 

i 

− ⎟ + ∑ = 

i 

V 

ref , c 

= 

⎛ 2π 

⎞ 

⎛ 2π 

⎞ 

ω u ⎜ + − ⎟ 

= i i 

it 

1 1 

2 

1 2 

sin ω ϑ2i 

(4.40) 

⎝ 3 ⎠ 

⎝ 3 ⎠ 

n 

n 

∑ 2u1 

i 

sin⎜ 

it + ϑ 

i 

+ ⎟ + ∑ = 

i 

65


Also, it can be written as, 

2π 

4π 

π 

V 

ref , b 

= Va∠ 

( − ) = Va∠ 

( ) = −Va 

∠ ( ) 

(4.41) 

3 3 3 

π 

( V + V ) = −V 

+ V ∠ ( ) 

V 

ref , c 

= − 

a ref , b a a 

(4.42) 

3 

ref b 

According to above expression, each equation is repeated for b and c phases. 

V , 

can be got by A-phase voltage forward π / 3 , the opposite of the sum of A- 

phase and B-phase voltages is Vc, Assume the system period is 20 ms, then the 

three-phase voltages constructed by this method theoretically delay 

ms (Jianwei et al,2011). 

20ms 

* π 

, as 3.4 

2π 

*3 

Figure 4.12. Proposed SRF based phase detection (a) Phase A, (b) Phase B, 

(c) Phase C 

66


Figure 4.12 shows that the unbalance voltage sag/swell in three phase systems 

are detected to compansate unbalance voltage sag/swell seperately. 

dqc f 

V 

dqa f 

Vdqb, 

f 

, 

, and 

V , 

are severally filtered by low-pass filter for component elimination. Finally, 

the filtered 

V 

dqa, f 

Vdqb, 

f 

, Vdqc, 

f 

, are finally compared to a dc reference in comparator. 

The comparator output is a sag/swell signal, which initiates a voltage sag/swell 

compensation process when the voltage sag/swell occurs. 

4.3.1.3. SOGI-PLL 

Signals of the electrical utility grid are usually corrupted by noise and 

harmonics. One way to remove these interferences is to apply filters. Either fixed or 

adaptive filters can be used to fulfill the above purpose. Yet, the design of fixed 

filters requires prior knowledge of both the signal and the noise, which may be 

difficult to obtain, especially when the three-phase grid is subjected to unbalanced 

faults. On the other hand, adaptive filters are able to adjust their impulse responses 

automatically according to the output signal of the filters, and their designs require 

less knowledge of the source signals or noise characteristics. This property of 

adaptive filters has made them highly useful for a variety of applications. For PLL 

applications, the adaptive filtering technique is employed mainly for noise reduction 

and quadrature signal generation, as is illustrated in the following example(Gao et 

al.,2012). 

67


where k affects the bandwidth of the closed-loop system(Ciobotaru et al.,2006). 

4.3.1.4. Reference Generation Using Sag Detection Methods 

Sag detection methods are used to detect balanced/unbalanced sag and swells. 

Firstly, all voltage signals are converted to per unit values. Magnitude signal (A(t)) is 

extracted form EPLL, SRF and SOGIPLL. A(t) signal is subtracted from reference 

signal (1 pu), the voltage sag/swell depth is calculated as shown in Figure 4.14. It 

shows the structure of sag/swell depth detection method based on EPLL, SRF and 

SOGIPLL. 

Figure 4.14. Block diagram of proposed method based on EPLL, SRF and 

SOGIPLL(Köroğlu,2012) 

Sag/swell depth is calculated using (4.35): 

S depth 

= 1− 

A( 

t) 

(4.46) 

Figure 4.15 shows a single phase sag condition for three sag detection 

methods. As shown in figure, voltage sag initiates at 0.3s with a 0.1s duration and 

%30 sag depth. 

69


10.0 

8.0 

6.0 

4.0 

2.0 

0.0 

-2.0 

-4.0 

-6.0 

-8.0 

-10.0 

Voltage Sag 

Vbusbar A Vbusbar B Vbusbar C 

0.280 0.300 0.320 0.340 0.360 0.380 0.400 0.420 

(a) 

Voltage Sag Detection Signal(EPLL) 

Voltage Sag Detection(SRF) 

Voltage Sag Detection (SOGIPLL) 

(b) (c) 

Figure 4.15. (a) Busbar, (b) magnitude(sag depth) and (c) sag detection signals 

It is shown Figure 4.15, SRF is the best way to detect voltage sag and swell 

compared to EPLL and SOGIPLL. SRF is more superior than EPLL and SOGIPLL 

due to its speed and The advantages of SRF are fast and more accurately than EPLL 

and SOGIPLL. EPLL and SOGIPLL extract phase information which is an 

advantage compared to SRF. However, It is clear that EPLL and SOGIPLL have 

more oscillatory than SRF. 

70


4.3.2. Voltage Injection Strategy 

Voltage sag and swell problems have several characteristic properties which 

must be compensate. Sag/swell magnitude and phase jump problem are the most 

important problems in sensitive loads. Therefore, the voltage injection strategies 

must be applied depend upon these major issues. 

The standard solution for compensating voltage sags is to reestablish the 

exact voltage before the sag. Therefore, the amplitude and the phase of the voltage 

before the sag have to be exactly restored. The resulting vector is shown in Figure 

4.16.(Meyer et al., 2008) 

Figure 4.16 Phasor diagram of Pre-Sag Compensation methods 

In PSC method, determining pre-sag angle (θ presag ) is determined by using a 

phase freezer unit. In literature, conventional phase freezer unit is created by 

measuring the supply voltage (V s ) and freezing the phase angle of the supply voltage 

when sag occurs. The phase angle of the supply voltage is used as the reference 

phase angle of the load voltage (V l ) during sag operation as seen in Figure 4.17 

(Delfino et al.,2005; Nielsen et al.,2004; Vilatgamuwa et al.,2002; Ajaei et al.,2011; 

Köroğlu,2012). 

71


Figure 4.17. Conventional phase freezer unit(Köroğlu,2012) 

The most important disadvantage of the conventional phase freezer unit is 

that it tracks both supply and load voltages and needs two independent voltage 

measurements. The conventional method works with no error in simulation 

environment but in practical it is very difficult to measure both supply and load side 

voltages. Supply measurement should be somewhere upstream of the fault which is 

difficult to locate and measure. To overcome the disadvantages of the conventional 

phase freezer unit, proposed algorithm is used in this thesis seen from Figure 

4.20(Köroğlu,2012). 

The block diagram of the proposed DVR control system for single-phase is 

shown in Figure 4.19. Supply-side and load-side voltages are defined by (4.47) and 

(4.48), respectively 

v 

presag 

presag 

( ω t + ϑ ) 

= V × cos (4.47) 

presag 

v 

l 

sl 

( ω t + ϑ ) 

= V × cos (4.48) 

l 

Based on the presag compensation method, the voltage phasor, which must be 

injected by the DVR, is the complex difference between the supply voltage phasor 

and the presag supply voltage phasor, as shown in the vector diagram of Figure 4.17. 

This phasor ( V 

inj 

) is calculated by the phasor subtraction unit, shown in Figure 4.18, 

72


according to (4.47) and (4.48). The coefficient γ in (4.47) is 1 when 

V 

presag 

cosϑ > V cosϑ 

; otherwise, it is “-1”(Ajaei et al.,2011) 

presag 

S 

S 

V 

inj 

2 

( V cosϑ 

−V 

cosϑ 

) − ( V sinϑ 

−V 

sinϑ 

) ) 

2 

= γ × 

(4.49) 

presag 

presag 

S 

S 

presag 

presag 

S 

S 

ϑ 

inj 

⎛ 

⎞ 

− 

Vpresag 

sinϑpresag 

−VS 

sinϑS 

= tan 1 ⎜ 

⎟ 

(4.50) 

⎝Vpresag 

cosϑpresag 

−VS 

cosϑS 

⎠ 

Figure 4.18. Phasor subtraction 

73


In the proposed phase freezing method, load side voltage is used to generate 

phase information shown in Figure 4.19. The phase angle of load side voltage is 

written to an array by two periods which each perios is 1000 sample. When sag 

occurs at a time, EPLL detects sag and sends enable signal (i1); then the phase 

information of one period before sag initiated is used as output phase. So, the phase 

is freezed and used during the sag. When sag finishes, instant phase information is 

used as output again. This process repeats itself for every sample time (Köroğlu, 

2012). The proposed system is simulated using presag compensation method. Phase 

freezing process is shown in Figure 4.20. The system in Figure 4.21 has a fault 30% 

sag with 12 o angle jump initiates at 0.3s with a duration of 0.1s. It explains to 

achieve phase freezing process between ϑ andϑ . 

s presag 

Figure 4.20. Block diagram of the phase freezing in DVR control 

Figure 4.21. Reference voltages generated with In-Phase and Pre-Sag methods 

75


Depending on the phase angle of the grid voltage during the sag, the DVR has 

to deliver a higher voltage amplitude to restore the correct voltage magnitude, 

because the phase jump of the grid has also to be compensated by the DVR. 

Therefore, the system has to be designed for a higher maximum voltage. In addition, 

less energy from the DC-link can be extracted (Meyer at al., 2008). Figure 4.22 

shows simulation results for 30% sag with 12 o angle jump starts at 0.3s with a 

duration of 0.1s. The amplitude of V 

error, presag 

is higher than V 

error, inphase 

. 

4.3.3. Voltage Control Strategy: Closed Loop 

In the case of voltage compensated APFs, output filters nand inverters are the 

main components. The inverter output voltage passes through the output filters to get 

switching-ripple-free compensation voltages. However, the output filters bring in 

time delay and resonance problems on the compensation voltage also. Thus, proper 

control methods are required to get the output compensation voltage according to a 

reference value (Kim et al., 2005). The accuracy and dynamic operation of dynamic 

voltage restores is an important issue. Basically, there are two voltage control 

strategies used in the dynamic voltage restorer: open loop and closed-loop. 

Open Loop method is uncontrolled and poor dynamic performance due to 

lack of its simple structure. Another disadvantage of using such open-loop control 

scheme is that the steady-state load voltage may not be compensated to the desired 

value owing to voltage drop across the transformer series impedance and the filter. 

This becomes particularly important if the load is nonlinear as nonsinusoidal currents 

drawn by such a load can distort the load voltage(Vilathgamuwa et al., 2002). In 

proposed method, Closed loop method is preferred due to its strong dynamic 

behavior. For the DVR injection voltage control, a multiloop control scheme is 

implemented as illustrated in Figure 4.22. 

76


V (s) 

- 

V ref (s) 

- 

v 

- 

c 

i 

Error 

Signal 

for PWM 

V (s) 

I (s) 

Figure 4.22. Proposed multiloop control method 

To track the load voltage properly, it is necessary to include a load voltage 

feedback. If the filter capacitor current is fed back to achieve a sinusoidal capacitor 

current while an outer voltage loop is used to regulate the output voltage. A 

feedforward loop will also be incorporated to improve dynamic response of the load 

voltage(Vilathgamuwa et al., 2002). After a voltage sag/swell is detected, the 

difference between the reference voltage and measured load voltage is calculated in 

per unit. The DVR injected voltage feedback ( V l 

) is compared with its reference 

( V ref 

) and the capacitor current(Ic) is used to improve dynamic performance of DVR. 

Then, the error is used to generate PWM signals. 

The natural damping frequency of closed-loop 

ω 

damping 

, 

1 

ω 

damping 

= ( 1+ 

nkikckv 

) 

(4.51) 

L C 

f 

f 

The natural damping frequency in closed loop system is therefore 

approximately 1+ nk k k ) times filter resonance frequency. The value of LC 

( 

i c v 

cutoff frequency is about 300 Hz in open loop control method. By choosing 

n 2 , k = 1, k = 50, k = 0.15 in proposed controller, Figure 4.23 explain the effect 

= 

i v 

c 

of closed loop method compared to open loop. 

77


Vbusbar(rms) 

CLOSE-LOOP VOLTAGE CONTROL METHOD 

Vload(rms) 

7.00 

6.80 

6.60 

6.40 

6.20 

6.00 

5.80 

5.60 

5.40 

5.20 

5.00 

4.80 

4.60 

4.40 

4.20 

4.00 

7.00 

6.80 

6.60 

6.40 

6.20 

6.00 

5.80 

5.60 

5.40 

5.20 

5.00 

4.80 

4.60 

4.40 

4.20 

4.00 

0.200 0.240 0.280 0.320 0.360 0.400 0.440 0.480 

Vbusbar(rms) 

OPEN-LOOP VOLTAGE CONTROL METHOD 

Vload(rms) 

0.200 0.240 0.280 0.320 0.360 0.400 0.440 0.480 

Figure 4.23. Comparison of Close Loop and Open Loop in proposed DVR 

As it is seen from Figure 4.23, Closed loop shows better performance than 

open loop method. Closed loop regulate the output voltage and keeps it constant at 

the side where a nonlinear load is connected. 

4.3.4. Gate Signal Generation 

In proposed DVR, gate signals are generated for two converters: 

• Symmetrical five level diode clamped multilevel inverter 

• Full bridge DC-DC converter 

78


4.3.4.1. Inverter 

The gating signals in inverter are generated by using modulating techniques. 

The most popular modulation techniques are sinusoidal pulse width modulation, 

space vector modulation, fuzzy logic controller etc. Sinusoidal Pulse Width (SPWM) 

technique is used to generate gate signals in proposed DVR. The gating signals are 

generated by comparing a sinusoidal reference with a triangular carrier signal. The 

amplitude of carrier signal controls the modulation index and it regulates output 

voltage of inverter. The modulation index is expressed as below: 

A 

A 

R 

M = (4.52) 

C 

The switching frequency of solid-state devices in diode clamped multilevel 

inverter is selected as 3000 Hz. Two triangular waves for each five-level diode 

clamped inverter are compared with two reference signal. Each triangular wave is 

compared with error (reference) signal as shown in Figure 4.24. 

Figure 4.24. Generation of gate signals for each multilevel five level diode clamped 

inverter 

79


Firstly, PI control measures 

V 

dc 

and compare it with V dc , ref 

(1.7kV 

) When 

Vdc 

below down V dc , ref 

(1.7kV 

) , PI signal is generated and compared with reference 

signal. This process repeated itself continuously. If PI output is greater than reference 

signal, reference is equal to reference signal(0.6). If PI output generates lower 

magnitude signal than reference(0.6), reference signal is equal to PI output and gate 

signals are generated. 

Carrier and reference signals generated by PI controller are shown in Figure 

4.26. 

Figure 4.26. Carrier and reference signals generated by PI controller 

Timing diagram with modulation waveforms are presented in Figure 4.27. 

Gate signals (S1, S2, S3 and S4) are generated with comparison of reference signal 

with carrier. 

81


Figure 4.27. Generation of gate signals for full bridge dc-dc converter 

82

5. SIMULATION RESULTS AND CASE STUDIES Mustafa İNCİ 

5. SIMULATION RESULTS AND CASE STUDIES 

This section presents the simulation results of multilevel inverter based DVR 

with DC-DC Converter. Simulation results consist of comparison of sag/swell 

detection methods (EPLL, SRF, SogiPLL), voltage control strategies (Open Loop, 

Closed Loop) and different voltage sag case studies. 

A 1 MVA, 1.2/2.4 kV transformer is used for connecting the DVR to the 

network. The proposed DVR model is simulated by PSCAD/EMTDC to compensate 

voltage sag and voltage swell at the source side. The power circuit and 

PSCAD/EMTDC diagram of proposed DVR system used in this thesis are 

shown in Figure 5.1. 

Figure 5.1. PSCAD/EMTDC model of proposed DVR System 

83


Simulation parameters used in PSCAD/EMTDC are given in Table 5.1. 

Parameters of system, load, diode clamped multilevel inverter and dc-dc converter 

injection transformer are presented in Table 5.2-6, respectively. 

Table 5.1. PSCAD/EMTDC Simulation Parameters 

PSCAD/EMTDC Parameters 

Solution Time Step 20 µs 

Channel Plot Step 20 µs 

Duration of Simulation Run 

2 s 

Table 5.2. System Parameters 

System Parameters 

Fundamental Frequency 

Voltage Source (V S1 ) 

Impedance of Feeder-I (R S1 + j2πL S1 ) 

Short Circuit Powers of Feeder-I 

50 Hz 

11 kV (L-L, rms), phase angle 0 o 

0.000001 + j0.037699 Ω 

1500 MVA 

Table 5.3. Simulated Load Parameters 

Load Parameters 

Nonlinear/Sensitive Load (L1) 

A three-phase diode rectifier that supplies a load 

of 100 + j125.66 Ω, 710 kVA, pf = 0.983, 

THD=5.1 % 

Table 5.4. Simulation parameters of Voltage Source Inverter 

DVR (VSI) 

Compensation Rating 30% 

Filter inductor (L f ) 

1.5 mH 

Filter Capacitor (C f ) 150 µF 

Filter Resistance (R f ) 

Power Rating 

0.05 Ω 

1230 kVA 

84


Table 5.5. Simulation parameters of Full Bridge DC-DC Converter 

DVR (DC-DC Converter) 

Transformer Rating 

0.5 MVA 

Turn ratio (Ns/Np) 2/1 

Input Capacitor (C1) 

Output Capacitor (C eq ) 

Input Voltage 

Output Voltage 

5 mF 

25 mF 

0.85 kV(dc) 

1.7 kV(dc) 

Table 5.6. Injection Transformer Parameters 

Injection Transformer (TR) 

Transformer MVA 

Base Operation Frequency 

Turns Ratio 

Leakage Reactance 

1 MVA 

50 Hz 

1.2 / 2.4 kV 

0.001 pu 

5.1. Comparison of Sag Detection Methods (EPLL, SRF and SogiPLL) 

Voltage sag/swell must be detected fast and compensated accurately. The 

sag inception is defined as the instant, when the RMS voltage (Vrms) of the supply 

drops below 0.9 p.u. The swell inception is defined as the instant, when the RMS 

voltage (Vrms) of the supply rises upper than 1.1 p.u. 

Firstly, unbalance sag condition is considered because of single line-toground 

fault is the most common type in transmission and distribution systems. 

Firstly, 30% single-phase voltage sag occurs between 0.3 s < t < 0.4 s. EPLL, SRF 

and SogiPLL is used to detect single-phase unbalance voltage sag. Figure 5.2 (a), (b) 

and (c) shows the source-side voltage, voltage sag inception time and magnitude 

information by using sag detection methods. 

85


Figure 5.2. (a) Source side busbar voltages, (b) Voltage sag inception time and (c) 

Magnitude information for three sag detection methods 

Sag inception times for three methods are given in Table 5.7. 

86


Table 5.7. Sag inception and finish time for three methods 

Voltage Sag (Phase A) Inception Finish Result 

EPLL 0.3028 s 0.4046 s Medium 

SRF 0.3012 s 0.4019 s Fast 

SogiPLL 0.3039 s 0.4055 s Slow 

It is shown Table 5.7, SRF is the best way to detect voltage sag and swell 

compared to EPLL and SOGIPLL. Although EPLL and SogiPLL extract the phase 

information compared to SRF, SRF is more superior than EPLL and SOGIPLL due 

to its speed and accuracy. However, It is clear that EPLL and SOGIPLL have more 

oscillatory than SRF as shown in Figure 5.2 (c). 

Figure 5.3 and Figure 5.4 show injected voltages and load-side voltages by 

using three sag detection methods. 

Figure 5.3. Injected voltages by using three sag detection methods 

87


y 

y 

y 

12.0 

9.0 

6.0 

3.0 

0.0 

-3.0 

-6.0 

-9.0 

-12.0 

12.0 

9.0 

6.0 

3.0 

0.0 

-3.0 

-6.0 

-9.0 

-12.0 

12.0 

9.0 

6.0 

3.0 

0.0 

-3.0 

-6.0 

-9.0 

-12.0 

DVR : Graphs 

Vload_A_DQ Vload_B_DQ Vload_C_DQ 



0.260 0.280 0.300 0.320 0.340 0.360 0.380 0.400 0.420 0.440 ... 

... 

... 

Figure 5.4. Source side voltages by using EPLL, SRF and SogiPLL methods 

5.2. Simulation Results for Open Loop and Closed Loop 

Weather (lightning, wind, ice), animal contact, contamination of insulators, 

construction accidents, motor vehicle accidents, falling or contact with tree limbs can 

result in voltage sags. Such faults may be 3-phase, line-to-line, or single line-toground. 

The 3-phase faults are the most severe, but are relatively unusual(Bingham, 

1998). In proposed DVR, the voltage sags with 12◦ phase jump have been generated 

by controlled short circuit impedance in the grid. 

5.2.1. Open Loop Voltage Control Method 

Three case studies (Case 1, Case2 and Case 3) are presented for the following 

sag types using open loop control method: 

88


• Single Phase Unbalance Voltage Sag 

• Two Phase Unbalance Voltage Sag 

• Three-phase balanced Voltage Sag 

5.2.1.1. Case 1: Single Phase Voltage Sag 

The great number of faults is single-phase line to ground fault (SLGF). In this 

case, single phase to ground fault is analyzed. This fault occurs on Phase-C. The 

phase voltage decreases to 70% from its nominal value during the period of 0.3-0.4 s. 

In this fault, phase jump occurs between source-side and load-side voltages. 

Phase jump is compensated by using presag compensation method. 

Figure 5.5. Simulation results for Case 1 

89


Figure 5.6. DC link voltage for Case 1 

DC link capacitor voltage is kept at reference value (1.7 kV) by DC-DC 

Converter. DC link capacitor voltage (V cap ) varies between 1.655-1.68 kV band when 

the voltage sag occurs as it is seen from Figure 5.6. As soon as the sag is finished, dc 

link voltage (V c ) returns to its steady state value. 

90


RMS characteristics of Phase A, Phase B and Phase C voltages are seen in 

Figure 5.7 when single phase voltage sag occurs on Phase C. 

Figure 5.7. RMS Characterisics for Case 1 

5.2.1.2. Case 2: Two Phase Voltage Sag 

A and B phase source voltage decreases to 70% from its nominal value 

during the period of 0.3-0.4 s. In A and B phases, phase jump occurs between 

source-side and load-side voltages. DVR operation for double line to ground fault is 

91


seen in Figure 5.18. Figure 5.8 (a) and 5.8 (b) show the simulation results of sourceside 

voltages and injected voltages under double-phase to ground fault. The load 

voltage is maintained at the desired 1 p.u. as shown in Figure 5.8 (c). 



Converter. DC link capacitor voltage (V cap ) varies between 1.627-1.651 kV band 

92


when the voltage sag occurs as it is seen from Figure 5.9. As soon as the sag is 

finished, dc link voltage (V c ) returns to its steady state value(1.7 kV). 



Figure 5.10 when two phase voltage sag occurs on Phase A and Phase B. 

93


Figure 5.10. RMS characteristics for Case 2 

5.2.1.3. Case 3: Three Phase Voltage Sag 

In this case, three phase balanced fault occurs. A, B and C phase source 

voltages decrease to 70% from its nominal value during the period of 0.3-0.4 s. In all 

phases, phase jump occurs between source-side and load-side voltages. Figure 

5.11 shows the simulation results of source-side, injected and load-side voltages 

under three-phase to ground fault. The load voltage is maintained at the desired 1 p.u. 

as shown in Figure 5.11. 

94




Converter. DC link capacitor voltage (V cap ) drops to 1.61 kV when the voltage sag 

occurs as it is seen from Figure 5.12. As soon as the sag is finished, dc link voltage 

(V c ) returns to its steady state value(1.7 kV). 

95




Figure 5.13 when three phase balance voltage sag occurs. 

96



5.2.2. Closed Loop Voltage Control Method 

Voltage sag compensation is provided by closed loop method in Case 4, Case 

5 and Case 6. Three case studies are presented for the following sag types using 

closed loop control method: 

• Single Phase Unbalance Voltage Sag 

• Two Phase Unbalance Voltage Sag 

• Three-phase balanced Voltage Sag 

97


5.2.2.1. Case 4: Single Phase Voltage Sag 

The phase voltage decreases to 70% from its nominal value during the period 

of 0.3-0.4 s on Phase-C. In this fault, phase jump occurs between source-side 

and load-side voltages. Figure 5.14 shows source-side, injected and load-side 

voltages, respectively. 


98





the voltage sag occurs as it is seen from Figure 5.15. As soon as the sag is finished, 

dc link voltage (V c ) returns to its steady state value. 


Figure 5.16 when single phase voltage sag occurs on Phase C. 

99


Figure 5.16. RMS characterisics for Case 4 

5.2.2.2. Case 5: Two Phase Voltage Sag 

A and B phase source voltage decreases to 70% from its nominal value 

during the period of 0.3-0.4 s. In A and B phases, phase jump occurs between 

source-side and load-side voltages. DVR operation for double line to ground fault is 

seen in Figure 5.17. It shows the simulation results of source-side, injected and loadside 

voltages under double-phase to ground fault. The load voltage is maintained at 

the desired 1 p.u. as shown in Figure 5.17. 

100





the voltage sag occurs as it is seen from Figure 5.18. As soon as the sag is finished, 

dc link voltage (V c ) returns to its steady state value(1.7 kV). 

101




Figure 5.19 when two phase voltage sag occurs on Phase C. 

102



5.2.2.3. Case 6: Three Phase Voltage Sag 

In this case, three phase balanced fault occurs. A, B and C phase source 

voltages decrease to 70% from its nominal value during the period of 0.3-0.4 s. In all 

phases, phase jump occurs between source-side and load-side voltages. Figure 

5.20 shows the simulation results source-side voltages and injected voltages under 

three-phase to ground fault. The load voltage is maintained at the desired 1 p.u. as 

shown in Figure 5.20. 

103




Converter. DC link capacitor voltage (V cap ) drops to 1.615 kV when the voltage sag 

occurs as it is seen from Figure 5.21. As soon as the sag is finished, dc link voltage 

(V c ) returns to its steady state value(1.7 kV). 

104




Figure 5.22 when three phase balance voltage sag occurs. 

105



5.2.3. Comparison of Voltage Control Methods 

Control methods are required to get the output compensation voltage 

according to a reference value (Kim et al., 2005). The accuracy and dynamic 

operation of dynamic voltage restorer is an important issue. Table 5.8 shows the 

comparison results of open loop and closed loop control methods. 

106


Table 5.8. Comparison and RMS values of phase voltages in open loop and close 

loop control method 

RMS Values Of Phase Voltages 

Fault Type Open Loop Closed Loop 

Va Vb Vc Va Vb Vc 

Single Phase Fault 6.35 6.35 6.17 6.35 6.35 6.35 

Two Phase Fault 6.15 6.15 6.35 6.32 6.32 6.35 

Three Phase Fault 6.1 6.075 6.08 6.27 6.26 6.25 

As it is seen from simulation results, closed loop shows better performance 

than open loop control method. Also, simulation results show the effectiveness of 

closed loop control method against open loop method. It is clear that injected voltage 

in close loop has more sinusoidal shape than injected voltage than open loop. Closed 

loop regulate the output voltage and keeps it constant at the side where a nonlinear 

load is connected. 

107


108

6. CONCLUSION Mustafa İNCİ 

6. CONCLUSION 

The most severe power quality problems in electrical systems are called as 

voltage sag and swell. Dynamic Voltage Restorer (DVR) is an effective solution to 

solve these power quality problems. Dynamic voltage restorer is a series connected 

device located between sensitive/nonlinear load and grid in system, it both detects 

voltage sag/swell problems and injects controlled voltage to system. 

In this study, multilevel inverter based DVR with DC-DC converter is 

modeled using PSCAD/EMTDC. The proposed DVR is designed for medium 

voltage level (11 kV) system. DVR in a three phase system is designed to protect 1 

MVA nonlinear load. The voltage sags with phase 12◦ jump are generated by 

controlled short circuit impedance in the grid. 

The basic elements and trends in literature are described in Chapter 3. The 

design parameters for a DVR are given in Chapter 4. Control strategies are also 

explained in this chapter. Two voltage injection strategies (Presag, Inphase) are 

implemented and tested. When phase jump occurs in system, In-Phase and Pre-sag 

methods show similar performance. If phase between source-side and load-side 

consist of phase jump, Pre-Sag compensation method represents better performance 

than in-phase compensation method. 

SRF based control technique is used to detect and extract the PQ disturbances 

in system. Also, EPLL and SOGI-PLL are used to detect and extract the voltage sag 

and swell. SOGI-PLL is a new method to extract voltage magnitude and phase angle 

simultaneously. The comparison results of EPLL, SRF and SOGI-PLL are presented 

in simulation results. 

The accuracy and dynamic operation of dynamic voltage restorers is an 

important issue. In available literature, there are two voltage control systems used in 

DVR applications: open loop and closed loop. Error signals are obtained by using 

closed loop and open loop voltage control strategies in proposed study. It is 

observed that rms characteristics in closed loop system have more smooth shape than 

injected voltage in open loop system. 

109


The inverter circuit in DVR is used to inject controlled voltage and maintain 

the desired output voltage. The most common inverter topologies in literature are the 

two- or three-level three-phase converter used in DVR. For high power applications, 

the use of two-level voltage converters becomes difficult to perform because of 

switch ratings and efficiencies. To prevent this condition, the symmetrical five level 

diode-clamp inverter is selected in proposed DVR. Symmetrical five level diodeclamped 

inverter consists of two single phase three level diode clamped inverter for 

each phases. In this wise, it can compensate balanced and unbalanced voltage 

sag/swell. It has advantages compared with cascade and diode clamped mutilevel 

inverters such as reduction the quantity, size and dimension of dc-link capacitors 

with lower cost. Sinusoidal Pulse Width Modulation (SPWM) based control scheme 

is chosen for the proposed multilevel inverter, two carrier based modulation 

technique for each diode clamped inverter has been presented and explained in this 

thesis. 

DC link voltage is an important issue when voltage sag occurs. To keep dc 

link voltage constant and to compensate deep and long duration voltage sag, DC-DC 

converter is employed. Full-Bridge isolated DC-DC converter is used in proposed 

DVR. The controller design procedures of the full bridge isolated dc/dc converter are 

presented. The simulation results show its effectiveness in DC link capacitor and 

keep it constant. 

In Chapter 6, the simulation results of proposed DVR are presented. System 

is constructed in PSCAD/EMTDC. Firstly, simulation is performed for different sag 

detection methods, voltage control strategies and voltage injection techniques. 

Secondly, simulation results are initiated for different voltage sag cases using open 

loop and closed loop voltage control methods. Source-side, load-side, injected 

voltages and DC-link voltages are given in simulation results. The proposed system 

shows that sag compensation is restored successfully. 

Voltage sags are the most important power quality problems in industrial areas. 

DVR is the most effective solution to compensate the disturbances. To reduce cost 

and improve performance of DVR, studies continue in the following topics. 

110


• Energy optimization 

• Elimination of injection transformers 

• Energy Storage Unit (SMES, PV, Supercapacitor) 

• DC-DC Converter to keep DC link voltage constant 

• Transformer problems 

• Reducing the number of components 

• Multiple functions of DVR 

• High voltage applications 

• Multilevel inverter based DVR structures 

• AC-AC converter based DVR structures 

• Elimination of DC link capacitors 

By performing trend topics, higher efficiency and lower cost can be achieved 

compared with available systems. 

111

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BIOGRAPHY 

Mustafa İNCİ was born in Şanlı Urfa, Turkey in 1987. He received his B.S. 

degree in Electrical and Electronics Engineering Department from Çukurova 

University in 2011. After completion his B.S. education, he started MSc education in 

Electrical and Electronics Engineering Department in Çukurova University in 2011. 

He has been working as a Research Assistant in Electrical and Electronics 

Engineering Department of the Çukurova University since 2011. His research areas 

are Power Quality, Power Electronics, Renewable Energy and Energy Efficiency. 

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APPENDIX 

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LIST OF PUBLICATIONS 

International Conferences 

• DEMIRDELEN, T., INCI, M., BAYINDIR, K.C., TUMAY, M., 2013. 

Review of Hybrid Active Power Filter Topologies and Controllers, 4 th 

International Conference on Power Engineering, Energy and Electrical 

Drives, POWERENG-2013, 13-17 May, Istanbul in Turkey 

• KOROGLU, T., INCI, M., BAYINDIR, K.C., TUMAY, M., 2013. 

Modeling and Analysis of a Nonlinear Adaptive Filter Control for Interline 

Unified Power Quality Conditioner, 4 th International Conference on Power 

Engineering, Energy and Electrical Drives, POWERENG-2013, Istanbul in 

Turkey 

National Conferences 

• INCI, M., KOROGLU, T., BAYINDIR, K.C., TUMAY, M., 2013. Şebeke 

Gerilim Değişimlerini Sezme Amaçlı Kontrol Metodlarının İncelenmesi 

ve Performanslarının Değerlendirilmesi(Turkish), V. Enerji Verimliliği Ve 

Kalitesi Sempozyumu 2013, Kocaeli, Page(s): 180-184 

• DEMİRDELEN, T., TAN, A., İNCİ, M., KÖROĞLU, T., BÜYÜK, M., 

TERCİYANLI, A., BAYINDIR, K.K., TÜMAY, M., 2013. Şebekeye 

Bağlı Sistemler için Üç Faz ve Tek Faz PLL’lerin Performans 

Değerlendirmesi(Turkish), V. Enerji Verimliliği Ve Kalitesi Sempozyumu 

2013, Kocaeli , Page(s): 5-9 

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EQUATIONS 

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ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED ...

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