Fine Pitch Flip Chip with Cu Pillar

IME Proprietary 

EPRC – 11 

Project Proposal 

Fine Pitch Flip Chip 

with Cu Pillar 

9 th November 2010 

Slide 1


Motivation 

• Increasing adoption of Flip Chip for 

mobile application 

‣Electrical performance 

‣High I/O interconnect 

‣Thinner package 

‣Cost effective for high pin count 

pkg 

• Cu pillar emerged as solution for fine 

pitch flip chip application 

‣ Standoff between chip & 

substrate 

(Source: private communication with a wafer foundry ) 

‣ Avoid solder short 

‣ Thermal performance 

(Source: Infineon) 

Slide 2

Technology Trends 


(Source: Prismark) 

Cu pillar bump on commercial microprocessor 

Fine pitch Cu pillar bump on lead substrate 

Effect of UF properties 

(Source : Amkor) 

Slide 3 

(Source: Chipworks) 

(Source : Amkor)

Challenges to be Addressed 


Interconnection 

induced 

stress on Cu low K 

structure 

• UBM & pillar design 

• Low CTE substrate 

• UF material 

• Reflow process 

Reliable joining method and 

process issue for fine pitch 

Cu pillar 

• Pillar & lead design 

• Joining material 

• Reflow process 

• UF material 

Effect of Cu pillar Sizes for 

different Pitch 

• Routing design rule 

• Pillar fabrication 

• Assembly processibility 

• Substrate layout 

Electromigration issues 

for different Cu pillar and joining 

material 

• Current density distribution 

modeling for different pillar size 

and joining 

• Characterization verification 

Fine pitch 

substrate 

• BU (130 -100um) 

• 2 layer (50-40um) 

Si 

Underfilling material, 

process and reliability for 

fine pitch Cu pillar 

• Underfill material type 

• Underfill process 

• Fluxing process 

Substrate 

Substrate 

Challenge 

Approach 

Test vehicle 1 * 


Slide 4 

• Larger chip**, full array bump 

• BU substrate with SOP 

• Fine pitch bump (130um – 100um) 


• Capillary underfill 

**Remark: Cu low K chip – subject to availability 

* To be finalized with members input 

• Smaller chip**, periphery array bump 

• Low cost 2 layer substrate 

• Fine pitch bump (50um - 40um) 

• MUF, WL-UF, NF-UF** 

**Remark: To be finalized with member’s input and subject 

to availability

Project Proposal 

Objective: 

Development and characterization of fine pitch Cu pillar interconnect for next generation devices, 

including the following: 


Structural design and failure mechanism analysis of fine pitch Cu pillar for Cu low K application 

Parasitic extraction, EM modeling and characterization for fine pitch Cu pillar 

Structural and electrical design rule for fine pitch Cu pillar (130um – 40um) 

Development of Cu pillar with different joining method including solder cap, solder bump and Cu-Cu 

Material characterization including fine pitch substrate with low CTE material and underfill 

Assembly, reliability testing and failure analysis 



• Larger chip**, full array bump 

• BU substrate with SOP 

• Fine pitch bump (130um – 100um) 


• Capillary underfill 

**Remark: Cu low K chip – subject to availability 

• Smaller chip**, periphery array bump 

• Low cost 2 layer substrate 

• Fine pitch bump (50um /40um ) 

• Solder cap (SnAg, CuSn) 

• Lead finish (OSP, NiPdAu) 

• MUF, WL-UF, NF-UF** 

**Remark: To be finalized with member’s input and subject 

to availability 

Slide 5 

* To be finalized with members input

Improving Cu Pillar Design for Fine Pitch Application 


 

Structural modeling and failure mechanism of the 

fine-pitch Cu-pillar FC package 

– Cu pillar geometry (e.g. UBM, pillar and landing pad/lead 

geometry, etc) 

– Packaging materials (e.g. properties of underfill material, 

substrate material) 

– Bump failure characterization and correlation with 

modeling 

– Understanding of failure mechanism / low K delamination 

analysis 

Cu pillar for mechanical/electrical 

and routing requirements 

 

Method for stress reduction for advanced Cu low 

K device 

– Compliant-rigid interconnect structures, including 

variable Cu pillar e.g. rectangular pillar 

– UBM and stress buffering design 

– Substrate CTE, landing pad / lead 

– Underfill material properties 

– Reflow process effect 

Slide 6 

(Source: IME)

Effect of Cu Pillar Geometry on 

Interconnect Parasitic and Current Distribution 

Parasitic extraction 

• 3D modeling and experimental characterization the “RLGC” electrical parasitic of the fine 

pitch Cu pillar (150um 40um) for up to 10 GHz 


 

Electromigration modeling and characterization 

• Current density distribution modeling for different pillar size and joining 

• Experiment characterization and verification 

 

 

Experimental characterization 

• Characterization of RLGC parameters overtime under stressed environmental condition e.g. 

temperature and humidity 

Design guidelines for fine pitch routing 

• Cu pillar height, pitch, line width & spacing 

• Crosstalk (< -30 dB) , return loss (>10 dB), insertion loss (

Development of Joining Method and Characterization 

with Fine Pitch Substrate 

Cu pillar + solder cap 

/ metallic + UF 

interconnect 

Process development and characterization of different 

joining methods 

•Comparison of solder cap with SnAg, CuSn, and micro 

SnAg bump 

•Exploration of Cu-Cu for fine pitch Cu pillar application 

• Bonding method (TC, TS, or US) 

• Effect of surface finish: SAM coating, NiAu 


Fabrication for fine pitch Cu pillar and substrate 

•Cu pillar of 130um - 40um bump pitch and AR of >1:1 

•Fine pitch substrate 

• BU substrate (130 -100um pitch) 

• 2 layer substrate (50 um - 40um pitch) 

• Landing pad / lead sizes, shapes, surface finish 


(Source: JCI) 

Slide 8

Assembly Process and Material Characterization, 

Reliability Test and Failure Analysis 


Assembly / process development and characterization 

‣ Fine pitch Cu pillar assembly 

‣ Solder cap coplanarity and solder wetting 

‣ Selection of flux and solder wetting 

‣ Flux dipping process and solder shorting 

‣ Fine pitch substrate finish (OSP, NiPdAu) 

‣ Underfill process characterization 

‣ Capillary flow underfill 

‣ Wafer level underfill 

‣ No-flow underfill 

Source: SPIL 

‣ Package assembly and sample build for reliability 

characterization 

Reliability assessment and Failure analysis 

‣ Moisture sensitivity test 

‣ Temperature cycling test 

‣ High temperature storage test 

‣ Electromigration test 

(Source: Infineon) 

Slide 9

Project Flow 


Members inputs 

Finalize project scope / 

test vehicle spec 

Mechanical/ 

Electrical 

design 

Test vehicle design 

& wafer fabrication 

Solder based Cu pillar 

assembly development 

Fine pitch / low CTE 

substrate fabrication 

Other joining method 

development 

Experiment 

characterization 

Quick reliability assessment, material 

selection and improvement 

Reliability test vehicle fabrication 

Slide 10 

Final reliability test and FA 

Project Time line and schedule : Feb 2011 to Aug 2012

Research Outcome 


• Design and analysis of Cu pillar for fine pitch application 

Structural design optimization of Cu pillar (pillar, solder, land/lead geometry) 

Parasitic and EM analysis of Cu pillar 

Comparison of Cu pillar with cap solder and micro SnAg solder bump 

Design rule for structural and electrical design of Cu pillar (bump pitch 130um – 40um) 

• Development of joining method and fine pitch substrate 

Process development and characterization results of different joining methods 

Cu pillar with solder cap and micro SnAg solder bump 

Exploration of Cu-Cu fine pitch Cu pillar application 

Fabrication for fine pitch Cu pillar and substrate 

Cu pillar of 130um- 40um bump pitch and AR of >1:1 

Organic substrate with 130um - 40um bump pitch 

Landing pad / lead sizes, shapes, surface finish 

Low CTE substrate 

• Assembly characterization, reliability assessment and failure analysis results 

Assembly process and characterization of underfill material 

Reliability test results 

Failure analysis results 

Slide 11


Thanks for your attention 

Slide 12

Fine Pitch Flip Chip with Cu Pillar

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