mid-end - I-Micronews

3D 

ISSUE N°18 

February 2011 

Packaging 

Magazine on 3D-IC, TSV, WLP & Embedded die Technologies 

Printed on recycled paper - (Courtesy of Silex Microsystems) 

FEATURE STORIES 

Equipment & 

Materials for 

Wafer-Level-Packaging 

ANALYST CORNER 

Welcome 

to the ‘mid-end’ 

COMPANY INSIGHT 

3D TSV interposer 

packaging by 

STATS ChipPAC 

F r e e r e g i s t r a t i o n o n www.i-micronews.com

WET DEPOSITION 

Superior quality. Lower costs. 

Shorter time to market. 

Alchimer is a recognized provider of nanometric films for a variety of 

microelectronic and MEMS applications, including TSVs for 3D packaging 

and wafer-level interconnects. 

Our wet deposition technology cuts costs by nearly 80 percent 

compared to dry processes, while delivering superior film quality and 

shortening time to market. 

Contact us to learn how our products deliver a combination of conformality, 

step coverage and purity that cannot be matched by dry processes. 

We’ll also explain how we can certify new and existing 

wet-processing equipment, or provide you with 

Alchimer-approved tools and tool suppliers. 

alchimer.com 

MOLECULES TO BUILD ON

F e b r u a r y 2 0 1 1 I S S U E N ° 1 8 

E D I T O R I A L 

Advanced Packaging, 2011 expectations 

...As the CMOS industry 

is transitioning to 

32nm and 28nm, wafer 

bumping is becoming a 

key factor and 

an important part 

of the supply chain… 

Dear readers, 2011 has just started and already appears to be promising dynamic 

year. I just recently joined Yole Développement Advanced Packaging team after 

several years with TriQuint semiconductor, STMicroelectronics and CEA-LETI. 

More recently, I was developing thin film wafer level packaging and flip-chip technology for 

SAW filters. Of course, most of the industry is focused on 3D integration with TSV and 

especially the new architectures for the new generation of application processors (the “Wide 

I/O interface”), but there are lots of initiatives in others domains, like RF-SiP. Being more 

focused now on the “big” picture of the packaging industry, it is really interesting to follow the 

evolution of the supply chain and how the value is going to be redistributed. By end of 2010, 

the first 3D with TSV product announcements have been made (Xilinx and Samsung) and 

2011 is poised to be a key year for the technology maturation. 

This February issue of the 3D Packaging Magazine will focus on the equipment and materials 

manufacturers, and the on-going developments in the “mid-end” infrastructure. 3D TSV, 

interposers, FO-WLP or embedded dies are shaking the classical supply chain. At Yole 

Développement, we are focused on those new technologies and our role is to understand and 

anticipate those changes. For 2011, Yole Développement will release new reports about “3D 

IC material and equipment” and “Flip-Chip technology”. The Flip-Chip report will expand our 

vision of the advanced packaging supply chain and market, while filling the void in our report 

offerings regarding Wafer Scale Packaging Platforms. It is important for us to understand 

the Flip-Chip technology and challenges especially as the CMOS industry is transitioning to 

32nm and 28nm, wafer bumping (notably lead-free and Cu pillar bumps) is becoming a key 

factor and an important part of the supply chain. We are seeing important investments from 

the CMOS foundries and the OSAT in order to support this transition. We are following the 

main players and their capabilities/capacities worldwide. 

Regarding emerging technologies, like FO-WLP, we are tracking the evolution of the 

technology (multiple dies, etc…) and the evolution of the manufacturing (transition to panel). 

The market share of such technology will be highly depending of the infrastructure readiness 

and the capabilities of the technology (especially die size and multiple dies). 

I hope this issue of 3D Packaging provides new and important information to help you stay 

informed about this very dynamic market place. 

e v e n t s 

• IMAPS - Int. Conf. & Exhibition on Device 

Packaging 

March 8 to 10, 2011 – Scottsdale, AZ 

• DATE 2011 

March 14 to 18, 2011 - Grenoble, France 

• Semicon China 

March 15 to 17, 2011 – Shanghai, China 

Dr Christophe Zinck 

Project Manager, Advanced Packaging, 

Yole Développement 

zinck@yole.fr 

platinum partners: 

3 D P a c k a g i n g 3 

For more information, please contact S. Leroy (leroy@yole.fr) or B. Stinson (stinson@i-micronews.com)


C O N T E N T S 

Feature Stories – Equipment & Materials 6 

Industry Review: 3DICs bring opportunities, challenges 

Yole Asks: 

• Alchimer on 3D interconnects 

• Brewer Science, Inc. leading the world in thin wafer handling solutions 

• 3DICs test & metrology: status of the development by FOGALE nanotech 

• An interview with Electronics Materials Authority Leo Linehan 

• Packaging wafers for MEMS and LED by Plan Optik 

Analyst Corner: Welcome to the ‘mid-end’ 

Company insight 26 

eSilicon: The turning point for MCMs 

STATS ChipPAC: Challenges and opportunity in 3D TSV interposer packaging 

Notes from Yole Développement 31 

Standardization initiatives for 3DICs 

Yole Asks 32 

IPDiA’s value proposition for interposer products 

What’s Inside? 34 

SystemPlus Consulting: Silex TSV in MEMS oscillator from Discera 

Event Review 36 

From i-Micronews.com 

Stay connected with your peers 

on i-Micronews.com 

W i t h 1 8 , 0 0 0 m o n t h l y v i s i t o r s , 

i-Micronews.com provides for Advanced 

Packaging area: current news, market 

& technological analysis, key leader 

interviews, webcasts section, reverse 

engineering / costing, events calendar, 

latest reports … 

Please visit our website to discover the 

last top stories in Advanced Packaging: 

• Micron reveals “Hyper Memory Cube” 

3DIC Technology 

• SPTS wins new 300mm PVD order from 

CEA-Leti 

• SemiLEDs subsidiar y Helios Crew 

launches HB-LED using MEMS silicon 

wafer-level-packaging 

• 3D Integration Entering 2011 

gold partners: 

For more information, please contact S. Leroy (leroy@yole.fr) or B. Stinson (stinson@i-micronews.com) 

4 3 D P a c k a g i n g

Highlights 

• 41 sessions, 36 technical sessions, including 4 poster sessions 

and a student poster session 

• 16 CEU-approved professional development courses 

• Technology Corner Exhibits, featuring approximately 

70 industry-leading vendors 

• 8 Technical Sessions covering all aspects of 3D/TSV 

• Panel Discussion – ECTC Spotlight on China 

• Plenary Session – Power Efficiency Challenges and Solutions: 

From Outer Space to Inside the Human Body 

• CPMT Seminar – Printed Devices and Large Area 

Interconnect Technologies for New Electronics 

• Special Tuesday Session – The Impact of Manufacturing 

Limitations on Electronic Packaging Performance and 

Reliability 

More than 

300 technical papers 

covering: 

Advanced Packaging 

Modeling & Simulation 

Optoelectronics 

Interconnections 

Materials & Processing 

Applied Reliability 

Assembly & Manufacturing Technology 

Electronic Components & RF 

Emerging Technologies 

Conference Sponsors:


F e a t u r e S t o r i e s – E q u i p m e n t & M a t e r i a l s 

Thin Si Wafer on Carrier (Courtesy of EVGroup) 

3DICs bring opportunities, challenges 

There certainly isn’t a ‘one-size-fits-all’ approach to 3DICs, but it’s a huge business 

opportunity with the potential to dramatically shake things up in the semiconductor 

industry. 

Only a few years ago, the semiconductor industry 

was still debating whether or not 3DICs would ever 

really take off. But the industry quickly accepted 3D 

as a viable path forward—aggressively pursuing it, 

finding ways to remove the hurdles, work with the 

technology, and actually implement it. 

Moving forward, many key decisions must be made 

and, as always, there will be more challenges to 

maneuver around. Confusion still surrounds the 

emerging ‘mid-end’ area in wafer processing, and 

the lack of standardization is also a concern for 

many. This time around, the changes aren’t just in 

technology: We’re already starting to see signs that 

equipment makers will be affected by consolidation. 

And since materials will play a pivotal role in the 

future of 3DICs and other wafer-level packages, it’s 

a good time to also take a look at what’s going on 

there and see where they’re headed. 

Emerging ‘mid-end’ 

With a convergence of front-end and back-end 

companies pursuing opportunities in the confusing 

zone of overlap in wafer-level packaging between the 

back-end-of-line (BEOL) and back-end packaging, 

the term ‘mid-end’ is now being used to describe 

it. This includes not only 3DICs with TSVs, but also 

fan-in wafer-level packages, fan-out wafer-level 

packages (FOWLP), flip chips, and embedded die. 

Not everyone is happy with the usage of this term, 

however, because they still see distinctly different 

companies with different business models and believe 

that front-end equipment manufacturers’ move into 

the back-end has less to do with 3D technology and 

more to do with a lack of opportunities in the frontend. 

Regardless, the term ‘mid-end’ is likely to stick and 

gain traction to describe this zone of overlap, as 

many companies are seeing this convergence. 

6 

3 D P a c k a g i n g

I S S U E N ° 1 8 F e b r u a r y 2 0 1 1 

“We’re seeing a convergence in the ‘mid-end’ 

of the semiconductor industry on multiple 

levels,” explains Thorsten Matthias, director 

of business development at EV Group. 

“Processes and technologies, which used to 

be purely front-end, back-end, or assembly, 

are now being moved across all areas. For 

example, in the past, oxide wafer bonding was 

primarily used for silicon-on-insulator (SOI) 

wafer manufacturing, so basically pre-frontend. 

Now it’s used for backside-illuminated 

image sensors. And it becomes even more 

difficult to distinguish between front-end, backend, 

and assembly when you create a stacked 

system such as MEMS-on-ASIC-on-logic. Also 

in the mid-end area, we have a convergence of 

industries such as VLSI-ICs, power electronics, 

compound semiconductors (CS), and MEMS. 

Vertical interconnects and vias have been used 

in CS and MEMS for many years.” 

In terms of TSVs, both IDMs and OSATs are 

pursuing various ‘mid-end’ types of structures. 

“We consider these mid-end types of structures 

to be TSVs between 100 to 200µm deep, with 

aspect ratios from 5 to 15,” says Arthur 

Keigler, chief technology officer and vice 

president of advanced technology at NEXX 

Systems. “Most of these are in the range of 100 

to 120µm deep, with an aspect ratio between 

8 to 10. Lower aspect ratio TSV is being used 

now in development mode to take advantage 

of existing tool sets by some customers, but 

we see movement to higher aspect ratios as 

process and tool sets become more affordable.” 

In plating, there are also signs of convergence, 

bridging IDM/foundry and OSAT, according 

to Steve Lerner, CEO of Alchimer SA. 

“Unfortunately, we’re not seeing it to the extent 

that it should be happening,” he notes. “Litho 

requirements are very different for each of the 

specified user segments. PCBs and LCDs tend to 

be panel-driven, while IDM/foundry and OSATs 

are solidly wafer-driven. Dry tools typically used 

in the front-end are trying to make their way 

into the OSAT arena, but we feel that approach 

is holding back progress because the OSATs 

won’t be able to afford such infrastructure.” 

The main drivers of the ‘mid-end’ in 2010 were 

flip chip and wafer-level chip-scale packaging 

(WLCSP), and it looks like fan-out wafer-level 

packaging (FOWLP) may see significant growth 

in 2011, followed by 3D TSV technologies in 

2013 and beyond. 

Front-end companies reaching 

into the back-end 

We’ve started to see many traditionally ‘frontend’ 

equipment companies start pursuing 

opportunities in what has been considered, 

until very recently, ‘back-end’ territory. 

3 D P a c k a g i n g 

For successful entrance into any market, clear 

differentiation must be established, points out 

Damo Srinivas, senior director of business 

development for Novellus’ equipment portfolio 

serving the advanced wafer-level packaging 

applications. 

“Novellus has introduced several significant 

technology advancements to aid in overcoming 

challenges associated with TSV integration, 

including robust, repeatable TSV fill, 

minimization of overburden and wafer bow, and 

mitigation of the thermomechanical stability 

issues inherent in a copper/silicon system,” 

Srinivas elaborates. “Cost, of course, has been 

a major hindrance to TSV integration, and 

minimizing process time as well as reducing 

the cost of consumables are areas Novellus 

has innovated. Clearly, with any new market 

penetration, platform manufacturability and 

reliability are key questions, and our strategy 

across our suite of 3D products has been 

to heavily leverage our production-proven 

productivity-leading front-end platforms and 

technologies, while optimizing the specific 

package for back-end integration cost and 

technology needs.” 

It’s worth noting that there’s a significant 

difference in how work is performed in the 

front-end vs. back-end. The back-end has 

a much greater cost sensitivity and cost 

pressures. “You’re forced to take the cost out 

of processes very aggressively in the backend, 

while in the front-end it’s more about 

ensuring processes work and guaranteeing the 

processes and supporting customers with any 

issues they may have,” notes Wilfried Bair, 

SUSS MicroTec’s vice president of strategic 

business development. 

The 3DIC market shows the greatest 

potential for significant future growth in the 

semiconductor industry. It’s a huge business 

opportunity, as Bair explains. “How often 

does a business opportunity to do something 

fundamentally different come along in this 

industry? The 3D technology is fundamentally 

changing how processing is done and offers the 

opportunity for new equipment modifications,” 

he says. “Large equipment makers like Applied 

or TEL and others in that category or size 

typically aren’t interested in anything with 

$100-150M equipment revenue, but the 3D 

market promises at least several hundred 

million for each new product type—so it’s of 

great interest.” 

Materials development for 3DICs 

and other wafer-level packages 

Materials will continue to play a pivotal role in 

the evolution of 3DICs and other wafer-level 

packages. The good news for materials is, as 

Phil Garrou, an industry consultant through 

his company Microelectronic Consultants of NC, 

and also a senior analyst for Yole, puts it: The 

process options have narrowed considerably 

since 2008, so basically now we’re looking at 

‘via-middle’ processes coming from the fabs 

and ‘backside via-last’ most likely coming from 

the OSATs, when just two years ago there 

were more than 10 process sequences all in 

contention. 

Along with technical challenges ahead, there 

are many other nontechnical, market-driven 

issues that need to be addressed, according 

to JSR Micro’s Mark Davis, product manager 

for packaging materials, and Jim Chung, 

program manager in emerging technologies. 

They point out that unlike FEOL processes, 

for which consortia or alliances pull resources 

together to solve technical challenges and 

set process development directions, the ‘midend’ 

market is much more fragmented and 

lacks the needed infrastructure. The result is 

smaller, individual companies tackling technical 

problems independently rather than working 

together using common platforms, and the 

result is unintentional perpetuation of market 

fragmentation. 

Not surprisingly, materials are viewed as an 

area with great potential for breakthroughs. 

“Users are tired of upgrading equipment with 

each new generation of products,” says Lerner. 

“Material scientists have the opportunity to 

create scalable materials that can serve the 

Cu Pillars RDL SnAg micro-bumps 

More and more key back-end realizations are happening at the wafer-level (Courtesy of Novellus) 

7


Wafer / Panel Molding 

equipments 

Equipment & Materials Tool-Box 

for 2 nd generation FO WLP manufacturing 

Wafer to Wafer Bonding 

equipment for 3D stacking 

of epoxy wafers 

Temporary Bonding / De- 

Bonding Handling solution 

(equipment & material) 

Adhesive material 

(Printable paste, 

die-attach film) 

Yole Developpement 

© January 2011 

Mold compound 

Encapsulant 

Exposure & Lithography 

(Mask aligners, steppers, LDI…) 

Spin coating 

Plasma cleaning 

(descum, stress relief…) 

Wafer test & 

Functional test 

RDL & Bump 

inspection 

Chip to foil / Die to 

Panel placement 

Low-temperature 

seed / 

metallizations 

(PVD / PECVD) 

Dielectric passivation 

materials (photo-resists, 

PCB build-up) 

Specific chemistries for: 

TMV Electroplating 

Surface treatment for better 

adhesion of polymer layers 

Extracted from Yole Développement’s 2011 report on “Equipment & Materials for the Wafer-Level-Packages” 

industry through several generations of design, on 

the same equipment platform. This adds value to 

the industry in terms of both cost and environmental 

impact.” 

New materials are under investigation for TSVs, 

notes Srinivas. “However, copper electroplating 

appears to be the front-runner for the fill, and PVD 

seems to be the process of choice for barrier/seed, 

both of which are already production proven for 

front-end applications, and which together tackle 

several of the known TSV integration issues such as 

thermomechanical robustness,” he adds. 

From Davis and Chung’s perspective, examples 

of ‘mid-end’ materials on the horizon that require 

further development involve barrier materials such 

as ultrathin barrier layers and thermally stable 

organic self-assembled barrier materials. They also 

believe that interlayer dielectric materials such as 

ultralow-k materials and air gaps need work. And for 

interconnect conducting materials they expect to see 

novel polymers, carbon nanotubes, graphene, and 

nanosolders emerge. For encapsulation materials, 

they say that desirable qualities include: low CTE, 

low modulus, high electrical resistivity, high thermal 

conductivity, high moisture resistance, and high 

adhesion to materials. 

Henkel Electronic Materials LLC is also focusing on 

several areas for the ‘mid-end,’ including advanced 

underfill solutions for TSVs and other advanced 

flip chip packages or bumped dies, according to 

Kevin Becker, Henkel’s director of technology. 

“This includes all kinds of pre-applied underfills, 

nonconductive pastes, nonconductive films, and 

wafer-applied underfill,” he says. 

One of the biggest challenges Becker sees is that 

the overall assembly process flow has yet to be 

determined; it isn’t standardized or even determined 

yet. “For materials pre-applied to the wafer, this is 

a huge challenge for us. At what point it’s applied 

and what processing is done to the wafer after our 

material is applied really determines the material 

requirements,” he explains. “Process dictates material 

properties. For example, the composition of the bond 

pads on either side of the substrate or on top of the 

bottom die in the stack will have a big impact on the 

material properties required for the underfill, whether 

it needs to be fluxing, how quickly it needs to cure. 

The bonding process will also dictate that, whether 

they’re going to use thermal compression bonding, 

gravity reflow, ultrasonic, or something else.” 

Henkel is heavily involved with materials for 

FOWLPs, such as Infineon’s embedded wafer-level 

ball grid array (eWLB) technology. “Compression 

molding is being used to make ‘virtual’ wafers, 

reconstituted wafers, which is a new process to the 

market,” explains Becker. “A lot of work is done on 

these molded wafers. It’s a somewhat immature 

technology; it’s changing very quickly, so the 

requirements for compression molding materials are 

also changing. The key challenge here, whether it’s 

a substrateless package, compression molding for 

chip-on-wafer, or other package types, is to manage 

the warpage. Molding a 12-inch ultrathin wafer that’s 

asymmetric and getting near zero warpage to enable 

a dicing process, redistribution process, or stacking 

process, is the biggest challenge for that particular 

type of package.” 

And yes, Becker sees materials that still need to be 

developed for 3DICs. He cites underfills, nanofillers, 

and backgrinding as being technologies that aren’t 

quite ready yet. “There are many temporary bonding 

requirements for TSV packages, particularly to enable 

mounting of the wafer for various processing, then 

8 



easy release afterward,” he says. “I’m sure there are 

other issues as well, but the underfill solution and 

all of the various temporary bonding adhesives for 

backgrinding through dicing and other wafer-level 

processing still aren’t there yet.” 

Some established companies have the size and 

infrastructure to support big customers. When new 

technologies come up, it may not always come from 

those large established companies, so they buy the 

technology and try to force consolidation. 

As far as where materials are heading, Becker 

believes that graphene certainly has great properties 

and won’t be surprised to see big innovations come 

out of the technology within the next 3 to 5 years. 

He also expects innovations in cure latency and 

nanomaterials. Thermal conductivity is another big 

issue in 3DICs, particularly if there’s any power or 

logic involved, so he hopes to see big innovations in 

these and other areas as well. 

Standardization 

Many in the industry had hoped to see more 

processes standardized by now. 

There are many reasons for the delay, but as Bair 

notes: One is that industry goals, such as those for 

TSV diameter, were initially in terms of 15, 20, 25µm, 

but R&D groups moved ahead very aggressively 

to shrink them to 10µm or smaller. In doing so, 

standardization was delayed. “But it brings the 

advantages of 3D to products much sooner, because 

the smaller vias have less impact on the die area. In 

terms of thin wafer handling and temporary bonding, 

there wasn’t an expectation that standardization 

would occur by now; it’s still a work in progress,” he 

explains. 

But with all of the announcements about bringing 

3DICs to market lately, the lack of standardization 

in terms of equipment and processes at this point 

is surprising. “It seems like there should be more 

maturity in the infrastructure,” says Becker. 

Everyone seems to agree that standardization is 

still a ways out. “We still have a long way to go in 

regard to standardized processes. The 3D pioneers 

use a wide variety of integration concepts, process 

flows, equipment configurations, processes, and 

materials. SEMI recently formed a 3DS-IC standards 

committee, with task forces for bonded wafer stacks, 

inspection and metrology, and thin wafer handling,” 

Matthias says. 

Garrou believes that when major players such as 

TSMC and Samsung, who are in process qualification 

with their major customers right now, are finished 

and release their ground rules, it will generate the 

materials requirements the industry is searching for 

in terms of standardization. 

Consolidation ahead 

Consolidation is common in semiconductor equipment 

companies and we’ve already seen some evidence 

of this in the 3DIC arena, namely Applied Materials’ 

acquisition of Semitool at the end of 2009. 


“Another reason behind consolidation is frequently 

pressure from markets. For any major investment 

into equipment, customers want to ensure that the 

supplier has the short-term and long-term capability 

to support the installed base and can also ramp the 

production volumes quickly enough,” explains Bair. 

“And if you take a look at the number of foundries 

able to process new technology, it’s constantly 

shrinking—and they tend to want large equipment 

companies to work with and support them.” 

Sally Cole Johnson for Yole Développement 

Thorsten Matthias is director 

of business development at 

EV Group headquarters in St. 

Florian, Austria. In this role he is 

responsible for overseeing EVG’s 

worldwide business development. 

Matthias received his PhD in technical physics in 

2002 from Vienna University of Technology. In his 

current role, he works in 3D integration, MEMS, 

LED, and nanotechnology. 

Steve Lerner is CEO of Alchimer 

SA, and a 30-year semiconductor 

industry veteran, most notably 

fostering emerging technologies 

in first level interconnects. He has 

held executive positions at startups 

Alpha Szenszor, GigaSys, CS2, 

and contractors Amkor, Swire, and IMI. 

Damo Srinivas is senior director of 

business development for Novellus’ 

equipment portfolio serving the 

advanced wafer-level packaging 

applications. He received his MS 

degree in materials science from 

Arizona State University, and a BS degree in 

metallurgical engineering from the Indian Institute 

of Technology. 

Wilfried Bair is SUSS MicroTec’s 

vice president of strategic business 

development. He is responsible for 

developing emerging market and 

business opportunities as well as 

strategic alliances for SUSS. With 

many years of experience working 

in 3D technologies and applications, he is focusing 

on SUSS’ 3D packaging and 3D integration 

product portfolio. Bair is also the general manager 

of SUSS’ US organization. 

Mark Davis is a product manager 

for packaging materials at JSR 

Micro. He has 20 years’ experience 

in the semiconductor industry in 

field applications engineering, 

sales, marketing, and product 

management. 

Phil Garrou is a consultant 

in the areas of electronic 

materials, IC packaging, and 3D 

integration through his company 

Microelectronic Consultants of 

NC, and a senior analyst for 

Yole. Garrou was previously the 

global director of technology and new business 

development and new business development for 

Dow Chemical’s Electronic Business Unit. He is a 

fellow of both IEEE and IMAPS, and has served 

as president of the IEEE CPMT (2003-2005) and 

IMAPS (1997). 

James Chung is a program manager 

in emerging technologies at JSR 

Micro. He holds a BS in chemical 

engineering from the University of 

Illinois at Urbana-Champaign and 

a PhD in physical chemistry from 

UCLA. Chung has worked at Intel 

in lithography development and at Cheil Industries 

(Samsung) in marketing. 

Kevin Becker is director of 

technology at Henkel Electronic 

Materials, LLC, and heads the 

Advanced Materials Group as well 

as the Film Adhesives Development 

Group. He joined Henkel in 1999 

and has been responsible for 

developing and launching several new product 

lines. Most recently he has overseen Henkel’s 

launch of the new non-conductive paste preapplied 

underfill for fine-pitch copper-pillar-based 

applications processors. 

Arthur Keigler is chief technology officer, 

vice president of advanced technology at 

NEXX Systems. He has more than 20 years’ 

experience in wafer processing, and holds an 

MS in materials science and engineering from 

MIT, as well as a BS in applied and engineering 

physics from Cornell. Keigler was also a Leaders 

for Manufacturing Fellow at MIT, earning an MS in 

mechanical engineering. He holds several patents 

in the field of wafer processing equipment. 

9



Alchimer on 3D interconnects 

CTO Claudio Truzzi discusses the company’s ‘nanotechnology engine’ and low-capex 

wet process technology. 

Claudio Truzzi, 

CTO, Alchimer 

Yole Développement: What is the Business 

model of Alchimer in the 3D Packaging space? 

Claudio Truzzi: Alchimer is offering high 

density integration solutions across the entire 3D 

interconnect space, starting with high-density 

substrates, flexible circuits, BT, LTCC, and right 

on through the TSV stack, including isolation, 

barrier, seed (if required), and fill. Our films are 

sufficiently flexible to address the EMS, OSAT and 

IDM/Foundry levels of material processing. 

YD: Could you comment about your recent 

partnership announcements in Korea and 

Japan? 

CT: One of Alchimer’s main missions, at this stage 

of our growth, is to demonstrate the benefits of 

our films in a way that’s regionally and culturally 

accessible to our customers. Every substrate 

and every design rule is customer-specific, and 

deposition processes and materials have to be 

tuned to maximize their cost-performance ratio 

before integration at the customer site. That’s why 

these announcements in Korea and Japan are so 

important – they are key to creating the necessary 

site synergy in the electronic manufacturing world’s 

most strategic regions. We will also be announcing 

similar sites in North America and Taiwan, where 

customers can utilize local development sites to 

tailor our films to their specific needs. 

YD: Who is driving the development of 3D 

TSV via filling based on Electrografting 

technology? 

CT: As with all of our products, the market is 

driving our via-fill efforts. Originally, Alchimer did 

not plan to be in the fill business, as there are so 

many competitors. But it became obvious that fill is 

a huge bottleneck in many respects. For instance, 

Cu Seed 

Isolation 

purity levels on Cu fill really need to improve to 

maximize reliability. Also, the standard group of fill 

chemistry suppliers really wasn’t addressing finepitch, 

deep-access, bottom-up capabilities. We 

feel that by providing clear differentiating products 

to address these areas, we can help designers 

maximize their real estate and more easily justify 

the move to TSV. 

YD: What type of equipment can be used to 

apply the eG and cG technologies? 

CT: Most standard electrolytic and electroless 

equipment can be tuned to run our Electrografting 

and Chemicalgrafting processes, respectively. The 

customer has three options for integrating our 

films into a production line: 

1. Certified legacy equipment, which a customer 

might already own; 

2. Inexpensive wet benches and stand-alone ECD 

tools, and, 

3. Fully automated systems that combine isolation, 

barrier, seed and fill, including cleaning, prewetting, 

annealing, and other ancillary functions 

in one tool with cassette-in, cassette-out material 

handling. 

This hardware flexibility is one of the most 

revolutionary aspects of our technology. 

Traditionally, tools have had the leading role in 

semiconductor fabs - processes have been toolspecific, 

and materials generic. This commonly 

accepted approach has brought our industry to 

its current juncture, where over-inflated capex 

investments are considered a necessary evil. 

Alchimer’s wet technology breaks this concept 

apart: our unique materials and processes go 

hand in hand and are the key to delivering superior 

performance for TSV lining and filling. The tool 

becomes a mere delivery mechanism, and not a 

profit center. This is the essence of how we are 

able to provide 60% cost of ownership reduction 

in the TSV manufacturing flow (drill, line, fill, CMP). 

Barrier 

Barrier 

SI 

Isolation 

SI 

Top view of a full isolation/ barrier/seed stack on TSV 

using wet-deposition technology (Courtesy of Alchimer) 

Highly conformal wet Isolation and Barrier 

layers on a 4-µm TSV (Courtesy of Alchimer) 

10 



YD: Yole Développement recently observed 

that two types of 3D Glass & Silicon 

interposers are emerging: one type of 

interposer is “Front-end” oriented, with 

small Vias diameters, manufactured in 

the CMOS wafer foundry environment. 

The second type of interposers is more 

“Back-end”, with thicker vias, bigger 

volume to plate, higher aspect ratios: 

could you comment on the benefits eG 

technology can bring in such two distinct 

types of interposer environments? 

CT: Alchimer’s TSV technology is applicationagnostic. 

This stems directly from our 

basic nanotechnology engine: our films are 

chemically bonded onto the wafer and grow 

from the surface out, rather than being 

deposited onto it. As a direct consequence, 

conformality, adhesion and uniformity are 

integral to the film layers we produce, and 

are not a function of surface topography or 

tool performance. We can graft our films 

on 1-micron diameter vias as easily as 

200-micron vias, with aspect ratios as high 

as 30:1. 

So, whether your interposer is front-end or 

back-end oriented, glass or silicon-based, 

you benefit from the excellent step coverage 

and adhesion, lower parasitic capacitance, 

higher breakdown voltage, and reduced wafer 

bulk stress and copper pumping. And from 

an integration perspective, Alchimer’s wet 

technology is fully compatible with standard 

fab safety and environmental requirements 

for handling and waste treatment. 

Cu 

Barrier 

Isolation 

Si 

Top and bottom view 

of a wet-processed, 

seedless 3X30 µm 

Cu-filled TSV. 

Wet isolation 

thickness: 

top = 80nm; 

bottom = 60nm 

Wet barrier 

thickness: 

top = 50nm; 

bottom = 35nm 

Step coverage >70% 

(Courtesy of Alchimer) 

YD: According to you, who is the best 

3DIC builder: CMOS foundries, OSATs, 

MEMS players, PCB substrate houses? 

CT: It depends. We’re using a single term, 

3DIC, to indicate very different applications 

and technology variations; this often happens 

in the early stages of process revolutions. 

Today we are seeing more-articulated 3DIC 

technology diversification, compared to just 

a few years ago, with different options being 

selected for different applications. Vertical 

connections and chip-stacking requirements 

for some applications, such as MEMS devices, 

are different from those for memory-on-logic 

or for memory stacks. 

The point at which the TSV wafer leaves the 

fab is a key differentiating factor that can 

help categorize the current multitude of 3DIC 

process flows. Once that wafer leaves the 

fab, it will almost certainly never go back. 

The number and type of steps the wafer 

still needs to undergo after that point (in 

the post-fab portion of the process flow) are 

determined by the application. 


For a single-device memory stack, the postfab 

portion is minimal - the fab will own the 

majority of the 3DIC flow. For an interposer 

with a memory stack on one side and a 

microprocessor on the other, the post-fab 

portion may be considerably larger and OSATs 

have the opportunity to own a larger portion 

of the flow. It’s worth noting that the current 

capex and dry-process know-how required for a 

full 3DIC line may represent a major barrier to 

entry for OSATs. Alchimer’s solution, based on 

low-capex wet process technology, can address 

that. 

www.alchimer.com 

Claudio Truzzi, CTO, Alchimer 

CTO Claudio Truzzi joined Alchimer with more 

than 20 years of experience in R&D, engineering, 

manufacturing, and product development in the 

microelectronics industry. His expertise encompasses 

molecular engineering, 3D-IC process flows, 

IC design, microelectronic packaging, MEMS 

and bio-electronic components, box build, wireless 

systems and hardware/software integration. 

Claudio’s achievements include development 

of miniature high-performance electronic 

systems for wireless and industrial applications, 

high-frequency packaging, antennas and filters, 

and wireless sensor networks. 

Earlier in his career he consulted with 

electronic-manufacturing services companies, 

semiconductor equipment manufacturers, waferlevel 

process developers, and optoelectronics 

companies. He also has held senior management 

positions at Convergix and CS2 in Europe. 

Widely published in scientific journals and conference 

proceedings, Claudio has an M.S. degree in 

electronic engineering from the University of Bologna 

and a Ph.D. degree in electronic engineering from the 

University of Torino. 

11



Brewer Science, Inc. leading 

the world in thin wafer handling 

solutions 

Dan Wallace 

Director of Advanced 

Packaging SBU 

Brewer Science Inc. 

Yole Développement: Dan, you started with 

Brewer Science in 2008. How about a little 

background on what you were doing before 

you joined Brewer Science and what your 

current role there is? 

Dan Wallace: I started in the industry in 1981, 

so I certainly have seen many advancements. 

Most of my career was with Motorola, and I later 

moved to Freescale Semiconductor when Motorola 

spun off their semiconductor products group. With 

Motorola and Freescale I was involved in a broad 

range of positions such as R&D, manufacturing, 

product management, marketing, and business 

management. When I left Freescale to join Brewer 

Science, I was the operations manager for the 

MEMS Pressure Sensor Business Unit. 

Now in my position at Brewer Science as the 

Director of the Advanced Packaging Business Unit, 

I find that this experience has given me a unique 

vantage point in understanding many of the 

challenges our customers face. 

YD: Brewer Science, Inc., is a 30-year-old 

company with headquarters in Rolla, Missouri. 

Can you give us a little background on how the 

company started? 

DW: Brewer Science is a privately held specialty 

chemical company founded in 1981 by Dr. Terry 

Brewer and headquartered in Rolla, Missouri. 

Brewer Science delivers materials, processes, and 

equipment for applications in semiconductors, 

advanced packaging/3-D ICs, MEMS, displays, LEDs, 

and printed electronics. 

Everything about the company is unique, from the 

fact that it’s a high-tech company located in rural 

Rolla, Missouri, to its 30-year history of consistent 

and successful global growth. Brewer Science’s 

open-minded approach to customer needs and indepth 

knowledge of process technologies has helped 

it to grow to be a global company with employees 

and offices in Asia, Europe, and North America 

supporting a worldwide customer base. 

The company’s vision and commitment is focused 

on introducing innovative technology solutions for 

the ever changing needs of the microelectronics 

industry. 

YD: We have seen that Brewer Science 

recently opened new offices in Tokyo, Japan, 

and Seoul, Korea, to go along with offices in 

Taipei, Shanghai, and Hong Kong. Are these 

sales offices? How do you handle “field 

engineering” for customers? Do you have 

engineers stationed in Asia? Or are technical 

issues dealt with from the US? 

DW: Brewer Science is purposefully executing 

a long-term strategy of developing more local 

support in the regions where we continue to see 

growth. The type of support will depend upon the 

needs of that specific region, although in most 

cases we are installing sales and some level of field 

applications support with US applications always 

very much involved. It would be important to note 

that Brewer Science has made a considerable 

investment in Taiwan by opening up an applications 

lab in early 2009. Already the size of the lab has 

doubled, and it continues to install equipment in 

support of Brewer Science products. As of today, 

the Taiwan lab is supporting a significant portion of 

our applications work in Asia. 

Thin Wafer BSI (Courtesy of Brewer Science) 

YD: A little introduction to your main product 

lines is probably in order. Brewer Science 

is probably best known for its ARC ® antireflective 

coating products used in the 

microlithography world. Please give us a bit 

of a description of your main product families. 

DW: After inventing anti-reflective coatings 30 years 

ago in 1981, Brewer Science’s continuing approach is 

to create and deliver innovative, originally developed 

materials and process solutions that enable a 

variety of microelectronic processes and allow a 

competitive edge for our customers. We make a 

significant investment in R&D, which is apparent 

12 



Latest Solution - ZoneBOND 

Room temperature debond process 

(Courtesy of Brewer Science) 

Device 

Carrier 

1 

2 

Adhesive on Device 

3 

Device 

Polymer Adhesive 

Carrier 

4 

ZB Carrier 

Release Zone 

Stiction Zone 

Thin Device 

Basic Process Flow: 

1. Coat polymer adhesive on Device 

2. Create carrier: (Release Zone & Stiction Zone) 

3. Bond face to face 

4. User processes, thin, pattern, etc. 

5. Remove stiction zone adhesive 

6. Mount device wafer to film frame & vacuum 

chuck - Peel Carrier from adhesive 

7. Clean adhesive from Device while on film frame 

5 

6 

7 

given the leadership role we play in the industry. 

Brewer Science has commercial products and 

developmental activities focused in the areas 

of lithography, LEDs, solar applications, 

MEMS, carbon nanotubes, printable/flexible 

electronics, and advanced packaging. As 

far as specific products, Brewer Science 

continues to expand its scope with CNTRENE ® 

microelectronics-grade carbon nanotube 

solutions, ProTEK ® temporary etch protective 

coatings, WaferBOND ® temporary bonding 

materials, ZoneBOND low-temperature 

debonding system, OptiNDEX high refractive 

index coatings, and Cee ® benchtop laboratory 

processing equipment. 

I would like to mention that Brewer Science 

really identifies a product in much broader 

terms beyond a bottle of polymer or a piece 

of equipment. The value that Brewer Science 

offers is the ability to deliver solutions to the 

industry based on our 30 years of experience. 

These solutions will include not only innovative 

materials but also our equipment and process 

experience. 

YD: Certainly i-Micronews readers are 

all aware of the WaferBOND ® temporary 

bonding products. It’s been clear that 

Brewer Science was the first chemical 

company to understand the need for 

temporary adhesives. Was this the 

result of your membership in EMC-3D 

consortium in 2007 or were you aware 

of these needs earlier? 

DW: Brewer Science was aware of the coming 

opportunity much earlier and started working 

on temporary bonding in 2003. We launched 

our first temporary bonding material, a 

WaferBOND ® product, in 2006. Since that 

time we have introduced several improved 

temporary bonding materials in support of the 

high-temperature slide debonding process. 

More recently, Brewer Science has introduced 

our patented ZoneBOND technology, which 

was developed to solve many of the industry 

problems with existing thin wafer handling 

processes. 

In addition, Brewer Science has authored over 

20 publications and has been issued over 70 

US and international patents related to 3D 

technology, which has further positioned 

Brewer Science as a market leader for this 

technology. 

YD: We have heard that there are 

now several grades (differentiated by 

temperature stability and removal 

temperature) of WaferBOND ® products 

available. Can you elaborate? 

DW: I first should talk about our temperature 

ratings of materials. For lack of a better 

method, we have chosen to assign a value 

representing the temperature capability or 

tolerance of that adhesive. For example, 

we say our WaferBOND ® HT10.10 product 

is a 220°C material. This description is very 

general because the overall capability of the 

material is dependent on not only the backend 

processing temperatures but also on 

many other factors that influence how well 

the material will perform during back-end 

processing. These factors include time at 

temperature, the presence of a vacuum or 

pressure environment, energy level such as 

in a PECVD process, and the degree of wafer 

stress at elevated temperature. Depending 

on these factors we have seen WaferBOND ® 

HT10.10 material performs well at 250°C and 

in other cases fails at 200°C. Our development 

efforts have taught us that all related process 

factors must be well understood. 

WaferBOND ® HT10.10 material is our current 

commercially released product. At the same 

time, we are also working on several new 

advanced platforms of adhesives targeted for 

temperature capabilities of up to 300°C. We 

have chosen to work with key customers in 

the development of these materials to ensure 

our developmental goals align well with our 

customers’ needs. 

YD: Since the 3D IC market has been 

“coming soon” for a few years now, how 

does a moderate-sized company such as 

Brewer Science decide on the appropriate 

investment level for such leading-edge 

technology developments? Did you get in 

too early? or was your timing just right? 

DW: Your question is a very interesting one, 

and I am sure on where every company has 

experienced both scenarios. If we could 

accurately predict when a new technology such 


13


as 3D IC may launch, we would rule the world. 

More often, that is not the case. It is Brewer 

Science’s focus to invent and provide cuttingedge 

technology solutions, and entering the 

3D IC market was a result of following this 

approach. Some of our methods may be 

more confidential in nature, but, in general, 

to aid in reducing the risk, we work closely 

with key suppliers and customers throughout 

the supply chain. These relationships have 

been instrumental in helping Brewer Science 

to determine the level of investment versus 

when a new technology may launch. Entering 

as early as we did has helped us in developing 

broader relationships in the industry and in 

understanding the applications much better 

than any of our competition. In that respect, I 

believe our timing was just right. 

YD: Does being a mid-sized chemical 

company give you any advantages over 

the “big boys”? 

DW: I find that, overall, we move faster. 

Communication is much easier because 90% 

of the company is within the same campus, 

so most of our colleagues are a 5-minute 

walk away. In addition, our processes foster 

close connections with our global employees. 

Usually decisions are made in hours rather 

than weeks or months. Our customers also 

recognized that because we are a midsized 

company we have greater flexibility in 

responding to their current technology needs 

and developing innovation that will address 

future challenges. 

YD: Since most 3D customers clearly 

want an “equipment + materials” tested 

solution for their thin wafer handling 

needs, your relationship with EVG has 

certainly helped introduce your material 

solutions to the industry. How has that 

developed through the years? 

DW: Brewer Science and EV Group 

early on recognized that the solution for 

temporary wafer bonding will not be just 

material or equipment alone, but it will be 

the combination of both working together. 

Given this, we have made much progress 

over the years advancing the development 

of temporary bonding technology. Now as 

the industry is coming closer to actually 

launching 3D IC technology, it is key for 

the market to have multiple suppliers in 

order to meet the demand and continue 

innovation. Thus Brewer Science continues 

to work with EV Group in the marketing of 

high-temperature slide debonding equipment 

and materials, but we are also pursuing a 

non-exclusive path with multiple equipment 

suppliers on newer technology, such as the 

Brewer Science ZoneBOND process. 

YD: We’ve seen recently that Suss Microtec 

is also offering a “WaferBONDlike” solution 

for its bonder/debonder equipment line. 

Care to discuss your relationship with 

Suss? 

DW: As mentioned above, we are pursuing 

a non-exclusive path with multiple equipment 

suppliers on technologies such as WaferBOND ® 

and ZoneBOND technologies. Ultimately we 

see this as the best way to serve the market 

needs and drive further innovation in both 

equipment and material development. 

YD: The EMC-3D consortium appears to 

be winding down. Care to comment on how 

membership in this consortium affected 

your overall 3D business strategy? 

DW: We benefited in several ways from the 

relationship. Certainly the combined process 

evaluation work of the membership was 

extremely beneficial. I would also say the 

work put into the CoO model was a good 

experience. Even though some of the input 

data may still need to be refined, the baseline 

model will prove to be a useful tool for the 

industry. 

YD: Being out there on the front line of 3D 

IC you certainly must have a perspective 

on how much longer it will be until we see 

real product-driven commercialization. 

What’s your best guess? 

DW: I think we all recognize from conferences 

and direct customer partnerships that we will 

see launches starting in 2012 to 2013. These 

may be slow at first while the main concerns 

are still being resolved. But as the industry 

begins to resolve the major concerns and the 

volumes help drive down the costs, I believe 

the benefits of 3D IC will drive a whole new 

market and level of performance. 

YD: We saw that you created a research 

collaboration with CEA Leti in 2009. 

What was that about, is it still in place, 

and how has that worked out? 

DW: We continue to work with Leti, with our 

efforts focused on evaluating developmental 

temporary bonding material performance 

through various backside processes and 

related process development, such as 

coating, bonding, debonding, cleaning, etc. I 

think we would all agree that the relationship 

has been very valuable. 

YD: The latest 3D based technology we 

have seen from Brewer Science is the 

“Zonebond Process.” Can you give us a 

short description and status report? 

DW: A picture is worth a thousand words. 

The scheme on the previous page describes 

the process pretty well. The motivation in 

developing a process technology such as 

ZoneBOND was driven by the desire to 

solve several key customer concerns with 

the existing thin wafer handling technologies. 

Overwhelmingly, our goal was to develop a 

solution that would offer maximum protection 

to the thinned device wafer, enable the 

use of value-added materials with a higher 

temperature tolerance, and lower the overall 

CoO by increasing throughput for both 

bonding and debonding. Based on results to 

date, I am confident that we will deliver such 

a solution. 

YD: Any other new products coming 

through the pipeline that our readers 

should be aware of? 

DW: I would love to share that information 

with you, but until we are closer to 

commercialization such activities are of a 

confidential nature. All I can say is that we 

continue to invest a significant percent of 

revenue in developmental activity aimed at 

new disruptive technologies that will enhance 

existing processes and expand capability to 

address existing and new applications for the 

microelectronics industry. 

www.brewerscience.com 

Dan Wallace 

Director of Advanced Packaging SBU Brewer 

Science Inc. 

Dan has been in the electronics industry for over 

twenty-nine years working in diverse and progressive 

roles in device design, manufacturing engineering, 

marketing and business development. His current 

focus is on material and business development for 

advanced material and process solutions in the area of 

thin wafer handling for 3DIC packaging applications. 

Dan’s background spans a broad range of 

technologies including, Power MOSFET, custom Analog 

IC’s, and MEMS products for the automotive market 

place. He has a masters in business, bachelors in 

electrical engineering and is a certified black belt in 

LEAN/Six-Sigma practices for manufacturing and 

business processes. Dan has authored several papers, 

patents and has spoken at various conferences. 




3DICs test & metrology: 

status of the development 

by FOGALE nanotech 

Yole Développement met the company FOGALE nanotech, the reference in the field 

of high accuracy dimensional metrology. Discover below the exchange between the 

consulting company and FOGALE: overview of FOGALE solutions, FOGALE’s point 

of view on the test & metrology developments, feedback on the status of the 3DICs 

industry… 

Yole Développement: Could you introduce us 

about Fogale Nanotech’s activity and company 

background? 

Gilles Fresquet: FOGALE nanotech, a company 

created in 1983, is now a worldwide known reference 

in the field of high accuracy dimensional metrology. 

FOGALE Nanotech headquarter is located in Nîmes, 

south of France, with two subsidiaries located in the 

USA and in Taiwan. 

Back in the 80’s and the 90’s, FOGALE nanotech 

provided metrology solutions for big scientific 

instruments such as Very Large Telescopes, 

nuclear reactors, particle accelerators and medical 

instruments. As an example, all the main particle 

accelerators are equipped with FOGALE sub 

micrometer leveling systems (capacitive method) 

and very large telescopes with FOGALE focus 

adjustment devices based on interferometry and 

optical techniques. Amazingly, the physics laws of 

the developed non contact metroly solutions for 

particle accelerators and very large telescopes are 

the same than the one used to monitor life cells or 

silicon wafers. So, since mid 90’s, FOGALE nanotech 

is delivering systems for the biotech, optical and 

semiconductor applications. 

With a high level of expertise in optical metrology 

and a strong scientific background, FOGALE 

nanotech provides tools well suited to new 

metrology requirements in the 3D integration and 

MEMS process control. FOGALE nanotech was the 

first company able to deliver metrology solution for 

MEMS in motion optical analysis and optical analysis 

of devices under controlled atmosphere. 

Since 2007, FOGALE R&D team is focusing on 

metrology and inspection solutions for the 3DIC & 

TSV area. 

YD: Can you comment on the recent traction you 

are seeing in the 3DIC & TSV metrology area? 

What needs to be measured and inspected for 

3DICs as of today? 

GF: FOGALE nanotech is currently involved in several 

projects concerning 3D integration. Through a joint 

development program with imec, the TSV depth 

measurement system (Deeprobe) has been qualified 

for Via first or middle process control. The goal was 

to measure the 25 to 50 µm depth of 5µm diameter 

TSV with good accuracy, linearity and repeatability. 

The Deeprobe has been lately used to measure 2µm 

diameter TSV with 1:25 Aspect Ratio on 300mm 

wafers. 

FOGALE nanotech is also involved in other projects 

concerning Via last approach for 3D integration. We 

are working with academics and industrial partners 

such as IEF (Institute of Fundamental Elelectronics 

Orsay), ST, LETI and others. The implementation 

of a common lab FOGALE-CNRS (French National 

Research and scientific Center) is ongoing. 

FOGALE is involved in the SMARTSTACK project 

(Partners: CEA LETI, ST micro, TEGAL FRANCE, 

“IDMs are very 

aggressive in the 

3DIC development 

but OSATs and 

CMOS foundries 

are not far behind, 

they want 

to be ready,” 

says Gilles Fresquet, 

FOGALE nanotech 


Fogale headquarter 

Fogale Laboratory (Courtesy of Fogale nanotech) 

15


“For all technologies, 

low cost and fast 

measurement 

methods will 

be required,” 

comments 

Gilles Fresquet 

41,4 

Die to wafer process stacking: Smartstack Project 

(Courtesy of Fogale nanotech) 

Ecoles des mines de St Etienne and GEMALTO). The 

goal of this project is to deliver a 3D platform able to 

combine several dies for several applications. 

5 major items are studied within this 3 years 

program: 

• Deep RIE process tuning to obtain optimal TSV 

structures. 

• Interconnect process for die to die and die to wafer 

connection. 

• Thinning processes for final 40 to 60 µm thick 

silicon wafers. 

• Modeling of several 3D integration schemes and 

validation by reliability test. 

• Performances study of the developed 3D modules. 

Within the smartstack project, FOGALE is in charge 

to deliverall the required in line process control 

solutions for all process steps (from TSV, thinning 

to final 3D interconnection). FOGALE is also working 

on metrology solutions for reliability studies. Thanks 

to the global approach of the smartstack project, a 

first tool has been designed and delivered for TSV 

control and wafer thinning process inspection. The 

FOGALE approach always combines microscopy and 

metrology, and this tool can also be used to monitor 

the final 3D interconnect process step. 

Today, for 3D ICs , several process steps need to be 

controlled: 

• TSV: depth, profile, liner integrity, voids after fill etc.. 

• Thinning: post bonding inspection to detect 

defects at the interface between the wafer and 

the temporary carrier, Total Thickness Variation of 

the glue layer. After back grind, apart from Silicon 

thickness which is required, edge and backside 

defects must be detected. 

• Interconnect: Non contact metrology and inspection 

solutions are required to control the interface and 

the alignment between dies and copper nails height 

and co-planarity. 

• Reliability and performance: Metrology and 

inspection solutions to avoid failures due to 

mechanical stress and environmental parameters 

and control solutions for the final package. 

YD: Could you comment on the different 

3DIC metrology & inspection methods today 

available and their related benefits (Moiré 

interferometry, X-Ray, SAM, others…)? 

GF: Several technologies can be used to control 3DIC 

process steps. 

• To measure substrate thicknesses, we can use 

capacitive or optical technologies. The advantage 

of optical technologies is the capability to measure 

multi layer substrates such as Si on temporary 

carrier. 

• For Substrate flatness, optical methods such as laser 

scanning, confocal chromatic or interferometry are 

working well. For surface roughness after thinning, 

AFM or optical techniques can be used. However 

optical techniques are preferred if a measurement 

on a large area is required. 

• For high A/R TSV, the SEM is used on cross section 

but it is a destructive method so a non contact 

measurement is required. Full field interferometry 

can be used but is limited to low A/R. Confocal and IR 

interferometry are the best candidates for high A/R 

TSV. However, after backgrind, IR interferometry is 

also able to measure Remaining Silicon Thickness 

over copper nails. For TSV characterization, the 

X-Ray tomography is the perfect solution for 

measurement on small samples. 

• For post bonding inspection, full wafer optical 

methods are working well, both in reflection or 

transmission. 

TSV depth uniformity across a 300 mm wafer (TSV diameter : 5 μm) 

Measurement done with FOGALE DeeProbe 300 (Courtesy of imec) 

41,2 

Via Depth (μm) 

41 

40,8 

40,6 

40,4 

40,2 

40 

39,8 

X position across a 300mm wafer diameter (mm) 



• For the die interconnect, the IR interferometry 

combined with NIR microscopy is a good candidate 

for in line process control. X-Ray tomography 

and acoustic microscopy are used but mainly for 

characterization. 

• For hermetic package characterization, we can 

use mass spectrometry, IR spectrometry and 

Raman spectrometry. For wafer level packaging, 

IR interferometry with NIR microscopy is a good 

non destructive solution and can be used on a full 

wafer surface. 

YD: 3DIC inspection & metrology is today 

clearly a booming area but mainly remains in 

the R&D and laboratory space. According to 

you, which inspection, metrology and testing 

steps for 3DICs may be finally integrated “inline” 

into high volume production? 

GF: I’m convinced that TSV and wafer thinning 

process control solutions will be integrated into high 

volume production. For 3D interconnect step, it will 

depend a lot on the 3D process integration approach. 

There are so many different ways to do it. 

In all cases, low cost and fast measurement methods 

will be required. We still miss versatile and fast 

solutions for in line process controls. Inspection and 

metrology on the same platform is a good approach. 

www.fogale-semicon.com 

YD: Who is the most aggressive in the 

development of test and metrology solutions 

for 3DICs based on TSV: OSATs, IDMs or CMOS 

Foundries? 

GF: FOGALE is working with all the players. IDMs are 

very aggressive in the 3DIC development but OSATs 

and CMOS foundries are not far behind, they want to 

be ready. The question about the timing depends on 

the final applications for 3DICs. 

Gilles Fresquet is the manager of the semiconductor 

business at FOGALE Nanotech. Before joining FOGALE, 

Fresquet spent many years at Thomson, Motorola 

and RECIF in a variety of process engineering and 

management roles. He hold a MSc. In Physics and has 

more than 25 years of semiconductor experience. 

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©2010 Solid State Corporation 


17



An interview with Electronics 

Materials Authority Leo Linehan 

Yole Développement’s analysts discussed with Leo Linehan, from Dow Electronics. 

Below, our Editorial Team presents you a review of this discussion. More than Dow 

Electronics solutions and added value of its technology, Leo give us its vision of the 

3D Integration industry, its technical challenges, new developments and the status 

of the market. 

Leo Linehan, 

Dow Chemical 

Yole Développement: Thanks for agreeing to 

chat with us today. Before getting to our main 

discussion points, some initial disclosure on 

your background. We understand that your 

first job was with IBM where you worked a 

decade. Can you tell us a little about your time 

there ? 

Leo Linehan: I started my career with IBM 

Microelectronics as a development engineer in their 

Packaging Thin Films line in Fishkill working on Cu- 

Polyimide process development. I then moved to 

the semiconductor side of IBM Microelectronics 

as a development engineer and then department 

manager in Lithography Materials and Process 

development. 

YD: Then you moved on to Shipley which was 

later acquired by Rohm and Haas (R&H) which 

was eventually acquired by Dow Chemical. Can 

you share with us some of your activities prior 

to the Dow acquisition ? 

LL: I moved from IBM to Shipley in 1997 to manage 

photoresist R&D. Since then I have been global 

technology director for Microelectronics, strategic 

account executive and global marketing director with 

Rohm and Haas Electronic Materials before moving 

into my current role as global business director 

running our Advanced Packaging Technologies 

(APT) business. 

YD: In 2009 Dow announced the acquisition of 

R&H which included the RHEM business (Rohm 

and Haas Electronic Materials). There was a 

lot of intrigue surrounding that acquisition 

because it was tied to Dow selling some basic 

commodity chemical businesses to the Saudis, 

which if I recall correctly fell through leaving 

questions about the viability of the R&H 

acquisition. As we all know, the deal finally 

went through propelling Dow into a major 

position in the Electronic Materials arena. Can 

you describe to us the structure of the current 

Dow electronic materials business and your 

role in it ? 

LL: Yes, 2009 was quite exciting in many ways. The 

acquisition was just one of the challenges we had 

to manage. Ultimately, 2009 proved to be a critical 

year for us. We successfully integrated Rohm and 

Haas with Dow and weathered the economic crisis, 

and we haven’t looked back since. Concurrent with 

the acquisition, we formed the business I am running 

now, Advanced Packaging Technologies, that is 

wholly focused on the rapidly growing packaging 

markets such as fine-pitch flip chip, WLCSP and 

the emerging 3D-TSV technologies. Previously, the 

advanced packaging market was being served by 

several different businesses within our Electronic 

Materials Business Group. We merged several 

product lines from Interconnect Technologies and 

Semiconductor Technologies into the new Advanced 

Packaging Technologies business, and we report up 

through the Growth Technologies business unit in 

Dow Electronic Materials. 

YD: For those who may not be aware, can you 

briefly describe what families of materials the 

Dow electronics materials business currently 

offers? and any future areas that your looking 

at. 

LL: Dow Electronic Materials is a leading 

supplier for many of the electronic industry’s 

most critical materials. Our Semiconductor 

Technologies Business suppliers CMP pads 

and slurries, advanced photoresists and antireflective 

coatings. Our Display Technologies 

business supplies light management and emissive 

films and process chemicals for LCD and OLED 

displays. Our Interconnect Technologies Business 

supplies process chemicals and plating solutions 

for circuit board and photovoltaics production as 

well as metallization and process chemicals for 

electronic finishing. Growth Technologies is a 

new business incubator and is comprised of three 

business segments. The first is my business, 

Advanced Packaging Technologies, which supplies 

bump plating chemistries, dielectric materials 

and assembly materials such as underfills and 

die attach materials. The second segment is 

Metalorganic Technologies, which supplies metalorganic 

CVD and ALD precursors for LED and 

semiconductor production. And, finally, Optical 

and Ceramic Technologies supplies silicon 

carbide for semiconductor processing equipment 

and zinc-based materials fabricated for use in 

optical systems. We are always looking for new 

opportunities for growth and we will continue to 

expand into new technologies. 



YD: Now lets look at how the electronics 

materials industry is or is not changing. 

Lets talk a little about (1) whether scaling 

is coming to an end and (2) what that 

means to the traditional microelectronic 

market segments and Dow electronics in 

particular. 

Looking at the electronic materials 

business in year 2000 we saw fab materials 

(chip fabrication) with ~ $15B in sales, 

interconnect materials (PCB related )at ~ 

$10B and packaging materials at ~ $2.5B, 

or a ratio of 6:4:1. Do you agree with some 

who forecast fewer and fewer fabs being 

built at 32 nm and below and if so how do 

you expect this to effect the electronic 

materials sales in this segment ? 

LL: Certainly economics are limiting the 

number of companies that can afford to build 

leading-edge fabs. Also, efficiencies achieved 

with scaling and the eventual construction 

of 450 mm fabs will allow a greater number 

of devices to be produced from each wafer, 

which in turn influences global demand for 

wafer production. That said, I think the 

electronic materials market supporting 

semiconductor device production will continue 

to offer attractive growth opportunities in new 

materials supporting sub-22nm production, 

such as EUV resists, double patterning 

materials, high-K gate materials and multigate 

process materials. 

YD: If you subscribe to the “more than 

Moore” philosophy, you see future 

product differentiation coming from 

packaging not from scaling. Do you agree 

with this ? Can you give some examples 

of where this may lead ? 

LL: I do subscribe to the “more than Moore” 

philosophy. Dow’s Advanced Packaging 

Technologies is driven by “more than Moore”. 

The packaging technologies that are being 

developed to enable “more than Moore” are 

opening opportunities for differentiation. 

There are a multitude of 3D packaging 

technologies in development that are driving 

opportunities for new dielectrics, adhesives, 

metallization materials, and others. 

YD: Looking at the PCB segment, the trend 

clearly continues to be miniaturization 

meaning thinner and smaller area. How 

do you see this affecting sales volume in 

this segment of the industry ? What do 

you see as the opportunities here ? 

LL: Thinner and smaller substrates are needed 

to support ever increasing consumer demand 

for ultra-portable electronics with constant 

connectivity, so there are significant growth 


opportunities in this segment. Increased 

power density and ultra-low K die have caused 

challenges managing thermal stresses resulting 

from TCE miss-matches in the material sets 

used in packaging. These challenges open 

opportunities in new laminate technology as 

well as silicon and glass interposers. Our 

Interconnect Technologies business is quite 

active supporting their customers who are 

developing high performance laminates for 

advanced packaging. My business has multiple 

projects focused on silicon interposers. 

YD: Bringing the discussion down another 

level, lets look at two of the hottest 

buzzword packaging technologies : fan 

out packaging and 3D IC technology. 

Looking at fan out packaging we think 

it is pretty well known rumor that RHEM 

was close to a product win with your 

InterVia dielectric, at Freescale in their 

RCP (redistributed chip pack) fan out 

technology, when the downturn came and 

Freescale decided not to move forward. 

Can you say anything about that or shall 

we just leave it as an unsubstantiated 

rumor ? Can you enlighten us as to the 

current Dow activities in this area. 

LL: I can’t comment on industry rumors. I can 

say Dow’s Advanced Packaging Technologies 

business has been successful in FO-WLP, and 

we are looking forward to seeing to seeing this 

exciting market grow. 

YD: Another technology with a lot of hype 

surrounding it is obviously 3D integration. 

R&H was an early supporter of 3D through 

its membership in the EMC-3D consortium. 

Rumor has it that with the significant 3D 

commercial announcements in the last 

few months, the work of the consortium 

will be winding down. Can you comment 

from a materials supplier vantage point 

how you view your experience in the 

EMC-3D consortium and what benefits it 

brought your business ? 

LL: Again, I can’t comment on industry rumors. 

The tremendous complexity of developing fully 

integrated processes to support 3D packaging 

make consortia such as EMC-3D very valuable. 

Our experience participating in EMC-3D has 

been very positive. 

YD: When asked to look into your crystal 

ball and predict commercial timing for 

3D integration in Jan 2009 you indicated 

that “...significant traction will be coming 

in 2012-2013…and HVM following that” 

Congratulations, your prediction is pretty 

much right on. Any comments on how you 

now see 3D evolving and what the play 

will be for materials suppliers and for 

Dow in particular? Do you see 3D IC as 

a broad change in the way we will make 

ICs in the future? or a niche technology 

for memory stacking and image sensors ? 

LL: 3D growth is of course closely tied 

to cost-benefit. Initial applications will be 

driven by high-performance applications that 

can support higher cost. Ultimately, as we 

drive cost down, 3D packaging will become 

common and will be seen in many high-volume 

consumer applications, so I don’t see it as a 

niche market in the future. Dow is actively 

developing many new materials to support 

3D packaging, such as new dielectrics, new 

underfills and new plating chemistries. 

YD: Over the last few decades we 

have certainly seen a major move to 

Asia for chip fabricatrion , packaging, 

interconnect, displays etc. As a materials 

supplier how does this affect how you 

do your development work and where 

you place your development labs going 

forward ? 

LL: Dow Electronic Materials has a philosophy 

of being close to our customers. We have APT 

development labs in Japan, Korea, Taiwan and 

the US. Going forward, we will continue to 

make the investments needed to stay close to 

our customers and the markets we serve. 

YD: Do you see a trend for Asian suppliers 

to want to buy materials that are being 

made close to the production factory? or 

is that not an issue ? 

LL: It varies. What is most important is a 

robust and reliable supply chain. Our global 

manufacturing footprint makes this less of an 

issue for Dow Electronic Materials. 

YD: Getting back to scaling, as we see 

the number players at each evolving 

node diminish does this make materials 

supply a riskier business? What does this 

tell you about partnerships and how you 

must now approach investment in new 

materials development? 

LL: We see customer partnerships and JDAs 

as a key tool to manage risk associated with 

the high level of R&D investment our business 

requires. In our APT business and certainly 

across Dow Electronic Materials, we place 

great importance on customer intimacy. 

YD: Leo, thanks for taking the time to talk 

with us. Best of luck to you and Dow in 

the future…. 

www.dow.com 

19



Packaging wafers for MEMS and LED 

MEMS and LED packaging puts high demands on materials and technical solutions 

in respect to packaging wafers. We have interviewed Carsten Wesselkamp, sales 

manager of Plan Optik AG - the technology leader in MEMS packaging solutions to 

find out the actual status in the wafer level packaging material market. 

Carsten Wesselkamp, 

Sales Manager, 

Plan Optik 

Yole Développement: Initially constrained 

to microfluidic and MEMS spaces, structured 

glass wafers recently gained momentum in 

new areas such as LED, CMOS image sensors 

and camera module module packaging. Could 

you comment on how Plan Optik has been 

following this evolution? 

Carsten Wesselkamp: Due to the nature of glass 

being transparent, wafer level packaging of LED, 

CMOS image sensors and ca,era modules, Plan 

Optik offers a variety of packaging wafers which 

are used in these applications. A good example is 

an anti-reflection coated glass-silicon cap wafer 

for the packaging of high power LEDs for car 

head lamps which is already supplied to one of 

the biggest LED makers worldwide in large mass 

production quantities. 

CW: Plan Optik produces compound wafers containing 

glass and Si areas. Besides other applications these 

wafers can be used for conductive connection 

through the packaging wafers. Main application 

is 3D wafer level packaging of MEMS. For these 

wafers a unique and patented method is used - the 

so called «glass reflow technology» - Si wafers are 

micro machined and the cavities respectively holes 

are filled by insulating glass. After several years of 

R&D in respect to implementation of such cap wafers 

in 3D MEMS packaging the first implementations 

in MEMS have started in 2010. Biggest advantage 

of this type of cap wafers: they can be anodically 

bonded and the vias are hermetic - a big benefit and 

mandatory demand for MEMS sensor packaging. This 

technology is not competing to regular TSV since the 

Si filled vias do have a lower conductivity. 

YD: What is the current status of “TGV” – Through 

Glass Via technology commercialization at 

PlanOptik? What are the benefits of providing 

electrical vias in glass instead of silicon wafers? 

YD: Do you believe that 3D Glass interposers 

could enter the LSI semiconductor packaging 

market? It seems that many glass suppliers 

are all quite active in this area at the moment! 

What are the benefits of Glass material here 

compared to silicon? 

CW: We believe that the main application of 

TGV technology is on MEMS packaging - not on 

semiconductor packaging - due to the restrictions 

in respect to conductivity and the fact that TGVs 

do not necessarily lead to lower cost compared to 

actual TSV solutions. 

Carsten Wesselkamp, 

Sales Manager of Plan Optik AG 

Mr. Wesselkamp serves as the 

international sales manager of Plan 

Optik AG, the technology leader in the 

production of structured cap wafers 

for MEMS applications in various 

industries. Plan Optik’s head quarter 

is based in Elsoff near Frankfurt, 

Germany. The company is listed in the 

Entry Standard at the Frankfurt stock 

exchange under ISIN DE000A0HGQS8. 

Glass-Si-Compound-Packaging-Wafer 

(Courtesy of Plan Optik) 

YD: Could you comment about your recent 

product release featuring holed Glass carrier 

substrates for thin wafer handling of TSV 

wafer applications? 

CW: For thinning and handling of semiconductor 

wafers such as GaAs and Si wafers rigid carriers are 

needed. For GaAs wafers typically sapphire wafers 

are used. A special cte adapted glass provides a 

similar performance but dramatically lower cost for 

this application. In TSV processing typically very thin 

Si wafers need to be handled (e.g. just 50 µm thick). 

This requires handling wafers which need to fulfill 

many demands such as heat and chemical resistance. 

A cte adapted glass is the perfect carrier material 

since it fulfills these requirements and additionally 

allows an easy temporary bonding inspection since it 

is transparent. Depending on the temporary bonding 

and release process such carriers can be blank (for 

laser release) or with holes (for chemical release). 



Low TTV Glass Carrier for TSV with holes for chemical release 

(Courtesy of Plan Optik) 

3M ® and EVG ® are both providing a temporary bonding solution and 

are working with such glass carriers. There are many proprietary 

developments for temporary bonding in almost all big semiconductor 

companies. Plan Optik offers carrier solutions (e.g. honeycomb surface 

structured carriers - a Plan Optik self-developed solution) which fits to 

most of the temporary bonding solutions in the market. Plan Optik is 

already supplying such carriers in mass production quantities. 

www.planoptik.com 

About Plan Optik 

Plan Optik AG has been founded in 1972 as a processor for 

optical parts such as lenses, filters and cover glasses. In the 

end of the 90s the product portfolio has been transformed to 

the production of glass wafer for anodic bonding. Nowadays Plan 

Optik is producing various kinds of packaging wafers (cap wafers) 

for MEMS wafer level packaging as well as process carriers for 

semiconductor processing and TSV substrates. Materials used 

are glass, silicon and glass-silicon compounds as well as quartz. 

For more information, please visit 

www.planoptik.com 


21



Analyst corner: 

Welcome to the ‘mid-end’ 

The mid-end: that confusing zone of overlap in wafer-level packaging between the 

BEOL and back-end packaging. 

Jérôme Baron, 

Market Analyst, 

Advanced Packaging, 

Yole Développement 

Everyone involved in the semiconductor industry is 

familiar with the terms “front-end” and “back-end.” 

You may have even heard the term “mid-end” also 

being used by integrated device manufacturers 

(IDMs) to describe everything that takes place 

between the back-end-of-line (BEOL) and back-end 

packaging operations. 

Many IDMs now have internal front-end-of-line 

(FEOL), BEOL, and back-end packaging operations. 

This is causing industry-wide confusion as more 

new steps such as bumping, redistribution layers 

(RDL), under bump metallization (UBM), throughsilicon 

vias (TSVs), passive integration, wafer 

molding, and wafer test are being done in the 

space between BEOL and back-end packaging 

operations. So these companies, among others, 

are particularly confused about who should be 

working on these steps. In some cases, it’s logical 

to ask the BEOL companies to do it. In other cases, 

it makes more sense to let the back-end packaging 

companies handle it. 

Now that wafer-level packaging companies are 

suddenly evolving rapidly and in many different 

directions, the boundary between “front-end” and 

“back-end” is becoming blurred. Many people are 

seeing a “mid-end.” Many others are adamantly 

opposed to this idea, still seeing a clear division in 

business models between front and back. 

Our definition of the “mid-end” is any wafer-scale 

packaging techniques that can be supported 

by either front-end or back-end equipments, 

materials, and infrastructures. In this sense, the 

mid-end is a very interesting space where both 

IDMs, CMOS foundries, MEMS foundries, wafer 

bumping houses, outsourced semiconductor 

assembly and test houses (OSATs), and possibly 

PCB companies can provide the same related 

services, but leveraging different equipment and 

material infrastructures—namely semiconductor 

processing, semiconductor packaging, PCB, or 

liquid crystal display (LCD) ones. 

“Mid-end” Infrastructure for Wafer-Level-Packages 

Main Technology Platforms 

P: Production 

D: Development 

Flip-chip & Cu- 

Pillars 

TSV Stack 

3DICs 

WL CSP 

(Fan-in) 

FO WLP & 

Embedded die 

WL Camera / 

LED / Fluidic 

Glass & Si 

interposer 

Glass Wafer Attach 

X 

Wafer Back lapping X X X X 

Technology 

platforms 

Thru Si Vias X X X 

Wafer rebuilt / molding 

X 

Sputtering / Plating X X X X X X 

Redistribution layers X X X X X 

Ball Drop X X X X 

IPD X X X 

OSAT subcon #1 P D P P P D 

OSAT subcon #2 P P P D 

Technology 

suppliers 

PCB #1 D D 

Substrate supplier #1 D P 

MEMS Foundry #1 D P P P 

Si CMOS Foundry #1 P D P P D 

IDM #1 P D P D D D 

IDM #2 P D D D D 

Extracted from Yole Développement’s 2011 report on “Equipment & Materials for the Wafer-Level-Packages” 



Take the case of the flip chip: ASE, STATS ChipPAC, 

Amkor, and SPIL all invested in flip chip bumping 

during the past 5 years to meet flip chip market 

growth. The price, yield, length, and complexity 

of their services is still perceived as a bottleneck 

to drive flip chip technology out of the highperformance 

market toward high-volume, low-cost 

consumer applications. Anticipating a strong move 

to flip chip for the 28/22nm nodes for system-onchip 

generations, TSMC recently invested massive 

funds in flip chip at their BEOL operations in Tainan 

(TW) and their capacity now exceeds the total 

capacity of each of the top four OSATs. If TSMC is a 

challenger in the future flip chip landscape, Global 

Foundries, Samsung, and UMC will likely follow and 

invest in this area we could call either the “mid-end” 

or “wafer-level back-end” space. In response to 

this move, OSATs are now reluctant to aggressively 

invest any further in wafer bumping and flip chip 

since it appears to be moving from a back-end 

packaging operation to the BEOL fabs now. 

We’re observing the same phenomena for waferlevel 

chip-scale packages (WLCSP)—TSMC and its 

subsidiary Xintec are building a brand-new 300mm 

fab dedicated to WLCSP operations. 

In a similar development with fan-out waferlevel 

packaging (FOWLP), OSATs regard FOWLP 

as their “mid-end,” because it’s an area where a 

“TSMC” won’t likely venture into since it’s much 

closer to OSAT packaging and test property. So 

STATS ChipPAC, ASE, and NANIUM invested in 

Infineon’s embedded wafer-level ball grid array 

(eWLB) technology, which is based on a high yield, 

extremely expensive front-end semiconductor 

equipment and material processing. At the 

same time, Amkor, J-Devices, and many others 

are pursuing another type of FOWLP based on 

PCB-related build-up materials and PCB panel 

processing equipment such as laser direct imaging. 

Indeed, since FOWLP is a “substrate-less” package 

technology it’s now causing the PCB materials 

and substrate industry to be wary of the very real 

possibility of being out of the wireless IC substrate 

business within the next decade. So PCB-related 

companies are becoming very active in the FOWLP 

area as well. This means that OSATs can look 

forward to more competition or instead choose to 

forge alliances for FOWLP 2nd generation with PCB 

players to move to larger panel size and reduce 

the cost of the passivation and molding materials 

involved in FOWLP. 

Looking at TSV and 2.5D interposer technologies, 

the question of who is doing what becomes even 

more confusing. While we’re starting to see some 

trends emerging for TSV manufacturing, it’s not 

at all the case with interposers. It’s still very 

much every company doing their own thing. A key 


debate in the interposer space for the wiring layers 

is whether the OSATs’ expensive RDL processes 

will prevail against foundries and the IDMs’ 

copper damascene BEOL wiring processes that 

are supported by old and depreciated fabs. The 

confusion becomes even more significant if you’re 

also following the current debate between glass vs. 

silicon interposers. Even though glass is a relatively 

new material in the semiconductor packaging area, 

it recently attracted the attention of the industry 

in terms of its exceptional mechanical rigidity, low 

coefficient of thermal expansion, and insulation 

properties. Glass sheets also cost significantly 

less than silicon and are widely available on panel 

size (mainly driven by the LCD and flexible display 

industries), prompting a few companies to evaluate 

the feasibility of a game-changing interposer 

strategy as proposed by Georgia Tech’s Packaging 

Research Center consortia. 

In the TSV filling space, a key question remains 

about the isolation, barrier seed, and seed layers. 

It’s a matter of which technology, front-end 

Chemical Vapor Deposition (CVD) or Physical Vapor 

Deposition (PVD) vs. back-end wet electrografting 

chemistries such as those supplied by Alchimer, or 

nanospray dielectric polymer depositions supplied 

by EGV, Suss or Dai Nippon Screen, will be adopted. 

In the underfill material space, we’re seeing 

many companies wonder if back-end capillary and 

no-flow types of underfills can apply to narrowgap 

3DIC bonding layers or if they should invest 

directly in the front-end type of bonding polymer 

layers such as BCB, PI, or PBO. 

Many choices remain, and difficult decisions must 

be made. But we always come back to the central 

debate: Is it best to invest in a cheap, ready-to-use 

back-end solution that may face scaling issues in 

the future, or is an initially more expensive frontend 

solution preferable because it will be higher 

yield and scale to smaller dimensions now and in 

the long run? 

And while all of this is being played out, we 

may also start seeing more consolidation in the 

semiconductor equipment market. Big front-end 

equipment players such as Applied Materials, TEL, 

Novellus, LAM, ASML, Ultratech, etc. make more 

than $40B tool sales in the front-end, contrasting 

with the back-end and mid-end tool markets 

revenue of only a few billion annually. 

Growing demand for mid-end tools will be surging 

in the future, with sustained demand for flip chip, 

FOWLP, and 3DICs with TSVs. Because only three 

foundries will “maybe” drive further the 22- to 18-nm 

tool market, front-end equipment companies are 

anticipating that we’re rapidly approaching the end 

of an era. 

23 

“OSATs can look 

forward to more 

competition 

or instead choose 

to forge alliances 

for FOWLP 

2nd generation 

with PCB players,” 

explains Jérôme Baron


So what’s a front-end company to do? Expand into the back-end 

packaging area, because the mid-end is becoming the most profitable 

part and an area where there are great business opportunities right 

now. A back-end tool’s average cost is $100,000 to $300,000 per 

unit. In the mid-end, the tool prices are much similar to the ones 

of the front-end. Typically, DRIE, wafer bonder, temporary bonders 

and debonders, mask aligners, etc., cost typically $1M to $5M per 

unit. A good example is Applied Materials’ acquisition of Semitool to 

expand and sustain this mid-end/back-end direction. 

Another possibility is to develop business in “derivative” semiconductor 

manufacturing technologies, where demand is growing quickly, such 

as high-brightness LED manufacturing, for example. It’s no secret that 

lithography giant Ultratech is eyeing the LED tool market. 

As a result, mid-end equipment companies such as EVG, SUSS, 

and SPTS, are being challenged by big fab tool companies, whose 

goal appears to be having a complete tool offering—from 3DICs 

from front-end to mid-end to back-end tools—so they can visit 

fabs and sell the whole set of tool solutions in one block to their 

customers. LAM, Novellus, and ASML appear to be trying to catch 

up to Applied Materials’ strategy. The only critical ingredient missing 

in the portfolio of the biggest players in this mid-end environment 

are the wafer bonding and temporary bonding and debonding tools. 

And factor driving this move is that big customers like TSMC, Intel, 

Samsung, and Toshiba may be afraid to rely on smaller companies 

like EVG and Suss to meet their capacities for the high demand in 

terms of the number of tools to be shipped per year, engineering 

support to fabs, etc. 

In another interesting twist, TEL and Applied Materials have both 

started to internally develop their own wafer bonding and temporary 

bonding/debonding tools. We’re expecting these equipment giants 

to announce the availability of their own 300mm bonding and 

temporary bonding/debonding tools this year. 

Clearly, there is quite a lot of activity going on in the mid-end. While 

the mid-end encompasses WLP technology, it runs much deeper 

than that and involves the now-emerging infrastructure required to 

support it. This mid-end is a fascinating space to watch, one that 

promises to become even more interesting as the big decisions are 

made and it continues to evolve. 

Jérôme Baron leads Yole 

Développement’s MEMS and 

Advanced Packaging market 

research. He has been involved 

in the technology analysis of the 

3D packaging market evolution at 

device, equipment, and material 

supplier levels. Baron earned 

a MSc. Degree in Micro and 

Nanotechnologies from the National 

Institute of Applied Sciences in 

Lyon, France. 

24 



C o m p a n y I n s i g h t 

The turning point for MCMs 

In the epic battle for low cost and performance, multi-chip modules (MCMs) had 

generally lost to system-on-a-chip (SoC) devices due to higher package assembly 

costs and lower performance. 

The tides are turning. Several factors have been in 

play recently: 

• Package assembly costs of MCMs have been 

dropping. 

• MCM package technologies are becoming 

commonplace instead of being relegated to 

certain applications such as memory or image 

sensors. 

• Emerging technologies are eliminating performance 

limits on MCMs. 

• Tapeout costs are increasing exponentially as 

wafer technology nodes shrink. 

Conventional stacked wirebond BGA 

Stacked and side-by-side SiP BGA 

Tapeouts that only cost about $200k a few nodes 

ago now run in the millions of dollars at 28nm. 

This means companies will be forced to have fewer 

tapeouts in order to support their product lines. The 

risk with each tapeout is higher and there is not 

much room for adding different flavors of product 

unless there is a considerable market for each 

individual product. MCMs may serve as a solution 

for this issue. 

Flipchip/wirebond back-to-back MCM 

Face-to-face microbump wirebond 

One approach for MCMs is to create a base chip that 

can interface with several different devices to make 

a family of products. The base chip can remain the 

same, but be paired with complementary devices 

and potentially different packages in order to gain 

the variety of interfaces or functionality needed to 

serve multiple markets or customer requirements. 

A few examples include: 

• A base device with various options for memory 

content. 

• A base device with complementary devices, 

such as SerDes, to change the external package 

interfaces. 

• A base device with additional functionality on a 

second chip to service additional markets 

Stacked TFBGA PoP 

Flipchip MCM with packaged memory 

Flipchip and stacked wirebond PoP 

What drives the cost? 

In conventional wirebond technology, the ball count 

is a good indicator of total package cost. The reason 

for this is not due to the cost of solder. Instead, 

the solderball count simply correlates well to the 

number of vias, traces and wirebonds in a design, 

which together are good indicators of package cost 

—without having to use any sort of special designrule 

set. Therefore, if an MCM can be developed to 

have considerably fewer solderballs, it may more 

than offset the cost of the additional die placement. 

Side-by-side flipchip BGA 

3D-IC 

3D-IC stacked with memory 



For example, assume a 208-ball thin and fine BGA 

(TFBGA) ASIC device that has roughly 150 signals. 

Fifty of these signals may be a 32-bit memory 

interface (32 data pins plus 18 address pins). If a 

memory die were embedded in the package with 

direct chip-to-chip copper wirebond connections, 

this would effectively eliminate the need for 

50 solderballs. The cost for this MCM would be 

roughly 80 percent of the single-chip solution. This 

assumes a 24-percent reduction in solderballs, vias 

and traces, plus the added cost of a second chip 

placement and additional copper wires. This does 

not include the cost of the known-good memory die, 

but that cost would be incurred anyway external to 

the package. 

A key assumption in the example above is that 

the wires connect directly between the two die. 

This requires some planning ahead with the MCM 

in mind. The ASIC would need to be planned 

relative to the pinout of the memory die/device, 

so that the pin order and wirebond length and 

angles meet standard rules. If at least one of the 

die is not planned with the other in mind, then the 

likelihood of success of direct bonding between 

the two die becomes unlikely. Instead, jumpers on 

the substrate or more advanced technologies such 

as package-in-package (PiP) would be required 

to make the connections between the two chips. 

This would drive up the cost and make the MCM an 

unattractive option. 

Therefore, while there are many factors that 

affect the cost of an MCM, they have recently 

been trending towards being less expensive than 

single-chip solutions with proper advance planning. 

Nothing is more expensive than a lack of planning 

for an MCM, or pursuing an MCM implementation as 

an afterthought for existing die. 

More than just an area benefit 

Package-on-package (PoP) technologies have become 

mainstream packaging techniques. The last Apple 

iPhone A4 processor used a flipchip die on the 

bottom package and two wirebonded stacked 

memories for the upper package. One clear benefit 

was in board area, but this volume application is 

also helping to drive down the cost for this approach 

in the industry. 

Applications such as high-end network processors 

are not as cost-sensitive as consumer applications. 

For these high-end applications, the adoption of MCM 

packaging has really been driven by area reduction 

and external pin-count reduction. Nonetheless, this 

may still be a more cost-effective solution for the 

system. By bringing the memory devices into the 

package, the number of balls needed to connect 

to the PCB is considerably reduced. While this 


does not initially appear to reduce package cost, 

it does reduce the overall system cost. Depending 

on how this is executed, bringing external memory 

(bare die or packaged memory) into the MCM may 

actually be a much less expensive option under 

some circumstances. 

Traditional MCM rationale still applies 

The classic reasons for using an MCM may still 

apply. MCMs are still good mechanisms for mixing 

die technologies such as GaAs and CMOS. They 

are also valid for mixing CMOS nodes such as 

0.13um CMOS with 65nm CMOS. These traditional 

MCMs are just now benefiting from the assembly 

infrastructure being put into place for the newer 

generation of MCMs. 

What will drive widespread MCM 

adoption? 

Cost and area savings are clear and valid reasons 

for moving towards MCMs, but a drive towards 

flexibility may be the next large factor. The everincreasing 

cost of a tapeout means that it may no 

longer be practical to have a family of parts that 

serve various segments in a market. Instead, a 

single tapeout that integrates other devices to 

add flexibility may offer the opportunity to create 

a family of parts with a single tapeout. This is a 

new angle on design-and-reuse—a cornerstone of 

SoC intellectual property (IP). But now the reuse 

may come from die that is shared across multiple 

packages in order to mix and match interfaces or 

additional functionality. Many of these strategies 

have already been seen in the market as well as 

in our own activity. This driver may not address 

the unit-cost challenge, but it certainly addresses 

the issue of rising non-recurring engineering (NRE) 

costs for the most advanced nodes. 

The difficulty here is changing the mindset of ASIC 

design teams so that they start with this end-game 

strategy in mind. This MCM strategy requires much 

more concurrent design activity with what was 

once considered downstream activity—packaging, 

thermal management, signal integrity, etc. Some 

companies will understand this and take advantage 

of it sooner in their design process. Once they’ve 

established a critical mass of complementary die to 

use in adding flexibility to their ASICs, they will have 

an advantage over those who underestimate the 

extent of the potential benefits of MCM adoption. 

www.esilicon.com 

Javier DeLaCruz, 

Semiconductor 

Packaging 

Director, 

eSilicon 

Corporation 

Javier DeLaCruz is 

the manufacturing 

technology director at eSilicon 

Corporation. He has over 15 years 

of experience in semiconductor 

packaging and is a senior member 

of IEEE. Prior to eSilicon, DeLaCruz 

served as principal packaging engineer 

at Multilink Technology where he 

managed the packaging team that 

developed most of the enabling 

technologies that allowed for lowercost 

packaging that serviced the 

optical networking market at 10Gbps 

and 40Gbps data rates. Previously, 

he served as technical program 

manager for the eastern U.S. at STATS. 

DeLaCruz started his career in M/A- 

COM’s research and development group 

where he used his electrical, mechanical 

and thermal background to develop 

analog packaging technology and other 

related patented work. 

27


C o m p a n y I n s i g h t 

Challenges and opportunity 

in 3D TSV interposer packaging 

Increasing demand for new and more advanced electronic products with a smaller 

form factor, superior functionality and performance with a lower overall cost has 

driven the semiconductor industry to develop more innovative and emerging 

advanced packaging technologies. 

One of the hottest topics in the semiconductor 

industry today is 3D packaging using 

Through Silicon Via (TSV) technology. Driven 

by the need for improved electrical performance 

or the reduction of timing delays, methods to use 

short vertical interconnects have been developed to 

replace the long interconnects found in 2D packaging. 

The industry is gearing up to move from technology 

path finding phase for TSV into commercialization 

phase, where economic realities will determine the 

technologies that can be adopted. Choosing the right 

process equipment and materials with innovative 

design solutions addressing thermal and electrical 

issues will be the key success factor. 

3D integration is progressing on three fronts starting 

with package-level (die, package stacking), wafer 

level (die-to-wafer bonding, fan out WLP) and more 

recently at the Si level (TSV) as shown in Fig.1. 

Gaining in popularity for many reasons, 3D TSV 

interposers are not considered as a just temporary 

measure or stepping-stone technology anymore. 

The consensus is that interposers may act as a 

bridge to full 3D IC integration in some applications, 

but they also remain a viable enabling technology for 

new applications requiring high-density 3D package 

integration architectures. 

3D TSV interposer is an efficient and practical 

approach to solving die integration challenges. Many 

microsystem devices that will have to move to waferlevel 

packages will also facilitate further integration 

using silicon TSV interposers. 

3D TSV interposer technology 

3D interposer, whether silicon or glass-based, is a 

next-gen substrate technology that is perceived 

as a ‘bridge’ platform between today’s 2D and the 

“true 3D” that is expected to debut in 2013-2014 

timeframe. Features such as the integration of 

advanced logic and analog functions will pave a way 

to the commercialization of 3D interposers in the 

near term. Silicon interposers with TSVs are being 

touted as a short-term bridge to full 3-D ICs. 

3D Integration- The solution space – 3D @ package level, wafer level & Si level 

Interconnect Density 

Time / Si Tech Node 

3D Packaging roadmap from STATS ChipPAC 



a 

3D Integration - TSV interposer SiP with IPD and POP 

Embedded Passives 

3D TSV 

b 

TSV and bump 

interconnection 

Figure 2. (a) Micrograph of Chip-to-Wafer bonding 

and (b)SEM micrograph of 50um pitch 

with underfill in small gap 

(Courtesy of STATS ChipPAC) 

TSV formation and interposer fabrication 

The various critical technology challenges associated 

with integration of high-aspect ratio TSV to form a 

reliable through-silicon interconnect structure can be 

identified as deep damascene copper via filling and 

CMP as well as thin wafer handling. Though there are 

a wide range of techniques for forming high aspect 

ratio deep silicon via structures like Bosch etch 

process, cryogenic etch process, laser drilling and 

powder blast micromachining, these methods in its 

original form yield extremely vertical profiles which 

makes them less suitable for realizing a reliable voidfree 

through silicon interconnection. 

Microbump process and bonding 

In advanced 3D stacking technologies, one of the 

important steps is to develop and assemble fine 

pitch and high density solder microbumps. Solder 

microbumps for flip-chip interconnections allow 

high wiring density in the Si-carrier, as compared 

to organic or ceramic substrates, and enable highperformance 

signal and power connections. 

Micro bumping technology where bump pitches are 

less than 50 micrometers using solder is explored 

extensively in the industry for realization of 

miniaturized 3D IC integration. Different solder and 

under bump metallurgy (UBM) material systems, 

fabrication process of solder microbumps as well 

as assembly process with those solder microbumps 

have been studied with the objective to develop 

reliable fine pitch solder micro joints at low cost. 

b 

Figure 4. 3D Packaging with TSV interposer with micro-bumped flipchips and IPDs 


The fine pitch solder microbumps can be applied 

to chip-to-chip or chip-to-wafer assembly. This is an 

important step to realize microbumping technology 

for miniaturized 3D stacked packaging. 

Integrated thin film passives with TSV interposer 

With shrinking of CMOS devices, the total size of the 

device is expected to shrink also, but more and more 

function blocks need to be integrated together for 

the more advance functions. One way is to integrate 

more devices within or after CMOS devices, such 

as RF passive devices. Another way is to package 

more function blocks together. Both methods target 

to reduce space and increase function. Passives 

in any electronic system occupy 70 to 80% of the 

board space laterally. Integrating them into the 

stacks reduces system space, enhances electrical 

performance by placing the passives (R, L, C) in 

the carriers so as to be nearer to the active chips. 

Hence embedding passives and actives with TSV 

technology adds advantages in the manufacture of 

3D SiP’s. Passive components that can integrated on 

the silicon carrier enable the system integration into 

more modular form as shown in Fig.9 

a 

Micro bump 

interconnection 

Figure 3. (a) Micrographs of TSV interposer flip chip package and (b) SEM micrograph of cross section of (a) 



29


Future applications of 3D TSV interposer technology 

The 3D TSV interposer technology allows integration of chips fabricated 

in different technology node (65nm, 40nm, 22nm, etc), different testing 

requirement with a shorter developmental cycle time. It also allows 

integration of different components such as MEMS, photonic and optical 

devices enabling larger system integration. 

3D TSV interposers are one of candidates that would be useful for 

ELK devices and high performance applications. TSV interposers also 

have the potential to replace advanced substrates due to advantages 

in thermal performance, precise dimension control, fine line width/ 

spacing, embedded passives as well as overall thickness. There should 

be cost/performance crossover between Si interposer and advanced 

substrates in the near future. Once TSV technology reaches a mature 

stage, it will be useful for more complex 3D heterogeneous integration. 

Conclusion 

For successful implementation of TSV interposer technology to 

microsystem products, TSV process and TSV packaging/assembly 

both should be well prepared and established with close collaboration 

and clear understanding. 

There is no question that 3D TSV will be adopted, but the timing for 

mass production depends on how the TSV technology compares in 

terms of cost with existing technologies. While progress is being made, 

design, thermal, reliability and testing issues remain a barrier to 3D 

TSV adoption in some applications. 

The semiconductor industry is beginning to capitalize on the additional 

values of a 3D TSV integration approach. Things are moving, the 

momentum is still there, but the first products must show up in 

the market to make 3D TSV a reality and thus move this advanced 

interconnect technology into the mainstream market and applications. 

3D TSV must help to reduce overall semiconductor cost, improve 

performance or reduce form factor and reduce the time-to market. 

About STATS ChipPAC 

STATS ChipPAC is a leading service provider of semiconductor 

design, bump, probe, packaging, test and distribution solutions 

for the communications, computer and consumer markets. With 

a broad portfolio of assembly and test services, advanced process 

technology in wafer level, flip chip and 3D TSV packaging, and a 

global manufacturing presence spanning Singapore, South Korea, 

China, Malaysia, Thailand and Taiwan, STATS ChipPAC delivers 

innovative and cost effective semiconductor solutions. 

For more information, please visit 

www.statschippac.com 

Seung Wook Yoon, 

Ph.D., MBA, is in 

charge of technology 

marketing of nextgeneration 

integration 

technology at STATS 

ChipPAC, including TSVs, embedded 

packaging, integrated passive device, 

and 3-D IC packaging. Prior to joining 

STATS ChipPAC, he was deputy lab 

director of the Microsystem, Module, 

and Components Lab at the Institute 

of Microelectronics in Singapore. 

Yoon received a Ph.D. in materials 

science and engineering in 1998 from 

KAIST in Korea. He also holds a MBA 

from Nanyang Business School in 

Singapore.. 



N o t e s f r o m Y o l e D É V E L O P P E M E N T 

Standardization initiatives for 3DICs 

New magazine design, new section has arrived with the Notes from Yole Développement! Sally Cole Johnson 

had the chance to interview separately Yole Développement analyst’s Jérôme Baron, Phil Garrou, Jean-Marc 

Yannou, and Christophe Zinck, inviting them to provide their insights into some key questions surrounding 3DIC 

standardization. 

What’s the holdup 

with standardization? 

Phil Garrou: It would have been nice if 3DIC 

standardization had begun earlier, but industry 

organizations wanted to ensure this was really 

happening before they put the required effort 

into it. With the commercial announcements in 

2010 by Elpida/UMC, TSMC, IBM, Samsung, 

and Xilinx, everyone is now convinced this 

technology can’t be stopped. 

Jérôme Baron: Material selection is a 

crucial part of the process and can become 

the differentiating criteria in wafer-level 

packaging performance, size, and cost. 

Most IDMs and foundries don’t disclose 

which technology they’re investing in until 

after several evaluation trials. This doesn’t 

help. So universities and R&D institutes 

such as LETI, IMEC, ITRI, IME, RPI, ASTRI 

and Fraunhofer’s institutes are playing an 

important role in this material evaluation, 

selection, and standardization process. But 

even here, R&D institutes often have ties to 

the material giants. So it’s difficult to identify 

and develop a standard solution. 

Christophe Zinck: Many issues need 

to be addressed before 3D/TSV volume 

industrialization, especially yield and thermal 

management. 

Jean-Marc Yannou: There are two lagging 

building blocks of 3D TSV: Module ownership 

(supply chain liabilities aren’t yet clearly 

defined) and development of an infrastructure 

for test of 3D modules (the owner will test it), 

and the design tools for developing 3D physical 

descriptions + thermal + electrical simulation 

of 3D modules. This is another ‘which came 

first, the chicken or egg’ situation. CAD vendors 

are quite conservative, so they are waiting for 

the first such 3D TSV modules to reach high 

production volumes. 

quickly in the near future. JEDEC, SEMI, 

SEMATECH, GSA, iNEMI, and ITRS are all 

involved and working together to coordinate 

the efforts. 

CZ: There’s a need to standardize stacked 

DRAM with logic. Cooperation is taking place 

within the industry, such as Elpida/PTI and 

UMC. I expect big players like Samsung to 

drive their own products and integration. 

Foundries and OSATs need standardization 

to align their ‘interposer’ offerings, but 

adoption of the interposer isn’t happening 

yet, especially for the wide I/O interface. 

Samsung already stated they wouldn’t use 

interposers for their APE. 

JB: For wafer-level passivation resist materials, 

no standards have emerged yet to replace 

Dow’s BCB. Many materials are being evaluated 

as a potential replacement, but these are 

mainly polyimide resists, epoxy-based resists, 

PBO materials or fluorine polymers for waferlevel 

packaging. The industry would expect 

one type of material family to emerge and be 

selected to help make standardization happen. 

But no one material has a perfect profile—some 

have curing temperature issues, elongation 

strength issues, cost issues, or are simply too 

complex to process. It doesn’t appear likely 

that a standard will emerge for wafer-level 

passivation layers. 

Who’s leading the standardization 

effort? 

JB: In terms of standardization for TSVs/ 

3DICs, IDMs and foundries may be the 

first out with early 3DIC designs, product 

samples, and later on installed capacities. 

Volume growing at those players’ sites will 

determine which technology and related 

suppliers will be chosen, win, and end up 

becoming a standard. 

But I do have a ‘bone to pick’ with JEDEC 

for their refusal to publish who was involved 

in drawing up this document. We must have 

transparency in terms of knowing who is 

drawing up the standards. 

Is the industry communicating 

effectively? 

JB: Standardization won’t come until fabless 

IC companies, CMOS foundries, and OSATs 

begin communicating more effectively with 

each other at the early beginning of the IC 

design phase. And front-end and back-end 

technologies need to converge to an optimal 

packaging solution that can be supported by 

the different “flavors” of this so-called ‘midend’ 

wafer-level-packaging infrastructure. 

PG: Qualcomm is certainly out there at nearly 

every 3D venue pushing for the technology 

standardization to move ahead. The quarterly 

SEMATECH meetings tied to other 3D 

conferences are also providing everyone an 

opportunity to contribute to the effort. 

Timeline for standardization? 

PG: It will take a few more years before 

everything is in place. 

JMY: By 2013, we’ll see the first mass production 

3D modules with TSVs for logic+memory “wide 

IO interface” in smartphones, which will 

probably be influenced by the current JEDEC 

discussions. 

Jérôme Baron 

Phil Garrou 

PG: In 2010, JEDEC issued JEP-158 3D Chip 

What’s going on with 

standardization of TSVs/3DICs? 

Stack with Through-Silicon Vias: Identifying, 

Evaluating, and Understanding Reliability 

PG: There’s a lot going on. Numerous 

standards setting organizations are engaged, 

so I see things starting to move much more 

Interactions, a guideline to describe the 

extension of standard tests to 3D chip 

structures. This does a good job of looking at 

reliability considerations and failure modes. 

Jean-Marc Yannou 

Christophe Zinck 


31


Y o l e A s k s 

IPDiA’s value proposition 

for interposer products 

IPDiA has developed two leading technologies based on several years of R&D 

and innovative programs in PICS technologies as well as in 3D packaging & 

interconnection. IPDiA is offering 2D- and 3D- interposer platforms dedicated to 

Medical, RF communication, Industrial, Defense and Aerospace domains. 

“Silicon Interposer 

with Passive 

Integration is your 

access to product 

miniaturization 

and enhanced 

performances,” 

explains Stéphane 

Bellenger, IPDiA 

2D-Interposer product is available as a silicon 

substrate with metal routing for external flipped 

and/or wire-bonded components inter-connection. 

The final module composed of external components 

on interposer could be integrated into the customer 

application by using wire-bond or CSP technology as 

an option (see figure 1). IPDiA’s interposer advantage 

is coming from the Passive Integration capability as 

an additional option of the 2D-interposer platform 

(high integrated capacitors with more than 250nF/ 

mm², high accurate MIM capacitors and polysilicon 

resistors, high Q-factor self, as well as ESD 

protection or Zener Diodes). Second advantage 

of the 2D platform is related to the form factor 

provided by the inter-connection design rules, with 

a cost-adapted process and equipment technology. 

The third interposer advantage is related to the high 

and proven reliability of the flip-chip technology 

ranges, from 20µm accuracy process suitable for 

auto-centering effect during the reflow (Solder 

bumps technology), to 7µm accuracy placement 

capability of thermo-compression processes (Gold 

bumps, ACF or NCF as an option). Finally, the usage 

of accurate jetting equipment for the underfill 

deposition is able to save surface and cost with a 

400µm jetting area (Jetting dot control) and less 

than 200µm for the bleeding areas (volume control 

with µ-grams accuracy). Very low CTE material 

usage is well-adapted to a die-to-wafer application 

using silicon. 2D-interposer main characteristics are 

described in the table. 

Passivation 1 – Organic passivation layer 

Metal 1 – Aluminium 

Figure 1: examples of 2D interposer for lighting 

application (4 wire-bonded LED & 5 flipped LED over 

Si-Interposer with PICS) and Medical application 

(Sensor, microcontroller and RF flipped 

die over Si-Interposer with PICS) 

(Courtesy of IPDiA) 

3D-Interposer product is a step forward platform 

using the full 2D-interposer technology options 

described here, with additional 3D interconnection 

using vias (See figure 3). 

As a consequence, the back-side is also proposed with 

the recommended routing suitable for the customer 

application, in term of end metal characteristics, 

pads or balls and dissipation surfaces. 

Finition 1 – Ni-Au 

Metal 2 – Copper 

Dielectric 1 – Oxide 

Dielectric 2 – Nitride 

Dielectric in vias – Oxide 

Silicon 

Dielectric 0 – Oxide 

Via – Copper filling 

Passivation 0 – Organic passivation layer 

Metal 0 – Copper 

Finition 0 – Ni-Au 

Figure 2: Illustration of via architecture (Courtesy of IPDiA) 

32 



Figure 3: Examples of 3D interposer with flipped die 

on each interposer side, and WLCSP finishing (Courtesy of IPDiA) 

A full mask aligner is the proper technology used in term of accuracy 

and cost for the 3D- interposer platform (Double side lithography) in 

combination with a deep silicon etching process suitable for cost to 

volume manufacturing target. 

High thickness for end-metal stack can be proposed thanks to 

IPDiA’s thick resist coating process. Vias can be processed with 

metallic or non-metallic material depending on the final application, 

via diameter and density. In the table is described the main 

3D-interposer characteristics. 

PARAMETERS 

Interposer Thickness (Without Via) 

Interposer Thickness (With Via) 

TSV diameter 

Vias filling 

Barrier layer 

Finition 0 

Finition 1 

PRELIMINARY SPECIFICATIONS 

[100 µm ; 400 µm] 

300 µm standard 

75 µm (Copper) 

Copper or Non metal 

Optional 

Optional 

Optional 

Via minimum pitch 125 µm 

Layer 0 metal thickness 

Copper 4 to 8 µm upon request 

Layer 1 metal thickness Aluminum 1 µm 

Layer 2 metal thickness Copper 10 to 15 µm 

Layer 0 metal minimum width 8 µm 

Layer 1 metal minimum width 1.5 µm 

Layer 2 metal minimum width 8 µm 

Minimum space between 2 metal lines 

(Layer 0) 


(Layer 1) 


(Layer 2) 

8 µm 

4 µm 

6 µm 

Table: Interposer characteristics (Courtesy of IPDiA) 

www.ipdia.com 

S t é p h a n e 

Bellenger, Assembly 

Market Manager and 

Packaging Expert at 

IPDiA. 

Over 20 years experience in 

semiconductor packaging from 

Innovation to Process Development & 

Industrialization within two international 

semiconductor companies. 

3 D P a c k a g i n g 31


W h a t ’ s I n s i d e ? 

Silex TSV in MEMS oscillator 

from Discera 

The Discera DSC8002 is a programmable CMOS oscillator incorporating a Silicon 

MEMS resonator. 

It is provided in several packages, the smallest 

being a 4-pin MLF whose dimensions are 

2.5x2x0.85mm. Thanks to a Silicon Fusion 

Bonding process and TSV connections the resonator 

achieve an area of only 0.27mm² 

Low resistivity Silicon wafer 

Electrical connections 

through wafer 

ASIC 

TSV 

Scallops relief 

characteristic of a DRIE 

Annular TSV without filling (courtesy of Silex) 

Electrical connections 

through wafer 

“The MEMS resonator 

die size has been 

shrinked by almost 

4 times,” 

explains 

Romain Fraux, 

System Plus 

Consulting 

MEMS Resonator 

Resonator die – SEM Tilt View 

(Courtesy of System Plus Consulting) 

Technology analysis 

The manufacturing of the resonator is realized by 

Silex Microsystems probably on 6-inch wafers. 

The MEMS resonator is wafer-level packaged and 

electrical connections are realized by TSV. 

Resonator 

Substrate 

Cap 

ASIC 

TSV 

MEMS Resonator Cross-Section 


Low resistivity 

Silicon wafer 

Poly 

Oxide 

Contact Si/Poly 

Void 


Silicon wafer 

TSV Details – SEM View 


The TSV are realized with the Silex TSI TM technology: 

through-wafer trenches are created by DRIE and filled 

with an isolating dielectric. The TSI TM technology is 

applied to a highly doped Si wafer, a closed vertical 

trench around a “plug” of Si constitutes an isolated 

electrical connection through the wafer (through 

silicon via – TSV). 

TSV Via-first process flow 

The TSV are realized on the low resistivity silicon 

wafer of the resonator prior to the manufacturing of 

the resonator itself. First, the wafer is patterned and 

TSV are etched by DRIE. In order to keep the via plug 

in position, the trench etch stops short of reaching all 

the way through the wafer (the final trenches have a 

TSV Via-first Cost Breakdown 

10% 

20% 

30% 

40% 

50% 

60% 

70% 

80% 

90% 

100% 

0 

Low resistivity Silicon wafer 

DRIE trenches 

Thermal oxidation 

Polysilicon deposition 

CMP top side 

Thinning + CMP back side 



Font: Franklin Gothic Book Regular/BOLD 

PMS: 7491c 

CMYK: c - 62 / m - 27 / y - 100 / k - 9 

RGB: r - 108 / g - 141 / b - 59 

WEB COLOR CODE: #6C8D3B 



Silicon Wafer 

DRIE trenches 

Thermal oxidation 

Polysilicon filling 

CMP top side 

Thinning + 

CMP back side 

TSV Via-First process Flow 


depth of ~100µm). Then the trenches are filled with 

the isolating dielectric: a thermal oxide is grown on the 

wafer followed by a deposition of polysilicon which fills 

the via. The layers of oxide and polysilicon are removed 

from the surface of the wafer by CMP. Finally, a thinning 

process (backgrinding + CMP) is applied to the backside 

of the wafer, removing the material that keeps the “via 

plugs” connected to the bulk, thereby isolating the via 

plugs from the bulk of the wafer. 

Cost analysis 

TSV induces an additional cost to the front-end 

process and represent ~17% of the manufacturing 

cost of the final wafer. The saving in silicon area 

due to TSV connections is hardly calculable, but 

in addition with the silicon fusion bonding process 

the MEMS resonator die size has been shrinked by 

almost x4 compared with the first generation of 

Discera MEMS resonator. 

www.systemplus.fr 

Romain Fraux, 

Electronics Cost 

Engineer, 

System Plus 

Consulting 

Romain Fraux is 

Project Manager 

for Reverse Costing 

analyses at System Plus Consulting. 

Since 2006, Romain is in charge of 

costing analyses of MEMS devices, 

Integrated Circuit and electronics 

boards. He has significant experience 

in the modeling of the manufacturing 

costs of electronics components. 

Romain has a BEng from Heriot-Watt 

University of Edinburgh, Scotland and 

a master’s degree in Microelectronics 

from the University of Nantes, France. 

MEPTEC PRESENTS 

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March 21, 2011 • Doubletree Hotel • San Jose, California 

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• Enabling Higher LED Performance with Smart Thermal Management 

• Beating the Sun – Thermal Challenges for Photovoltaic Systems 

• TELCO & Server System Cooling Technology Update 

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35 

1/30/11 10:46 AM


e v e n t r e v i e w 

IMAPS Device Packaging 

Conference to focus on Advanced 

Packaging 

Panelists are: 

The seventh Annual Device Packaging Conference (DPC2011) will be held in 

Scottsdale, Arizona, on March 7-10, 2011. It is an international event sponsored 

and organized by the International Microelectronics And Packaging Society (IMAPS). 

Tom Strothmann 

Dir. of Business Dev. 

STATS ChipPAC 

Lars Boettcher 

Embedded Die Mgr. 

Fraunhofer IZM 

Navjot Chhabra 

Dir. Adv. Packaging 

Freescale 

Note from Dr Phil Garrou, General Chair 

IMAPS will hold the 7th International Device 

Packaging Conference this year at its usual location 

outside Scottsdale AZ. I will be finishing up my two 

year tenure as General Chair of the meeting. The 

conference will once again be focused on all aspects 

of Advanced Packaging such as 3D integration, 

3D packaging, bumping, fan in and fan out WLP, 

embedded packaging, MEMS, integrated passives 

and LED packaging. Industry experts in these areas 

will be heading up these tracks. 

Keynote presentations will include: 

• Jerome Baron, Yole Développement, “Demand 

and Applications for 3D TSV” 

• Peter Elenius, E&G Technology Partners, “Flip 

Chip and Wafer Level Packaging - Past, Present 

and Future” 

• Farrokh Ayazi, Ga Tech, “Advanced Packaging for 

Multi-Axis Resonant MEMS Gyroscopes” 

• Kai Liu, STATS ChipPAC, “RF System-in- 

Packages: History and Trends” 

The full program can be accessed on our website 

www.imaps.org. 

h t t p : / / w w w . i m a p s . o r g / p r o g r a m s / d e v i c e 

packaging2011.htm 

Of special interest will be the “Fan-Out and 

Embedded” panel discussion arranged by Andy 

Strandjord, Pac Tech and Linda Bal, Freescale Semi 

which is detailed below. 

Fan-Out and Embedded Panel Discussion: 

Tuesday March 8th, 7:00pm – 8:30pm 

Moderators: Andrew Strandjord, Pac Tech USA and 

Linda Bal, Freescale Semiconductor 

An executive panel has been assembled from 

several of the leading microelectronics companies 

and institutes from around the world to discuss the 

latest on Fan-Out and Embedded Technologies. The 

introduction of new manufacturing technologies 

and added infrastructure has moved both of these 

technologies into high volume production over the 

last year, and many questions remain on how this 

will affect the future of the microelectronics industry. 

The panel members will each give a short presentation 

on the current activities within their company, and 

then debate and give their perspective on the issues 

related to volume manufacturing, future technology 

innovations, cost, and market trends. During this 

discussion, the panel will also be soliciting questions 

from the audience. 

www.imaps.org 

John Hunt 

Dir. of Engineering 

ASE 

Thorsten Meyer 

eWLB Project Mgr. 

Infineon 

Images Courtesy of: Stats ChipPAC, IZM, Freescale, ASE, & Infineon 




6 th European Advanced Technology Workshop 

on Micropackaging and Thermal Management 

The sixth annual European Advanced Technology Workshop on Micropackaging and Thermal Management was 

held on February 2nd and 3rd, 2011 in the city of La Rochelle on the Atlantic coast of France. 

This year’s event attracted over 100 attendees 

from 13 countries with over a third of the 

participants coming from outside of France. 

With this diverse participation, there was a 

high quality of technical exchange among 

scientists and engineers from universities, 

national laboratories and industry. 

After the welcome address by IMAPS France 

president Jean-Marc Yannou, the workshop 

started with two keynote papers: 

• Alexandre Avron, a market analyst from 

Yole Développement (France), reviewed 

strategies for the thermal management of 

high power modules and systems, operating 

in different market segments, with power 

dissipation up to 200W/Cm 2 

• David Saums, Principal of DS and A (USA) 

presented an overview of the trends and 

developments for electronic coolant liquids 

to meet the needs of different market 

segments, environmental requirements 

and legislation. 

MiNaPAD 2011 

In total, there were 23 papers divided into four 

sessions: (1) applications, (2) materials, (3) 

simulation and modelling and (4) systems. 

The program highlighted the progress of 

several technologies which are maturing in the 

marketplace: 

• Metal Matrix Carbon Composites for baseplates 

and packages. In these novel composites, 

aluminium or copper is combined with graphite, 

carbon fibres or diamond to provide a material 

with high thermal conductivity and low density. 

• Heatsinks with high fin density. Here, the 

high surface area leads to a significant 

improvement in heat transfer to liquid 

coolants in power devices. 

• Two phase liquid cooling systems. 

In addition, new and interesting developments 

were presented for die attach adhesives for 

power components. Combining a high thermal 

conductivity with moderate flexibility, they offer 

good adhesion strength with lower thermomechanical 

stress, compared to traditional 

epoxy adhesives. 

On the power applications side, new sectors 

as electric or hybrid vehicle propulsion and 

LED lighting, reach a step of growth which will 

open volume markets for the related cooling 

systems. 

As every year, the workshop hosted table top 

exhibits and there was record number of 18 

exhibitors. They presented die attach and 

coating solutions, packages and baseplates, 

heatsinks, cooling circuits as well as thermal 

simulation and measurement. 

The exhibit area provided a location for 

stimulating discussions and networking among 

attendees, speakers and exhibitors. 

After a well appreciated 6th annual workshop, 

all enthusiastically look forward to the 7th 

annual IMAPS MicroPackaging and Thermal 

Management Workshop to be held again in La 

Rochelle in February, 2012. We look forward to 

see you there next year. 

www.imaps.org 

The first edition of the Micro/Nano-Electronics Packaging and Assembly, Design and 

Manufacturing Forum (MiNaPAD) will be held on May 11 and 12, 2011 at the new 

Minatec campus in Grenoble, France. 

Organized by IMAPS France, and co-sponsored 

by CEA-LETI, Minatec and the French Chapter 

of IEEE/CMPT, the MinaPAD forum responds to 

a growing interest in design and assembly of 

micro- and nano-electronic packages and their 

increasing importance in the value chain for 

electronic components. As such, the forum’s 

objective is to bring closer the package design 

and assembly communities – which both have 

a large presence in Europe. 

The conference will feature several consecutive 

sessions and an exhibition. Many abstracts 

from prominent organizations have been 

received and over half the exhibition booths 

are already booked. Among the confirmed 

participants are world-class equipment and 

material suppliers from Europe, Japan and the 

United States, CAD tool vendors, assembly 

and test service providers (OSAT), as well 

as the top European research institutes and 

semiconductor companies. Keynote speakers 

from ITRS (International Technology Roadmap 

for Semiconductors), NANIUM and ST 

Microelectronics have accepted invitations. A 

final program will be available in early March 

2011. 

The abstract deadline has been extended until 

February 15. Exhibitors who are not already 

registered are encouraged to reserve quickly. 

Topics to be addressed in the MiNaPad forum 

include: 

• Package design methodology, design tool 

• Innovative packaging for MEMS, photovoltaic, 

biosensors, energy harvesting, LED 

• System-in-Package for smart systems, 

telecom, automotive and medical applications 

• A s s e m b l y, 

processes, 

e l e c t r i c a l 

testing and 

reliability characterization 

of advanced packaging platforms (TSV, 

3D Packaging, fan-out WLP, embedded IC 

package) 

• Interconnect for flip chip, sub 45nm CMOS, 

fan-out WLP, through silicon via, and 3D 

packaging 

• Poster session 

For more information, please contact 

Florence Vireton: +33 (0)1 39 67 17 73 

email: imaps.france@imapsfrance.org 

We look forward to see you in Grenoble! 


37



In 2011, Yole Développement’s Advanced Packaging Analysts Team 

chose to attend the following key events: 

> IMAPS - Int. Conf. & Exhibition on Device Packaging 

March, 8 to 10 - Scottsdale, AZ, USA 

www.imaps.org/devicepackaging 

> DATE 2011 

March, 14 to 18 - Grenoble, France 

www.date-conference.com 

> Semicon China 

March, 15 to 17 - Shanghai, China 

www.semi.org/scchina-en/index.htm 

> MEPTEC - The Heat is On - Beating the Heat: Performance and Cost 

Improvements through Thermal Management Design 

March, 21 - San Jose, CA 

www.meptec.org 

> Image Sensors Europe 

March, 22 to 24 - London, UK 

www.image-sensors.com 

> ICEP 

April, 13 to 15 - Nara, Japan 

www.jiep.or.jp/icep 

> MiNaPAD 2011 

May, 11 to 12 - Grenoble, France 

www.imapsfrance.org 

> ECTC 

May 31 to June 3 - Lake Buena Vista, FL 

www.ectc.net 

> IISW 

June, 8 to 11 - Hokkaido, Japan 

www.imagesensors.org 

> ICMAT 2011 

June, 26 to July 1 - Singapore 

www.mrs.org 

> Semicon West 

July, 12 to 14 - San Francisco, CA, USA 

www.semiconwest.org 

> Semicon Taiwan 

September, 7 to 9 - Taipei, Taiwan 

www.semicontaiwan.org 

> EMPC 

September, 12 to 15 - Brighton, UK 

www.empc2011.com 

> 3DIC 2011 

October 3 to 5 - Tokyo, Japan 

www.3dic-conf.org 

> Int. Wafer Level Packaging 

October, 3 to 6 - Santa Clara, CA 

> Semicon Europa 

October, 11 to 13 - Dresden, Germany 

www.semiconeuropa.org 

And also Semicon Japan, EPTC, 3-D Architecture for Semiconductor 

Integration and Packaging... 


www.EVGroup.com


About Yole Développement 

Beginning in 1998 with Yole Développement, we have grown to become a group of companies providing market research, technology analysis, 

strategy consulting, media in addition to finance services. With a solid focus on emerging applications using silicon and/or micro manufacturing 

Yole Développement group has expanded to include more than 40 associates worldwide covering MEMS and Microfluidics, Advanced Packaging, 

Compound Semiconductors, Power Electronics, LED, and Photovoltaic. The group supports companies, investors and R&D organizations worldwide 

to help them understand markets and follow technology trends to develop their business. 

Consulting services 

• Market data, market research and marketing analysis 

• Technology analysis 

• Reverse engineering and reverse costing 

• Strategy consulting 

• Corporate Finance Advisory (M&A and fund raising) 

CONTACTS 

For more information about : 

• Services : Jean-Christophe Eloy (eloy@yole.fr) 

• Publications: David Jourdan (jourdan@yole.fr) 

• Media : Sandrine Leroy (leroy@yole.fr) 

reports 

• Collection of market & technology reports 

• Players & market databases 

• Manufacturing cost simulation tools 

• Component reverse engineering & costing analysis 

More information on www.yole.fr 

MEDIA 

• Critical news, Bi-weekly: Micronews, the magazine 

• In-depth analysis & Quarterly Technology Magazines: MEMS Trends – 3D Packaging – PV Manufacturing – Efficien’Si - Power Dev’ 

• Online disruptive technologies website: www.i-micronews.com 

• Exclusive Webcasts 

• Live event with Market Briefings 

Editorial Staff 

Board Members: Jean-Christophe Eloy & Jeff Perkins – Media Activity, Editor in chief: Dr Eric 

Mounier - Editor in chief: Jérôme Baron - Editors: Dr Christophe Zinck, Jérôme Baron, Phil Garrou, 

Jean-Marc Yannou, Sally Cole Johnson – Media & PR Manager: Sandrine Leroy – VP New Media 

Development: Bill Stinson - Assistant: Camille Favre - Production: atelier JBBOX

mid-end - I-Micronews

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