3D - I-Micronews

3D
ISSUE N°22
FEBRUARY 2012
Packaging
Magazine on 3DIC, TSV, WLP & Embedded die Technologies
Printed on recycled paper
INDUSTRY REVIEW
Demand for
wafer-level
chip-scale packages
accelerates
COMPANY INSIGTH
ST-Ericsson and
CEA-Leti unveil
their WIOMING 3D
demonstrator
ANALYST CORNER
Release of the 1 st
wide-IO Jedec
standard
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in 3D!
Finally, a One-on-one
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The world of device manufacturing is in a rapid state of transformation—
and 3D & wafer-level packaging is a game-changer of unprecedented scope.
To meet the needs of cost, performance and size, multiple solutions are
emerging for wafer-level packages encompassing several technology platforms.
The result? An entire global supply chain dedicated to 3D integration of IC
chips is emerging, as the semiconductor IC community has grown to accept
3D integration as an alternative to scaling. The question is no longer why 3D?
Today, the question is how, where, when 3D…and with whom? To become a
part of the 3D development vanguard, it's imperative that you meet and engage
the emerging innovators at Connect in 3D. Collaboration Summits SM are
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The Connect in 3D Collaboration Summit, presented by Yole Développement,
the world leader in technology information, provides the freedom to meet, learn,
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Mark your calendar today!
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contact Brian Perkins, bperkins@HighlinerEvents.com, +1 207-799-1356.
OCTOBER 31–NOVEMBER 1, 2012
WESTIN MISSION HILLS RESORT & SPA
PALM SPRINGS, CA

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
E D I T O R I A L
3D comes true in 2012!
If there were any 2012 prophecy I could believe, it is the promise of
a year rich with 3D packaging announcements and product releases.
Here’s a short-yet-major announcement which, to be honest, I’m surprised
has not made a bigger buzz yet: for the first time ever, a commercial
product has been announced with through silicon vias (TSVs) in a CMOS
logic integrated circuit (IC). The IC is a smartphone application processor
and the TSVs are meant to connect it directly to its overlying DRAM
memory via a so-called wide-IO bus. This announcement was made on
January 18, 2012 by Renesas at ICP - the Integrated Circuit Packaging
conference in Tokyo.
…It’s a fact that
3D is getting more
real every day…
e v e n t s
• MEPTEC – The Heat is On
March 19 – San Jose, CA
• Semicon China
March 20 to 22 – Shanghai, China
• Image Sensors 2012
March 20 to 22 - London, UK
platinum partners:
It’s a fact that 3D is getting more real every day. Last October, Xilinx
announced the product launch of the virtex-7 family of FPGAs with up
to six large CMOS and memory dies assembled side-by-side on a huge
silicon interposer. Last December, Jedec released its first standardization
document concerning the operation protocol and aspects of the physical
layout for so-called “wide-IO interfaces”, which are used to stack large
data bus (512 bits) DRAMs onto their interfacing logic chips, necessitating
TSV in the logic IC, so as to reach unprecedented data bandwidths and
to limit the DRAM power consumption altogether.
But the news didn’t stop there. Not even a month later, Renesas
Electronics announced that volume production of devices following wide-
IO architecture will begin as soon as 2013. Concurrently, ST-Ericsson
also claim successful demo chips based on wide IO and 3D integration.
One can reasonably assume that if the industry keeps up with this pace
of announcements and product releases related to 3D, we can expect
that many bold product designs and innovations will materialize by the
end of the year. We intend to continue addressing every advanced
packaging topic in 2012, not just 3D integration by means of TSVs. A lot
is happening within the scope of wafer-level packaging, flip chip and chip
embedding, to name just a few. For example, in 2011 Texas Instruments
industrialized their MicroSiP packaging concept based on chip embedding
in substrate, and STEricsson seemed only weeks away from releasing
their first fan-out WLP product.
In this February issue we’ll focus on industrial facts, in order to bring
a balanced and complementary viewpoint to offset our self-proclaimed
R&D-enthusiast bias. On example of this are the articles in this issue on
the evolution of fan-in WLCSP, its infrastructure and market, and how it
went from being considered an advanced technology differentiator to a
“must-have” industry standard in just a few years.
Jean-Marc Yannou,
Senior Analyst, Advanced Packaging,
Yole Développement
yannou@yole.fr
3 D P a c k a g i n g 3

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
C O N T E N T S
INDUSTRY REVIEW 6
• Demand for wafer-level chip-scale packages accelerates
COMPANY INSIGHT 10
• ERS: High tech thermal solutions coming from southern Germany
for the world market
• Palomar Technologies Assembly Services discusses the value
of automation for ultra high-precision applications
(Courtesy of ASE Global)
• AT&S has taken dramatic stepsto bring ECP ® to market,
and now things are starting to warm up
• ST-Ericsson and CEA-Leti’s WIOMING prototype shows how to combine
wide IO memory and logic SoC for future 3D multi-processor architectures
ANALYST CORNER 20
• Market dynamics impact WLCSP adoption
• WLCSP market trends to watch in 2012
• Moving 3D IC forward with the standardization of wide IO DRAM
WHAT’S INSIDE? 26
OmniVision’s VGA wafer-level camera
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latest reports …
> TSMC plans 3-D IC assembly launch
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> First major 3D TSV wide-IO product
announcement is made by Renesas
> STATS ChipPAC packaging evolution
to 2.5/3D: a closer look
GOLD PARTNERS:
4 3 D P a c k a g i n g

Solid State Equipment LLC
ADVANCED PACKAGING
SINGLE WAFER
WET PROCESSING
TSV CLEAN AND RESIST STRIP
As received – post DRIE After SSEC Cleaning As received – post DRIE After SSEC Cleaning As received – post DRIE After SSEC Cleaning
Si ETCH TO REVEAL Cu TSV
DRY FILM STRIP
Optical SEM ISIS 3D
FLUX CLEANING
ADVANCED PACKAGING SINGLE WAFER WET PROCESSING
UBM AND RDL METAL ETCH
Undercut vs Etch Time
Undercut (µ)
1.7µ
1.5µ
0µ
(non-measurable)
WaferChek +15 sec +30 sec
Over-etch Over-etch
Etch Time
Before Etch
After UBM Etch
ssecusa.com
© 2011 SOLID STATE EQUIPMENT LLC
SSE_345_MicroNews AdV3.indd 1
10/20/11 3:11:03 PM

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
INDUSTRY REVIEW
Examples of WLCSPs made by ASE
(Courtesy of ASE)
Demand for wafer-level chip-scale
packages accelerates
Wafer-level chip-scale packages (WLCSPs) are by no means the lowest-cost solution
available, but its tiny volume and electrical performance benefits are turning it into
the “go-to” package for use in mobile phones and tablets.
For insiders’ perspective into the WLCSP
market, we turned to Advanced Semiconductor
Engineering, Fairchild Semiconductor, FlipChip
International, Teramikros, and VTI Technologies.
Growth ahead
WLCSP technology is constantly evolving—not
necessarily in groundbreaking ways, but to
meet different increasing demands and subtle
variations in the thickness of the material,
material compositions, structures, and sizes for
new applications.
While it’s now being produced in much greater
volume, it is important to point out that there is no
standard WLCSP. There are tremendous variations
in WLCSP because each customer has specific
application requirements.
“Our customers have been saying for the past 6
months that the growth of WLCSP is accelerating,”
says John Hunt, director of engineering at ASE.
“Many packages are being transitioned to WLCSP,
and one customer is moving an entire family of flip
chip CSP into WLCSP. We’re also seeing more analog
and power management going into WLCSP. I expect
it to pick up—we’ve put in additional capacity for
300-mm analog.”
Ted Tessier, FlipChip International’s chief
technical officer, believes WLCSP growth will
continue to increase during the next 5 years as
new applications emerge that will benefit from the
minimal form factor possibilities of this technology.
“Emerging applications like image sensor packages,
MEMS packaging, as well as stacked die solutions,
will emerge in the industry. Fan-out packaging
technologies, either wafer-level or embedded-diein-laminate
approaches, will continue to leverage
the installed supplier base put in place for waferlevel
packaging (WLP) technologies,” he notes.
“I expect the technology to continue to grow. Fanin
WLP is mature, but there are emerging new
technologies that are still somewhat immature,”
says Heikki Kuisma, director of advanced
development at VTI Technologies.
6
3 D P a c k a g i n g

I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
Examples of WLCSPs made by ASE
(Courtesy of ASE)
From Fairchild Semiconductor’s perspective,
Yong Liu, senior member technical staff, and
Jifa Hao, technical staff member, concur that
they expect growth for WLCSP power devices
to continue at the same or an even faster
pace, thanks to its primary advantages: small
package size, minimized IC to PCB inductance,
and shortened manufacturing cycle time.
“WLCSP has been primarily applied to small
(< 3 mm 2 ) to medium (3-5 mm 2 ) chip sizes,”
says Takeshi Wakabayashi, Teramikros’
general manager, development division. “We
expect it to also penetrate to large chip sizes,
such as 5 mm 2 , or larger as well, increasing
the growth rate of WLCSP market.” He expects
WLCSP to ultimately become the dominant
packaging design in the future.
For the moment, WLCSP technology for I/O
counts of less than 50 is considered by most
to be mature. There is, however, plenty of
activity underway in the industry to extend
board-level reliability of WLCSP packages to
array sizes in the 100 – 200 I/O range—while
achieving acceptable reliability. There are
opportunities for improvements in this area
and for broadening the application envelope
to these higher I/O counts.
Liu and Hao note that WLCSP requires waferlevel
equipment and high automation, and
that the reason some OEMs are reluctant to
use WLCSP is because it involves a solder
bumping process that’s quite different from
the traditional wafer-level device process.
Interestingly, as Wakabayashi points out,
it’s becoming more important to make PCBs
smaller to secure and maximize space for
the battery because it directly determines
the competitiveness of smartphones. “Since
WLCSP is truly a chip-size package, it’s the
package type of choice to fight for limited
space,” he explains. “Unfortunately, however,
some OEMs had a bad experience with
unsuitable WLCSPs with reliability issues.
Their smartphones were susceptible to
damage from being dropped. We can’t stress
enough the importance of selecting the right
WLCSP.”
Fan-out WLCSP and chip
embedding in substrates
Can fan-out WLCSP or chip embedding in
substrates supplement adoption of WLCSP
in the near future? The general consensus
is yes, but the timeline for this happening
remains unclear.
Tessier believes that IC modification to
prepare devices for embedding in fan-out
WLCSP or embedded die in PCB substrates
will grow in popularity over the next few years
because fine-line redistribution layers (RDL) is
most effectively carried out at the wafer-level
to minimize per die costs associated with die
preparation for embedding.
Kuisma notes that the scope of fan-out WLP
will remain more limited than ordinary WLCSP.
“But for us, this is a very interesting technology
that we need to look at closer,” he adds.
“With the advent of more SMT-compatible
underfill processes, WLP solutions involving
larger array sizes are enabled. Without these
underfill advances, the board-level reliability
of such large arrays wouldn’t be adequate for
smartphone applications,”
says Ted Tessier, FlipChip International.
Both fan-out and embedding can supplement
WLCSP, according to Hunt. “There are reasons
to go to fan-out WLCSP, such as when you can’t
fit all of the I/O onto a package at wafer-level.
WLCSP is a less expensive solution, so you
wouldn’t use fan-out WLCSP if you don’t need
it. It can, however, supplement applications
for which WLCSP isn’t suitable,” he elaborates.
“And chip embedding actually uses a WLCSP
inside. Customers are beginning to ask us
to prepare the die before embedding—which
means putting copper RDL and under bump
metallization (UBM), one or both, on the
die before they embed them. This is a new
application for wafer-level processing.”
Is adoption of WLCSP
OEM dependent?
Adoption of WLCSP into smartphone applications
varies widely from one OEM to the next, but
its smaller package form factor is behind its
adoption by most.
Some OEMs have been reluctant to adopt
wide-scale use of WLCSPs, primarily because
of board-level concerns related to the largearray-sized
devices, according to Tessier.
“With the advent of more SMT-compatible
underfill processes, WLP solutions involving
larger array sizes are enabled. Without these
underfill advances, the board-level reliability
of such large arrays wouldn’t be adequate for
smartphone applications,” he says.
3 D P a c k a g i n g
(WLCSP Market & Industrial Trends report, January 2012, Yole Développement)
7

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
And as the industry moves down to 0.3 and
0.25 mm, it’s possible to fit higher I/O counts
onto the die. So some of the devices that
today need it fan-out or embedding won’t
with the move to finer pitches. You’ll still be
able to use a WLCSP—assuming reliability
requirements can be met.
Expansion to other applications
WLCSPs aren’t just for smartphones and
tablets—the technology is starting to make
headway into automotive, medical and more
MEMS applications.
“We’re observing the wide adoption of
WLCSPs beyond smartphone applications,
such as analog and power for industrial use,
in addition to medical and automotive,” says
Wakabayashi.
On the medical end of things, Kuisma sees
WLCSP use primarily in implantable devices
like pacemakers.
The automotive industry is also trying to
shrink down their electronics. “During the past
6–9 months we’ve seen increased interest in
power control modules and analog devices
for WLCSP, whereas it was previously RF and
digital applications,” explains Hunt. “This
increase isn’t necessarily under the hood; a
tremendous number of electronics go into the
body of the car—for navigation, radios, and
satellite communication.”
5–6 years, according to Tessier. “With the
wide-scale adoption of polybenzoxazole (PBO)
dielectrics and thick-plated copper RDL and
UBM structures, a package solution is available
to support WLCSP applications as they migrate
from ELK to ULK constructions,” he adds.
Advantages of WLCSP in CMOS
image sensors and MEMS
What are the advantages of using WLCSPs in
image sensors and MEMS?
From VTI’s perspective, mechanical stress
on MEMS is the most important thing. This is
much lower with WLCSP than with QFN/LGA,
explains Kuisma. “Size is the next advantage.
Avoiding wire bonds with increasing gold prices
is also important. Note: ultrasonic wire bonding
is always tricky with MEMS, especially copper
bonding with much higher energy. Further, our
way of stacking dies in WLCSP leads to very
low parasitics and good immunity to EMI. We
expect that more MEMS manufacturers will
eventually shift to WLCSP. Cost-wise, wire
bonding and QFN/LGA are equal to WLCSP in
MEMS applications,” he adds.
“It depends on your definition of WLCSP, but
we’re seeing more and more requests for 3D
and MEMS processing of packages in waferlevel
format,” says Hunt. “The smallest MEMS
reduce the size, which is always desirable.
Most image sensors, or at least many of them,
are wafer level.”
VTI’s CMR3100 is the world’s smallest
gyroscope, at 3x3 mm 2 , and it relies on WLCSP.
(Courtesy of VTI)
bumped devices. The added stand-off possible
with a WLCSP structure allows for ease of
underfilling as well as for ease of molding
with concurrent underfilling with molding
compound. Smaller stand-off flip chip bumps
may provide additional challenges.”
WLCSP is fundamentally different than flip
chip, according to Wakabayashi, although he
views some types of WLCSP as very similar.
“WLCSP doesn’t require expensive flip chip
bonders and can be mounted with conventional
SMT machines. Flip chip also requires very
costly underfill,” he says. “WLCSP with 0.25-
mm or even 0.20-mm pitch can be mounted
with high-speed SMT machines and general
reflow processes. In the case of low-k devices,
which are so fragile, handling of bare chips is
extremely difficult and costly.”
Other WLCSP trends
One WLCSP manufacturing trend is that while
it’s still primarily done in Taiwan, companies
are setting up facilities in other locations such
as Singapore, the Philippines, Korea, Portugal,
and China.
“Customers are beginning to ask us
to prepare the die before embedding,”
says John Hunt, ASE.
Opportunities for WLCSP expansion to
automotive and high-power computing aren’t
as good as applications like smartphone
and tablets, Liu and Hao caution, due to the
high current density, high power, and heat
dissipation factors. However, for lower-power
applications such as point-of-load switch, buck
converter, and smart integration of analog, logic
and power, they see great opportunities ahead.
Migration to new CMOS
technologies’ impact on WLCSP
Is the migration to new CMOS technologies
helping or hindering adoption of WLCSP? Are
new technologies necessary for ELK and ULK
layers?
The migration to new CMOS technologies seems
to be compatible with improvements that have
occurred in WLCSP packaging over the past
8
WLCSP vs. flip chip
There’s a clear trend of significant pitch
reduction. Why are WLCSPs used rather
than flip chips (even though WLCSPs can be
considered flip chips)?
Although the industry dabbles with 0.3mmand
0.25-mm-pitch WLCSPs, cell phone
OEMs are generally not equipped to perform
such fine-pitch assembly at the PCB level.
“Virtually all 0.3-mm WLCSPs shipped today
are used in modules or system-in-package
(SiP) applications, where they’re assembled
more like coarse-pitch flip chip components
rather than SMT components,” says Tessier.
“Generally, if these components are available
in a WLCSP format, the end user will attempt
to use these packages rather than redesign
the parts to slightly finer-pitch flip chip
“All of ASE’s WLCSP are in Taiwan. But we’re
increasingly facing low-cost competitors in
China,” notes Hunt.
Another more obvious trend: The relentless push
toward thinner WLCPS. With discrete packaging
continuing to produce thinner interconnects,
capacitors, and resistors, WLCSPs need to be
continuously thinned down to match these
thickness reductions—with target thicknesses
changing every 3 months.
And the industry is also working hard to
find ways to make larger WLCSPs for power
modules as reliable as smaller ones—at high
power, with thicker RDLs, and improved power
distribution—at a lower cost. So the goal is
to find ways to achieve all of this without
sacrificing reliability.
Sally Cole Johnson
for Yole Développement
3 D P a c k a g i n g

I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
Jifa Hao, Member of Technical Staff,
Fairchild Semiconductor
Hao is responsible for reliability engineering for technology
development. He received his Ph.D. in physics from State
University of New York at Stony Brook, and has published more
than 25 papers in journals and conference proceedings, and
holds 8 patents (and has 4 patents pending).
John Hunt, Director of Engineering,
Production Promotion, ASE (US)
Hunt provides technical support for the introduction, engineering,
marketing, and business development activities for all advanced
wafer-level packaging technologies at ASE. Prior to joining ASE,
Hunt was technology development manager at ADFlex Solutions,
and research and development engineering manager at both Nortel and Digital
Equipment Corp. He has 40 years’ experience in various areas of manufacturing,
assembly, and testing of electronics components and systems, with emphasis
on the development of new technologies and processes. Hunt holds a BS degree
in chemistry from Rutgers University, and a MS/MBA in industrial engineering
and engineering administration from the University of Central Florida.
Heikki Kuisma, Director of Advanced Development,
VTI Technologies
Kuisma’s responsible for the management of research and
advanced development in the area of MEMS sensors, MEMS
manufacturing technology, packaging of sensors, and sensor
interface circuits. He is also actively participating in the
planning and management of national and European technology programs in
Microsystems and microelectronics.
Yong Liu, Senior Member of Technical Staff,
Fairchild Semiconductor
Liu works in the packaging development group. His main interest
area is advanced analog and power electronic packaging. Liu
holds a Ph.D., is an IEEE senior member, and has co-authored
more than 160 papers in journals/conference proceedings, two
books, and has been granted 25 US patents (and has 18 patents pending).
Ted Tessier, Chief Technical Officer, FlipChip International
Tessier has more than 25 years’ experience in the semiconductor
packaging industry and a comprehensive industry perspective,
based on senior engineering and management positions at
Nortel, Motorola, Biotronik, Amkor, STATS ChipPAC, and FCI.
He has published actively and is well known in the industry for
his work in the areas of advanced packaging technologies, including wafer
bumping, multichip modules/system-in-package technologies, flip chips, 3D
packaging, WLSCPs, and wafer-level processes.
Takeshi Wakabayashi,
General Manager, Development Division, Teramikros
In 1980, he joined Casio Computer, engaged in development
of semiconductor process technology. In 1987, he completed
gold bumping process development for mass-production and
was engaged in development of WLP Technology in 1997. He
started the production of WLP at Casio Micronics Co., Ltd. 4 years later. In
2002, he initiated EWLP development for embedding and completed WLP
process development for 300mm wafer and low-k devices. He has been General
Manager of Teramikros since October 2011. He filed more than 40 patents
on Wafer Bumping, WLP technologies. Actively participating in JEITA, JPCA
standardization activities on embedding technology.
MiNaPAD conference - Grenoble, April 24th 2012
BEYOND 300 mm workshop:
Packaging Challenges and Opportunities
for 450 mm wafers and panel scale solutions
A SEMI event hosted by IMAPS
For more information visit:
www.semi.org/beyond300mm

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
COMPANY INSIGHT
High tech thermal solutions
coming from southern Germany
for the world market
ERS is a German company, founded in 1970 and specializing in thermal solutions
for the semiconductor industry. Calling itself a “research & development company
with a large production capacity” ERS participates actively in semiconductor
industry events and welcomes thermal challenges that defy standard solutions.
In 2008, engineer Klemens Reitinger took over the company from its founder
Erich Reitinger and launched a program of growth and diversification.
Klemens Reitinger,
Owner & General
Manager, ERS
Yole Développement: Would you please give
us a little background on what you were
doing before you joined ERS and what your
recent focuses at ERS are?
Klemens Reitinger: I joined ERS electronic
GmbH in February of 1992 having graduated as an
engineer of fine mechanics in Vienna. I worked in
almost every department within the ERS factory
including manufacturing, R&D and customer
support before taking over as general manager
in 2001. In June 2008 I took ownership of the
company and began a program of growth and
diversification including starting two completely
new product groups – FOWLP (eWLB) tools and
hot/cold thermal systems for final test.
YD: ERS is a technology leader in thermal
wafer test equipment dedicated to the
semiconductor wafer production since 1970.
Could you introduce to our readers ERS’s
products and activities?
KR: ERS was founded by my uncle, Erich Reitinger,
in 1970 and is now based in the Munich suburb
of Germering, Germany. We have approximately
45 employees generating approximately Euro 10M
in annual revenue. ERS has a world-wide support
network with offices in Dresden, in Charlotte,
North Carolina and in Dallas, Texas as well as sales
and service partners in Asia.
Our core competency is in thermal equipment
and our main products are thermal chucks used
in probing tools for semiconductor wafers. In
the 1970’s we introduced what we believe was
the very first thermal chuck for wafer test - a
2-inch Peltier-controlled unit. Since then we have
researched, developed and manufactured multiple
applications of temperature creation and control.
By the middle of the 1990’s, we had determined
that using air as the sole coolant in ERS thermal
units was the future direction of the company.
Thermal systems using air as the only coolant have
the highest uptime and the lowest running costs in
the industry and taking this decision enabled us to
take a very strong position in a market ever more
dependent on reliability and cost control. Many of
our products, especially the AirCool plus system,
flew in the face of conventional wisdom in terms of
what was possible and not possible with air cooling.
We have delivered thermal chucks systems using
only air as the coolant with operating temperature
ranges of -65°C to 500°C.
YD: Could you tell us what the main
requirements for fan-out WLP de-bonder
tools are in terms of thermal accuracy and
reliability for eWLB applications?
ERS’s ADM 300 eWLB debonding system (Courtesy of ERS)
KR: The key features of our fan-out WLP auto debonder
are based on the patented processes we
empirically developed over many months. These
processes include the safe removal of the carrier,
the clean de-taping and the extremely critical,
controlled cool-down of the reconstituted wafer
after de-bonding/de-taping. Air-cooled chucks in
the system are the basis of its inherent reliability
and the thermal control of those chucks is a direct
derivative of our experience in wafer test. The suite
10
3 D P a c k a g i n g

By Courtesy of CEA LETI and Novapack
By Courtesy of ST Microelectronics and CEA LETI
I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
of production features in the system comes
from customer input and includes wafer
marking, de-flash and warpage monitoring.
YD: Do you consider providing equipment
to process future 450 mm wafers?
KR: Yes, definitely. ERS is already
developing 450 mm air-cooled thermal chuck
technology for future 450 mm silicon wafer
test applications. As for the eWLB de-bonding
tools, the trend seems to be in the direction
of rectangular panels with form factors in
discussion that would exceed the area of a
450mm wafer. We have already built the first
engineering tool for these larger panels and
have requests for tests to be performed on
them at the FOWLP competency center in our
factory.
YD: According to you, what are the main
key features and advantages of the Fanout
wafer level packaging (also known as
eWLB technology) compared to standard
embedded wafer-level-packages? How
do you explain the different motivations
and drivers for eWLB?
KR: This is difficult for us as a tool vendor to
judge. Here are some of the answers that we
hear in the marketplace when we pose that
question to our customers:
• Suitable for multi-chip and system-inpackage
applications
• Maintain the same socket size through
silicon shrink generations
• Short signal path for improved high
frequency performance
• Very good thermal performance
• Lower material costs through “batchwiring”
• The opportunity to use existing front-end
tools for the redistribution layer (RDL)
• Very thin package size
• Small footprint package size
YD: Could you update us on what is
coming up on the R&D front at ERS?
KR: As mentioned, we are already working
on air-cooled 450mm thermal chuck systems.
Our current line of wafer thermal chucks is
now completely modular in manufacture, onsite
service and upgrading.
As for FOWLP, we continue to research
de-bonding, adhesive removal and shapecontrol
solutions for new applications using
new molding materials, adhesives, substrate
sizes and methods. This is being done in
cooperation with some 15 different industry
partners at our FOWLP competency center in
our factory.
In the back end, we are now working on a
general, air-only tri-temp solution (no liquid
nitrogen necessary) for the final test of
packaged semiconductor devices.
YD: What makes your ERS equipment
stand out versus competitors?
KR: We are a team of problem-solvers
including experts in thermo-dynamics, fine
mechanics, electronics test engineering,
software and system integration. Because
we have our own CAD/CAM manufacturing
capability we have access to same-day
prototyping so we can move quickly. What
really sets us apart from other high-tech
companies, however, is the fact that we set
temperature in the center of the problemsolving
process. I believe that is what really
makes us stand out from the others.
www.ers-gmbh.de
1events
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2 nd Micro/Nano-Electronics Packaging and Assembly,
Design and Manufacturing Forum
Conference & Exhibition
• The 2 nd MiNaPAD Forum (Micro/Nano-Electronics Packaging and
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Minatec campus in Grenoble on April 24-26. The event will begin on April
24 with a workshop Beyond 300mm sponsored by SEMI and hosted by
IMAPS. The MiNaPAD conference and exhibition will then be held on April
25-26. The final program and registration forms will be available at the
end of February.
By Courtesy of Ansoft
April 24 – Beyond 300mm Workshop
SEMI event hosted by IMAPS
April 25-26 – Conference & Exhibition
For further information, please refer to the website
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3 D P a c k a g i n g

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
COMPANY INSIGHT
Palomar Technologies Assembly
Services discusses the value of
automation for ultra high-precision
applications
With the ever-evolving trend for smaller applications, the capability to produce
high-precision, high-reliability bonding remains imperative.
Donald Beck,
General Manger, Palomar
Technologies Assembly
Services TM
Yole Développement: Could you please tell us
about your past background and career and
about your current assignments at Palomar
Technologies?
Donald Beck: I began my career in the mid-1980s
with a small microelectronic assembly house
in southern California. At that time, automated
wire bonders had just been introduced; I could
actually complete a part manually faster than
a machine could do it at that time! In 1989, I
joined a new team focused on HTCC packaging.
This particular role rendered a lot of knowledge
about the microelectronics industry, specifically
in Asia. Prior to joining Palomar Technologies, I
worked at a Florida-based company for 12 years
where I focused on classified complex assemblies.
In 2004, I joined Palomar as a Senior Applications
Engineer and within the first year became
Applications Manager. I quickly noticed that all
the key elements for contract microelectronic
assembly existed, so I lobbied to evaluate creation
of Palomar Technologies Assembly ServicesTM
(previously Palomar Microelectronics). In 2008, I
became General Manager of Assembly Services.
Coupled Capacitor on Die (COD) for Microelectronic
Circuits; Lightweight Modular Antenna Assembly
having RF Amplifier Modules Embedded in
Support Structure Between Radiation and Signal
Strength Distribution Panels; High Frequency,
Low Temperature, Thermosonic Ribbon Bonding
Process for System Level Applications; Method for
Removing Microelectronic Substrates 1; Method
for Removing Microelectronic Substrates 2.
YD: How would you define Palomar Technologies
as a company in just a few words?
DB: Palomar today is a company committed to both
ingenuity and integrity. When our team commits
to new application development—be it a new die
attach platform or new assembly technology—we
always honor our word and produce products we’re
proud to stamp our name on. We never dismiss the
importance of every customer we work with, which
is demonstrated through our long list of recurring
business opportunities around the globe.
YD: How would you like to define Palomar
Technologies in just a few words in 2015?
I’ve published several technical papers and articles
including “The Great Debate: Ball vs. Wedge” and
“Automated Precision Assembly for High-Volume
HB LEDs”. I also currently hold five patents: Closely
DB: By 2015, I would expect that our Assembly
Services division would support the majority of
our growing world-wide customer base and to
further define the unique and invaluable offerings
Palomar has as the only OEM who can service
all microelectronic needs through both capital
equipment and in-house precision microelectronic
assembly.
YD: How are your product lines structured,
and which is your best selling product family?
6500 Die Bonder cleanroom (Courtesy of Palomar Technologies)
12
DB: The 3800 Die Bonder, introduced in 2010, is
a leading solution. This large 0.9017 x 0.508 m 2
(35.5 x 20 inch) work area die bonder offers ultra
flexibility in application production, whether you
require epoxy die attach, pulsed heat eutectic
attach or a full-production in-line assembly. The
3800 Die Bonder offers a multitude of solutions
on a single platform—truly the “Swiss Army Knife”
of die bonders. Our 6500 Die Bonder is an ultrahigh
placement accuracy pick-and-place machine,
3 D P a c k a g i n g

I S S U E N ° 2 2 F e b r u a r y 2 0 1 2
which also has wafer level packaging (WLP)
configuration. Our 8000 Wire Bonder—a
large area, high-reliability wire bonder and
ball bumper with deep access capabilities—
complements our die attach equipment.
Augmenting our systems is our Customer
Services (Field Service support, Process
Development Consulting and bonder training
courses). With Assembly Services, customers
gain the unique ability to prototype and
develop critical processes and materials with
an OEM, utilizing highly skilled engineers
and the most advanced process tools; thus
reducing risk and shortening time-to-market
for today’s leading-edge applications.
YD: Which share of your Palomar’s
revenues can be attributed to advanced
semiconductor packaging?
DB: The majority of Palomar’s end application
development can be classified as “advanced”
or “complex”. “Electronics assembly” can
umbrella many organizations and OEMs, but
there is a component of that group into which
Palomar falls that does the really difficult
“stuff”, such as odd-form deep access
wire bonding, high-accuracy wafer level
packaging, or even highly secured assembly
services laboratories with computerized
production monitoring and management.
YD: What is the average life cycle time
of your equipment? How much of the
company’s revenue do you reinvest for
R&D?
DB: Today, we know of many Palomar systems
reaching decades of longevity and peak
performance. Our Field Services engineers
and Process Development Consultants enable
the success of our legacy equipment. We are
often creating that next “big thing” through
process development and prototyping with
our customers in our Assembly Services
laboratories.
YD: “High-precision” seems to be a
keyword of Palomar’s product offering. Do
you think that even finer accuracies will
be needed in the future? Can you please
give us some application examples?
DB: Today, almost all of our Assembly
Services opportunities stem through the need
for high accuracy. We see this especially in
photo diode and laser module designs. We’re
beginning to see a need for

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
YD: Silicon photonics seems to be booming again for the first
time since the 2000 slump. Are you confident that this will be
a long-term opportunity for Palomar?
DB: Palomar believes that whenever customers need the highprecision
pick-and-place requirements for opto-electronic
assemblies, we have a superior solution.
YD: Are there cases for which the LED market will require
high accuracy or other differentiating arguments Palomar
can offer? Which ones?
DB: As previously mentioned, we have seen some LED light engine
designs requiring sub-3µm placement requirements. These tend to
be designs with focus lenses so that alignment of the LEDs to the
lens is critical. Another could be through the emergence of Micro-
Ball Grid Arrays (BGAs). As these designs shrink, the need for high
accuracy will grow. We see this today with some surface mount
assemblies where an SMT assembler can support all needs up
until the Micro-BGA when they seek support through our Assembly
Services division. These applications are some of the leading
applications for our 6500 Die Bonder platform.
YD: What are Palomar’s current focuses in R&D?
How the mobile
industry has
grown a $1B+
semiconductor
packaging
platform?
DB: Palomar works with a broad range of customers to meet their
assembly challenges. We continually develop and improve both
machines and processes to improve our customers’ return on
investment.
www.palomartechnologies.com
Donald Beck, General Manger, Palomar Technologies Assembly
Services TM , Palomar Technologies
Donald Beck has led the Assembly Services division at Palomar Technologies
since 2008, expanding it from a "tiger team" to a major player in precision
microelectronics contract assembly. Under Mr. Beck’s tenure, Assembly
Services continues to develop new processes and solutions for customers
worldwide.
A three-decade microelectronics industry veteran, Mr. Beck began his
career at in southern California, developing high-reliability, Class B military,
prototype thick film memory modules. In 1989, Mr. Beck worked with a new
team to qualify and manage all assembly activity for on-shore and off-shore
subcontract suppliers. During this time, he developed assembly techniques
for Cofire Ceramic and Thin Film MCMs. Mr. Beck later become Lead Engineer
of Advanced Manufacturing for a Florida-based company. In this new role,
he not only engineered complex military packages, but also managed a
large microelectronic assembly supply chain. Mr. Beck joined the Palomar
Technologies team in 2004 to run the Applications Division, holding the title of
Senior Applications Engineer. At Palomar, he developed ball bump applications,
automated interconnect processes including an automated part pass through
system (for automotive customers), and an ultra-fine pitch (60um-70um)
interconnection processes for complex MCM applications. Soon after the start
of his career at Palomar, Mr. Beck was named General Manager of Palomar
Technologies Assembly ServicesTM.
14
WLCSP
Market &
Industrial
Trends
Discover the NEW
report on
i-Micronews.com/reports
3 D P a c k a g i n g

I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
COMPANY INSIGHT
AT&S has taken dramatic steps
to bring ECP ® to market, and now
things are starting to warm up
Excerpts from an interview with Mark Beesley, Chief Operating Officer, Advanced
Packaging at AT&S.
AT&S People: So Mark, could you tell us a
little bit about ECP ® – what is it?
Mark Beesley: “ECP ® , or Embedded Component
Package is AT&S’s patent-protected, next generation
packaging technology for active and passive
components. We are leveraging our state-of-theart
PCB competence, combining fifteen years of
R&D in the field of component embedding and
launching a really innovative concept.
The breakthrough is that our customer can now
stack surface mounted components on top of our
ECP ® substrate. In basic terms we can reduce
module and semiconductor package size by up to
40% compared to existing technologies.
Combine that with incredible reliability and
performance improvement, and our target markets
are really interested to benefit from ECP ® ”
AT&S: So tell us which Markets are your
targets?
MB: “Do you remember the smartphone of
five years ago? Probably not. Five years ago
the smartphone market was niche (but rapidly
expanding) and tablets were doomed. In 2012,
market analysts are predicting that smartphone
unit sales will approach five hundred million, nearly
one third of the total market for mobile phones,
and tablet sales in 2011 are slated to exceed sixty
three million units. What an incredible story.
Our first priority is to engage with these ramping,
technology-driven Markets, with the potential
to deliver high volume business. No surprise
that smartphone is where ECP ® has enjoyed first
successes, our miniaturisation benefit is so valuable
to differentiate an OEM’s product in this fast moving
segment … but it is far from the whole story.
“Green Energy” is tremendously exciting for us,
both in Industrial and Automotive areas. Our
integration and performance advantages can really
offer commercial benefits through supply chain
complexity reduction and power consumption
improvements.
Data, sensor and highly miniaturised medical
device applications are further areas where
ECP ® can become the standard concept for high
performance products launching to Market in the
next two years.”
AT&S: Who are your key competitors?
MB: “In any area, competition is an essential
ingredient to vibrant development, and powers the
ramp up of demand. I am glad to say that we see
strong competitors in our field of expertise too.
The hotbed of laminate packaging is currently split
between Europe and Asia. On the horizon we also
have a new competitive element – the component
packagers – our target is to be number 1!
The AT&S advantage is clear and twofold. First
of all we are already manufacturing at our
dedicated facility in AT&S Hinterberg, and we have
achieved qualification status with global leaders
in the semiconductor business. Secondly we have
reached a level of business understanding that
enables us to move quickly to serial production,
both key advantages in the rapidly changing
Market places in which we operate.”
AT&S: Tell us about the team behind your
business and the leadership challenges …
MB: “Creating a high performance environment is
our clear management objective, and I am glad to
say that by combining home-grown AT&SP talent
with strong additions from outside the company we
are well on track. I am really pleased to see the
team move every day in the right direction.
We often talk about the Advanced Packaging
“speedboat” – direct action, quick to move and
very flexible. People are empowered to do what
they need to do, to get things done.
Our ultimate objective is to provide a strong, simple
and direct process framework that enables our people,
and those working with us to understand what we
want to do, and to ensure that we achieve our goals.”
substrate
Other IC
mounted on
top of package
ecp.ats.net
Embedded IC
Drawing of an IC embedded in
PCB package (courtesy of Yole
Développement). IC embedding
in PCB like AT&S’s ECP allow for
miniature SiP integration of active
with passive circuitry
Passive components
3 D P a c k a g i n g
15

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
COMPANY INSIGHT
ST-Ericsson and CEA-Leti’s
WIOMING prototype shows how to
combine wide IO memory and logic
SoC for future 3D multi-processor
architectures
Pascal Vivet, researcher at CEA-Leti, and Vincent Guerin, senior design engineer
at ST-Ericsson, describe the brand new WIOMING 3D prototype. They also
discuss about the expected benefits of this first of a kind circuit including a wide
IO memory stacked over logic SoC and remaining issues concerning design, test,
as well as supply chain for 3DIC manufacturing.
Vincent Guerin, Senior
Digital Design Engineer,
ST-Ericsson
Pascal Vivet, Researcher,
CEA-Leti, MINATEC
Yole Développement: Could you explain for
our readers the activity and products of ST-
Ericsson and CEA-Leti, as well as the aim of
your collaboration?
Vincent Guerin and Pascal Vivet: ST-Ericsson
is an industry leader in design, development and
creation of cutting-edge mobile platforms and
semiconductors across the broad spectrum of
wireless technologies. Established in 2009, ST-
Ericsson is a 50/50 joint venture uniting the wireless
semiconductor division of STMicroelectronics
(ST-NXP Wireless) and the mobile platform
division of Ericsson (Ericsson Mobile Platforms).
Today, the company is a key supplier to industry
leaders, including mobile operators and device
manufacturers, and we are actively engaged
with seven of the top nine OEM manufacturers by
revenue.
industry and academic research, CEA-Leti is
responsible each year for the development and
transfer of innovative technologies in a wide variety
of sectors: nanotechnologies, RF front-ends,
digital baseband, sophisticated signal-processing
algorithms, multi-processor architecture, low
power design techniques, embedded software, etc.
Thanks to a world-class research infrastructure,
including a nano-characterization platform,
300mm and 200mm lines for nano-electronics
and MEMS, in 8000 m² of clean rooms, CEA-Leti
has developed a complete 3D technology toolbox
comprised of various TSVs (first-, middle-, last-),
Copper Pillar technologies, and 3D stacking
steps (wafer thinning, bonding, debonding, dies
assembly, etc.). The 3D technologies developed
by CEA-Leti are progressively transferred into
ST-Microelectronics fabrication line for the first 3D
technology applications.
CEA-Leti is an applied research center for
microelectronics and for information and healthcare
technologies. Providing a unique interface between
As part of the Cocoa project, the aim of the CEA-
Leti/ST-Ericsson/ST-Microelectronics collaboration
is to develop and validate the 3D design flow in
Package Molding
Metal Stack
Copper Pillar
TSV
Copper Pillar
Metal Stack
Package Molding
Fig. 1: WIOMING prototype concept, including WideIO DRAM stacked over logic SoC
16
3 D P a c k a g i n g

I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
order to pave the way for future products,
using a three-layer 3D-stack test vehicle.
This three-dies stack integrates a WideIO
compatible DRAM memory stacked over two
WIOMING, a multi-core application processor.
This advanced 3D prototype is a first proof of
concept of how to efficiently stack memory
on logic and logic on logic (Fig. 1). The overall
project objective is three fold: i) validate and
ramp-up the 3D technology ii) develop and
validate the 3D design flow and tools, and iii)
develop the required architectural building
blocks, mainly the Wide IO DRAM interface
and a 3D asynchronous Network-on-Chip.
CEA-Leti brings its 3D technology and its
experience in NoC design, integrated in an
existing multi-core processor backbone; ST-
Ericsson brings its knowledge in advanced
DRAM interface and its ability to drive a full
project from application requirements down
to fabrication and test.
YD: At RTI this past December, you
jointly presented the WIOMING circuit
with 3D Wide IO technology. Could you
describe this circuit and its capabilities?
VG & PV: The WIOMING is made of three
stacked dies, integrating a Wide I/O DRAM
memory stacked on top of two identical
SOC logic dies, which incorporates multiple
processor cores on each die. TSVs (throughsilicon
vias) connect these three dies
together. The ST-Ericsson WIOMING provides
12.8GBytes/s of memory bandwidth, which is
a 50% increase over the latest available dual
channel LPDDR2 solutions at 533MHz, and
at 20% less power. Increasing the DRAM
frequency to 266MHz, moving to dual data
rate (DDR) mode and combining with existing
LPDDR3 technology for lower bandwidth
operations will enable us to provide more than
50GBytes/s for future ST-Ericsson products.
This will provide for unprecedented graphics
and CPU performance on smartphones and
tablets.
The WIOMING circuit also integrates a 3D
asynchronous Network-on-Chip (3D-ANoC)
communication infrastructure. The CEA-Leti ’s
3D-ANoC communication infrastructure is
fully implemented in the so-called Quasi-
Delay Insensitive asynchronous logic, which
is a very robust class of un-clocked logic that
brings robustness to Process, Voltage and
Temperature. This Globally Asynchronous
Locally Synchronous 3D architecture does
away with any global timing and clocking
constraints, both in the 2D direction (within
die sub-units) and in the 3D direction through
Fig. 2: Multi-processor backbone architecture,integrating a WideIO interface and a 3D NoC
the TSVs. In order to further reduce the
impact of TSV for 3D NoC connection, the
3D NoC integrates asynchronous serial
links. The 3D-ANoC technology reaches
550MHz maximum operating frequency
in the 2D direction, and 200MHz in the
3D direction. Compared to an equivalent
synchronous NoC, the asynchronous NoC
presents a power consumption reduced
by a ratio of four. Regarding multi-core
architecture, the 3D Network on Chip brings
an efficient packet-based communication
infrastructure to connect the die sub-cores
together, instead of the more traditional onchip
bus interconnect. For testability and
yield purposes, the 3D-ANoC architecture
also integrates some 3D DFT (Design
for Test) structures as well as TSV fault
tolerance scheme. The proposed 3D-ANoC
communication infrastructure allows easy
connection of a large multi-core backbone in
both the 2D and 3D dimensions (Fig. 2).
Together with the high throughput and low
power Wide IO memory interface, it is then
possible to build a 3-die circuit, efficiently
stacking memory on logic and logic on
logic (Fig. 3). This advanced three-dies
3D prototype represents a first proof of
concept that clearly demonstrates how these
technologies can be employed to efficiently
stack memory and logic for future 3D multiprocessor
architectures.
YD : What products has ST-Ericsson
targeted for this wide IO technology?
VG: ST-Ericsson is preparing the WideIO
technology for their Nova application
processors, as well as the integrated LTE
NovaThor digital base band solutions for
tablets and smartphones. The current
generation of products under development
is based on the JEDEC LPDDR3 memory
standard. To significantly increase memory
bandwidth in the next generation of
products, ST-Ericsson is considering a split
memory architecture which makes use
of a combination of WideIO and LPDDR3
memories. For example, a wide IO memory
could be stacked over a SoC including
application processor, baseband, as well
as wide IO memory controller and LPDDR3
memory controller.
YD: A new JEDEC standard for wide
I/O was announced on January 5,
2012. What are your thoughts on this
announcement?
VG & PV: The WIOMING does implement the
Jedec Wide I/O standard published on January
5, 2012. ST-Ericsson and ST-Microelectronics
were able to release a Wide I/O chip at the
Fig. 3: WIOMING 3D stack, including WideIO DRAM and two SoC
17

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
“Increasing the
DRAM frequency to
266MHz, moving
to dual data rate
(DDR) mode and
combining with
existing LPDDR3
technology for
lower bandwidth
operations will
enable us to
provide more than
50GBytes/s for
future ST-Ericsson
products.”
same time the standard specification was published
by Jedec, which reflects the involvement of both
companies in the simultaneous development of the
standard and the device.
YD: You worked in close collaboration with
Cadence to develop new EDA tools. What do
you believe to be the remaining challenges in
design and test for 3D Integration?
VG & PV: With regard to 3D CAD tool and design
flow, CEA-Leti and ST-Ericsson worked in close
cooperation with ST-Microelectronics and Cadence.
The 3D design kit was developed and is maintained
by ST-Microelectronics, with the help of the others.
Cadence provided its latest EDI version, including
a set of 3D features which extend from early floorplanning
to place and route, as well as timing and
power analysis, taking into account all TSV-related
constraints. Cadence’s tool suite is mature enough
to successfully implement all 2D and 3D aspects of
such a complex design.
However, one remaining issue is to manage the
format of the logical models used to describe the
overall 3D stack - in particular with the memory
provider. Different companies using different
design flows interact with each together, which
is a new working model for the digital design and
the signoff of the complete system. Consequently,
there needs to be good cooperation between all
players. Once this cooperation is defined and
agreed, it will enable a complete cross-die design
flow in order to emulate the full system - for
example, but not restricted to, timing, power and
thermal analysis.
Another challenge for 3D primarily concerns power
and thermal analysis. Some initial 3D analyses
have been performed, but the results need to be
validated with silicon measurements. For Designfor-Test
(DFT) for 3D, some classical DFT techniques
such as Boundary Scan have been applied to 3D
signals (WideIO and 3D NoC) using existing DFT
tools, but with some specific add-on to handle the
JTAG protocol within the 3D stack. Such 3D DFT
challenges are currently being studied in the IEEE
3D-Test Working Group. Nevertheless, CAD tool
implementations of the IEEE 3DT-WG proposed
solutions are not yet fully available.
Here’s a table that summarizes which DFT features
have/have not been implemented in the WIOMING:
There are still some test issues to be resolved - in
particular, the diagnosis needs to be reworked for
fast process issue identification during reliability
qualification / yield ramp-up phase / customer
return.
YD: In your opinion, how should the different
players (IDMs, OSATs, Foundries) collaborate to
successfully commercialize wide IO technology?
VG & PV : Only the full engagement of the
OEMs, IDMs and memory suppliers to produce
a commercial product platform will drive the
business model and supply chain requirements
to a workable solution. The consignment models
which are already in place for some products with
integrated KGD memory are the way to go forward,
as it is the only way to make it suitable for the
OSATs, memory suppliers and IDMs. Dedicated
memory test and failure analysis solutions have
to be worked out together in order to enable high
test coverage, quick failure location and low DPPM
in the final product, without generating too much
overhead during the production process.
DFT
Features
DFT
Complexity
ATE
Implementation
complexity
Direct Access Medium High
3D interconnections
Stacked Memory
Full coverage @-speed Diagnosis Full coverage Diagnosis
No No No Yes Yes
Embedded
BIST
High
High
Yes Yes No Yes Address fail
Boundary
Scan
Medium
Low
Yes No Yes No Static only
ATPG High Medium
Some commercial solutions and papers available, but yet untested
for 3D interconnections here while ATPG used on SoC side only
Parametric
No physical access to 3D IOs =>
No individual test measures for DC or AC parameter characterization
IddQ No
www.stericsson.com - www.leti.fr
Vincent Guerin, Senior Digital Design Engineer,
ST-Ericsson
Vincent GUERIN is working for ST-Ericsson since 2009, as technical advisor within
the physical design department. Member of the Technical Staff, he is in charge
of identifying and developing new methodologies to improve Power/Performance/
Area of wireless chips, such as pulse latch bank or advanced CTS techniques. He is
also implicated in the physical implementation of pilot projects and in this context
participates to the development of 3D ICs.
Prior to joining ST-Ericsson, he worked as CAD Support Engineer for Texas
Instruments and as Field Application Engineer for Magma Design Automation.
Pascal Vivet, Researcher, CEA-Leti, MINATEC
Pascal Vivet received his Master of Electronics from University Joseph Fourier
(UJF), Grenoble in 1994. He accomplished his PhD in 2001 within France Telecom
lab, Grenoble, designing an asynchronous Quasi-Delay-Insensitive microprocessor.
After 4 years within STMicroelectronics, Pascal Vivet has joined CEA-Leti in 2003
in the advanced design department of the Center for Innovation in Micro and
Nanotechnology (MINATEC), Grenoble, France. His main topics of interests are focused
on asynchronous logic, Globally-Asynchronous-Locally-Synchronous design, Networkon-Chip
architectures, Low Power design, high level modeling using SystemC/TLM,
Processor Array architectures, and more recently 3D design. He has participated to
the design of three main NoC prototypes, the FAUST, ALPIN and MAGALI circuits. He is
currently involved in the development of 3D prototypes. He is the author or co-author
of more than 40 papers.
18
3 D P a c k a g i n g

IMAGE SENSORS 2012
0.2
0.1
IMAGE SENSORS 2012
FOCUS ON DIGITAL IMAGING
20-22 March, Hotel Russell, London
Keynote Speakers
www.image-sensors.com
0.3
Dr Eric R. Fossum
THAYER SCHOOL OF
ENGINEERING AT
DARTMOUTH, US
Dr Samuel Harvey
Moseley
NASA/GODDARD SPACE
FLIGHT CENTER, US
Dr Nobukazu
Teranishi
PANASONIC
CORPORATION, Japan
Mats Wernersson
SONY ERICSSON, Sweden
0.4
0.5
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automotive, security, defence, space, astronomy and industrial sectors.
Book online with discount code 3dp or find out more about IS2012 at image-sensors.com
IS12full[186x273].indd 1 30/1/12 17:14:47

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
ANALYST CORNER
Market dynamics impact WLCSP
adoption
For connectivity devices, WLCSP became the standard package in 2010, and the
market is poised to continue growing.
Jean-Marc Yannou,
Senior Analyst,
Advanced Packaging,
Yole Développement
Wafer-level chip-scale package (WLCSP)
market growth is expected to climb by
12.6% during the next 5 years, while the
compound annual growth rate (CAGR) for 2010–
2016 appears to be growing much faster for MEMS
and image sensors (at 25%) than for CMOS and
analog ICs (at 7%)—in WLCSP units.
Why? Certain sectors, such as the connectivity
devices used in mobile phones, are nearly 100%
WLCSP now, displacing QFN and BGA packages.
Another reason is that we’re not seeing WLCSPs
being used outside of the mobile world. Very
few are used in PCs or consumer devices, or other
automotive or industrial applications. Growth,
however, is emerging with tablets, which proves that
they are being built to smartphone architectures
rather than PCs.
Certain changes in the mobile phone industry
have had a big impact on WLCSP. Nokia used to
be the world’s OEM leader and biggest champion
of WLCSP, so that’s one reason why its adoption
in ICs failed to grow as quickly as expected during
2010–2011. Second-tier OEMs didn’t take to
WLCSPs; they’re using larger packages that can
be mounted on cheaper assembly lines in China,
rather than WLCSP, which is considered a little
tricky to mount on end-users’ PCBs. In the end, it
always comes down to cost and these second-tier
companies are avoiding making any unnecessary
new investments in equipment.
Who’s leading the way with WLCSP now? Broadcom
shipped 300,000 WLCSP wafers in 2010, which is
a tremendous volume. They needed to work with
five subcontractors—ASE, Nepes, SPIL, STATS
ChipPAC, and now TSMC—because there wasn’t
one who could handle the entire volume.
Where are all of these WLCSPs going? Most notably,
many of Broadcom’s WiFi combo chips are being
used in Apple’s iPhones, iPads, and iPods, as well
as Motorola’s products.
2010-2016 WLCSP unit forecast by end equipment type
We are not seeing WLCSPs being widely used outside of mobile phones and tablets
50 000
45 000
40 000
35 000
30 000
Units
25 000
20 000
15 000
10 000
5000
0
2010
2011 2012 2013 2014 2015 2016
voice phone
smartphones
PMP/MP3
notebooks
feature phones
tablets
set to box
others (medical, automotive...)
(WLCSP Market & Industrial Trends report, January 2012, Yole Développement)
20
3 D P a c k a g i n g

I S S U E N ° 2 2 F e b r u a r y 2 0 1 2
Pad
Redistribution
Copper pillar
The average WLCSP device size
is growing larger: the largest
WLCSP IC on the market, the
Fujitsu MB38C311A, is a 309
I/O 50mm² large WLCSP chip
with PMU, and audio interface
functions (Courtesy of
System Plus Consulting)
These connectivity chips are manufactured in
WLCSP form, but don’t ship this way to the OEMs.
They’re first sent to a module maker, who then
creates a module like an internal piece of PCB,
onto which the WLCSP device is meshed along
with other discrete passive devices. At this point it
becomes difficult to say whether these devices are
actually WLCSP or flip chip. Since they’re bumped
on an internal substrate prior to shipping to the
OEM, they can be considered flip chip. But the
pitch between two consecutive bumps is closer to
WLCSP pitch than flip chip pitch. It actually falls
halfway between WLCSP and flip chip for the most
advanced connectivity modules—because the WLCSP
connectivity die pitch is shrinking (down to 250µm
for the most advanced ones). But it’s excluded from
the flip chip family due to its larger pitch.
In terms of WLCSP adoption, we were surprised
to discover that this package hasn’t been adopted
for applications outside of smartphones, except
for tablets. It’s an inexpensive type of package
and the reason it isn’t experiencing wide adoption
appears to center on the small pitch to the PCB.
Other applications require a larger pitch, so now
the question is: Will we see WLCSP in any other
sectors anytime soon? It’s doubtful—at least in the
near future.
units has grown considerably during the past 3
years. We’re now frequently finding 30mm 2 or
larger devices packaged with WLCSP, which wasn’t
previously the case. These connectivity chips
are mounted on modules, so they may not be
representative of all of the other devices, which
are generally below 10mm 2 . The average die size
with WLCSP is becoming larger with technology
improvements.
For reliability, it’s good to consider smaller devices.
And the move from CMOS 45nm to 28nm should
enable that. But it also means that many devices
will become I/O limited. With the current WLCSP
pitch, there won’t be enough area on the die to
place all of the bumps needed to reach all of the
external interfaces and the PCB. So WLCSP will no
longer be an option for devices that would be I/O
limited. Options are to use fan-out WLCSP or chip
embedding that’s already at 28nm or go back to a
previous package type, namely BGA, flip chip or QFN.
With the adoption of CMOS 28nm, if some of the
fan-in WLCSP technology shifts to fan-out, it may
change the competitive landscape—that’s why
some WLCSP companies, including Teramikros and
FlipChip International, are already investing in chip
embedding technologies.
“The average die
size of WLCSP
packaged units
has grown
considerably
during the past
3 years,” says
Jean-Marc Yannou.
Moving forward, the biggest question is what will
happen to WLCSP and the connectivity devices
as CMOS technology migrates to 28nm from the
current 45nm node. One issue is reliability of
WLCSP. With the move to the next CMOS node
devices can be made smaller, and small devices
are known to be generally more reliable than large
devices with WLCSP. As a matter of fact, WLCSP
usually applies to the smallest of devices, even
though the average die size of WLCSP packaged
Also expect to witness more WLCSP manufacturing
in China. In 2010, 8% of worldwide WLCSP capacity
came from China, which was the same amount
produced in the US and Europe. But China’s share
appears to be growing, with Chinese-based JCAP
expanding its 300mm wafer capacity and Nantong
Fujitsu planning to open a factory for full turnkey
services.
www.yole.fr
Jean-Marc Yannou joined Yole
Développement in 2009 as a market
analyst and project manager for
Advanced Semiconductor Packaging.
Before, he occupied various positions
in the semiconductor industry for
15 years. He worked for Texas
Instruments in test and product
engineering and for Philips (then NXP
semiconductor) where he served as
Innovation Manager for System-inpackage
technologies.
3 D P a c k a g i n g
21

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
WLCSP market trends to watch
in 2012
2012 should be a robust year for the WLCSP market, with interesting supply chain
trends emerging.
Lionel Cadix,
Market & Technology
Analyst,
Advanced Packaging,
Yole Développement
There are essentially two wafer-level chip-scale
package (WLCSP) supply chains: One for fan-in
WLCSPs, which are considered “regular” WLCSPs
without through silicon vias (TSVs), and a separate
one for 3D WLCSPs, which are WLCSP packages
with multiple levels of dies or lids and TSVs. 3D
WLCSP applies to MEMS and to many CMOS image
sensors.
In the 3D WLCSP platform, 80% of capacity is split
60/20 between wafer-level packaging houses and
integrated device manufacturers (IDMs).
The top three device categories for WLCSPs are
analog and mixed-signal, wireless connectivity,
and image sensors. The top three device types
include a Bluetooth/WiFi/FM combo, CMOS image
sensors, and DC/DC converters.
~12% for 2010-2016, despite decreasing prices.
Growth, however, won’t occur equally across all
device types—expect a low CAGR for ICs, and a
high one for MEMS.
At least 25 billion WLCSP devices are targeted
for shipment in 2012, driven primarily by wireless
connectivity for mobile/telecom applications,
followed by CMOS image sensors.
The use of fan-in WLCSP for connectivity devices
in handsets is becoming increasingly standardized;
in 2012 it will approach 100%. Biggest customer?
Broadcom. Other solutions used for the same
application, such as QFN or BGA solutions, are now
being sidelined by fan-in WLCSP.
Trends
There are two key WLCSP trends worth mentioning.
“The top three
device categories
for WLCSPs are
analog and mixedsignal,
wireless
connectivity, and
image sensors. The
top three device
types include a
Bluetooth/WiFi/
FM combo, CMOS
image sensors,
and DC/DC
converters,”
explains Lionel Cadix.
Market outlook for 2012
The global WLCSP market value, including wafer
level service, die level service and test, exceeded
B$1.5 in 2011, with an expected CAGR value of
%
60
50
40
30
20
10
0
MEMS, sensors and BAW
track pad controller
USB controller
CMOS image sensors
GPS
magnetometer
MOSFETs
touch screen controller
Audio/video codec
microcontroller
First, IDMs want to reduce their dependence
on packaging subcontractors who didn’t invest
enough in 8 and 12 inch. capacities during the
2008-2009 economic downturn. As a result, IDMs
are creating internal capacity for fan-in WLCSP.
Fan-in WLCSP 2010-2016 unit CAGR (%) by device type
BT+WiFi+FM combo
logic gates
Audio power amplifiers + video drivers
temperature sensor
others (medical, automotive, FPGA,
ctrl…)
PMU/PMIC
ESD/EMI IPD
DC/DC converter / LDO
Amplifier / switch / RF power detector /
voice coil motor driver IC, …
LED driver Ics
EEPROM/flash
bluetooth+FM
(WLCSP Market & Industrial Trends report, January 2012, Yole Développement)
22
3 D P a c k a g i n g

I S S U E N ° 2 2 F e b r u a r y 2 0 1 2
Texas Instruments, for example, is one IDM with
significant WLCSP production capacity. TI invested
heavily in 300mm bumping at their Clark facility in
the Philippines in 2010.
3000
WLCSP total market value (M$)
Second, with cost pressure clearly threatening the
integrated position of the OSATs within the WLCSP
space, some wafer bumping houses are considering
climbing the value chain to provide full turn-key
services to their customers—by developing wafer
test and back-end steps.
Company highlights
M$
2500
2000
1500
CAGR ~ 12%
As far as individual companies making bold moves
in the WLCSP market, the more noteworthy
highlights include:
1000
TI invested significantly in 300 mm bumping for
flip chip and WLCSP at their Clark facility in 2010.
500
STMicroelectronics is currently building a midend
facility in Singapore for flip chip bumping,
fan-in WLCSP, FOWLP, and 2.5D glass and silicon
interposer substrates.
TSMC stepped up with their first investment in fanin
WLCSP. Their 300mm fab was built under the
name “Xintec/TSMC,” but since 2011, the Hsinchu,
Taiwan-based line has been fully operated by TSMC
and is serving customers with full turn-key fan-in
WLCSP services—including test and back-end—on
300mm wafers.
In Japan, Casio Micronics and Tera Probe formed a
new company called Teramikros, which is the first
in the world to attempt to become a pure-play fanin
WLCSP contract manufacturing service provider.
Teramikros is now licensing its fan-in technology
and qualifying a Chinese OSAT, Nantong Fujitsu,
for Q2 2012.
STATS ChipPAC completed expansion of its 300mm
operations in Taiwan, taking additional capacity
online in 2011. This was the most significant OSAT
investment in WLCSP during the past 3 years.
And, JCAP in China is expanding its 300mm fanin
capacities and moving to 3D WLCSP services,
including via-last TSV for MEMS and CMOS image
sensor packaging on 200mm wafers.
Manufacturing locations
If you guessed that the main manufacturing
location for WLCSP is still Taiwan, you’re right,
with 39% of all processed wafers originating there,
followed by Japan and Europe.
For fan-in WLCSP, the big players are Taiwan-based
ASE in 200mm wafers and SPIL in 300mm wafers.
0
2010 2011 2012 2013 2014 2015 2016
(WLCSP Market & Industrial Trends report, January 2012, Yole Développement)
For 3D WLCSP, the top players are Taiwan-based
Xintec in 200mm wafers (61% of processed wafers)
and France-based STMicroelectronics in 300mm
wafers (68%).
Currently, there’s an emerging manufacturing
shift to China. What’s behind it? In 2010, most
WLCSP fab capacity was booked due to higherthan-expected
demand from IC companies. OSATs
and wafer bumping houses didn’t invest in enough
extra capacity, which led to price tension in the
market and created a situation in which some
analog and mixed-signal companies couldn’t ramp
up new products in WLCSP because of OSATs’ high
pricing for full turn-key WLCSP services. Afterward,
several companies shifted to Chinese WLCSP
players to find extra capacity at competitive prices.
Pursuit of the fan-in WLCSP market
Company to pay close attention to in the WLCSP
space include: Powertech Technology Inc. (PTI).
Taiwan-based PTI is on its way to becoming
another big challenger in the WLCSP space. PTI is
building a mid-end factory to supply open-contract
manufacturing services based on flip chips with
copper pillars/fan-in WLCSPs/3DICs and TSVs.
2012 will certainly be interesting for this company—
and the entire market!
www.yole.fr
Lionel Cadix joined Yole
Développement after the completion
of several projects linked to the
characterization and modeling of
high density TSV and 3DIC chip
stacking in collaboration with CEA-
Leti and STMicroelectronics during
his PhD. He is author of several
publications and 8 patents in the
field of 3D Integration.
3 D P a c k a g i n g
23

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
Moving 3D IC forward with the
standardization of wide IO DRAM
3D IC technology has taken a giant step forward with the recent announcement
by JEDEC that it has issued standard JESD229 for Wide I/O mobile DRAM.
Participants in the effort included many of the major global players including
Samsung, Elpida, Hynix, Micron, Qualcomm, Nokia, ST Ericsson, TI, Intel, AMD,
Apple and others.
Dr Phil Garrou,
Senior Analyst,
Advanced Packaging,
Yole Développement
JEDEC JESD229 for Wide I/O mobile DRAM
The purpose of this standard is to define the
minimum set of requirements for JEDEC compliant,
1 GBb through 32 GbB DRAM devices with four,
128b wide channels using direct chip-to-chip attach
methods between 1 to 4 memory devices and a
controller device. The standard defines the Wide
I/O specification including features, functionality,
AC and DC characteristics, packages, and pin
signal assignments.
The 512-bit memory interface has four independent
128 bits wide channels each operating at clock
speeds to 266 MHz resulting in a total bandwidth
of 17 GBb/s for wide I/O SDRAMs (4.26 GBb/s/
channel). The specification supports as many
as four memory banks per channel, allowing die
stacking of up to four wide I/O SDRAM die. The
specification calls for 1.2V signal levels.
Wide IO electrical and LMI (Logic Memory Interface)
specifications are shown below:
• Large bus interface (512 bits) at low frequency
(200 MHz) in SDR
• 4 independent and fully asynchronous channels
• BW = 12.8 GBps (200 Mbps per pin)
• VDD1 = 1.8V, VDD2 = 1.2V, VDDQ = 1.2V
• Low Power Features: PASR, Auto TCSR
• Balls allocated for future DDR extension
• Total number of balls including supply: 1200
(193/ch signal)
• Density: up to 32 Gbit monolithic
• Up to 4 DRAM dice stacked on top of the mobile
processor
5.27 mm
• Boundary Scan
• IO physical location
– Each channel has 6 rows and 50 columns
– 40µOm min pad/bump/TSV pitch
JESD229 does not standardize the bonding
configuration between the memory and logic chips
– i.e. F2F, B2F, side-by-side with interposer, or
stacked memory on top of logic. JESD229 may be
downloaded on JEDEC website (ww.jedec.org).
The next generation of this Wide I/O specification,
already underway, promises to deliver eight times
the performance and support 2.5D assembly.
Wide IO Required for Future
Smartphones and Tablets
Sophie Dumas, from the CTO office of ST Ericsson
and Chairman of the JEDEC subcommittee for Low
Power Memories, indicates that Wide I/O mobile
DRAM using 3D stacking with TSV will provide
“double the bandwidth at the same power, or can
cut power in half at the same bandwidth” and
compared to LPDDR2 and LPDDR3 it is particularly
well suited for applications requiring increased
memory bandwidth up to 17GB/second, such as
3D gaming, high resolution displays (1080p H264
video, pico projectors), and user multitasking»
Dumas continues that “…display resolution will
double for smartphones and quadruple for tablets
in the near future, both requiring significant
increases in memory bandwidth”.
Dumas and the JEDEC committee expect Wide IO
to be in mass production by early 2014.
nns
0.54 mm
ADDR
CMD
DQ
DQS/DM
6 column
spacing
2 ~ 3
row spacing
Wide IO electrical and LMI (Logic Memory Interface) specifications (Courtesy of JEDEC)
24
3 D P a c k a g i n g

I S S U E N ° 2 2 F e b r u a r y 2 0 1 2
2011
LPDDR2
3.2 GBps
2012
LPDDR2
4.3 GBps
2013
LPDDR3
6.4 GBps
2014
WideI0
12.8 GBps
Expected Device
Mass Production
Mobile Memory Std Wide IO LPDDR3 LPDDR2
Data IO width (bits) 512 32 32
Max data transfer rate per 10 (Mb/s) 200 1600 800,1066
Max data transfer rate per device (Gb/s) 12.8 6.4 3.2, 4.3
Relative power comsumption
Wide IO adoption already underway
For mobile applications Wide IO DRAM die is stacked on top of
the mobile application processor. Details on such structures have
recently been described in the ST Ericsson, Cadence, CEA Leti
program known as Wioming.
In early 2011 Samsung announced wide IO DRAM and the goal of
providing 20 nm, 4Gb wide I/O mobile DRAM sometime in 2013..
In December 2011, Elpida announced sample shipments of 4Gbit
Wide-IO, announcing volume production for these devices in 2012.
At the recent IC Packaging Technology Expo at NEPCON Japan
Renesas announced that they will apply TSV technology to its
mobile SoCs so that they will support Wide I/O DRAM starting with
mobile phone products. The DRAM will be stacked on the back of
the SoC via 1,200 microbumps. The company plans to contract out
the production of advanced SoCs to a silicon foundry as well as the
production of TSV.
Early in 2011 Micron released details on its hybrid memory cube
(HMC) technology and the consortium they created with Samsung to
collaborate on the implementation of an open interface specification
for the HMC technology.
Open-Silicon, a fabless ASIC designer is developing the controller
IP for HMC based on their Interlaken controller IP ( a high-speed,
chip-to-chip interface protocol). Based on Micron’s specifications,
the logic controller layer of HMC, complete with TSV, will be
manufactured by IBM in East Fishkill NY, using 32nm, high-k metal
gate process technology. Micron will fabricate the DRAM arrays
based on their 3x nm process in their fabs. Micron will also assemble
their memory layers and the IBM logic control layer at their R&D
production line in Boise, Idaho.
For those interested in following the progress of 3D standardization,
Wiki Sematech is tracking and continually updating here
(http://wiki.sematech.org/3D-Standards-List).
www.yole.fr
Phil Garrou joined Yole Développement forces as senior technical advisor
in the fields of advanced packaging. Phil as more than 20 years extensive
experiences in the semiconductor industry where he mainly served as global
marketing manager for DOW Chemical’s BCB polymer business.
3 D P a c k a g i n g
25

F e b r u a r y 2 0 1 2 I S S U E N ° 2 2
W h a t ’ s I n s i d e ?
OmniVision’s VGA wafer-level
camera
Whether it’s for the main camera of low-cost phones or the front-facing camera
of high-end phones, low-cost, low-resolution camera modules are extremely
important.
Wafer-level cameras
In order to manufacture low-cost camera modules,
the main cost drivers -- the image sensor, the
optical module and the fixture used to assemble the
module to the phone board -- have to be reduced to
a strict minimum.
The image sensors lend themselves rather well
to low-cost manufacturing due to their waferlevel
manufacturing approach. With this approach
it is possible to manufacture optical lenses at
the wafer-level, thus creating a very low-cost
wafer-level optical module (or wafer-level optics,
WLOptics). Another benefit of WLOptics is their
reflow-compatible materials. By eliminating the
plastic lenses used in standard optical modules, the
camera modules become compatible with reflow
soldering, and thus can be integrated at the same
time as the other surface mount components on the
phone board.
One way to optimize this reflow compatibility is to
package the image sensor at the wafer-level by
redistributing the pads to the back side. This also
reduces the camera module area to the image
sensor area.
OmniVision CameraCube
The OVM7692 is a VGA reflowable camera module
which integrates a Wafer-Level Packaged CMOS
Image Sensor and Wafer-Level Optics. The camera
module is provided in a 2.8 x 3.2 x 2.5 mm 25-pin
package, and integrates a 1.75µm pixel CMOS Image
Sensor (CIS), ref. OV289AA from OmniVision, which
is manufactured by TSMC using a CMOS technology
with a 0.11µm process.
Glass
wafer #2
with lens #1
and aperture
Glass
wafer #3
(Spacer)
Glass
wafer #4
with lens #2
Glass
wafer #5
(Carrier wafer)
CIS
Glass wafer #1
with IR filter
Solder ball
Wafer-level optics
OmniVision OVM7692 cross-section
(Courtesy of System Plus Consulting)
A pioneer of the CMOS Image Sensor industry,
OmniVision released its latest wafer level camera,
the OVM7692, in 2010.
The wafer-level optical module of the OVM7692
is currently outsourced to VisEra Technologies in
Taiwan. VisEra was founded in December 2003 as
a joint venture between TSMC and OmniVision. On
June 30, 2011, OmniVision paid $45M for VisEra’s
WLOptics manufacturing operations, and expects
to close the transaction in the second quarter of
2012. According to OmniVision, this transaction
will allow for streamlining the production process,
consolidating the supply chain, expanding the
production capacity and reducing the cost.
Glass wafer #1
Glass wafer #2
Lens #1
Lens #2
Glass
wafer
#3
Glass wafer #4
OmniVision OVM7692 CameraCubeChip
(Courtesy of System Plus Consulting)
OVM7692 Wafer-level optics cross-section
(Courtesy of System Plus Consulting)
26 3 D P a c k a g i n g

I S S U E N ° 2 2 F E B R U A R Y 2 0 1 2
The WLOptics of the OmniVision CameraCube
consists of an assembly of four glass wafers.
The first glass wafer, on top of the module, holds
an IR filter (consisting of layers of Niobium oxide
sandwiched with layers of Silicon oxide). The
second glass wafer holds the first lens. Next up is
a spacer glass wafer, etched by powder blasting,
which separates the second glass wafer from the
fourth glass wafer -- which holds the second lens.
The lenses are made with a UV curable polymer
and are manufactured with a replication process.
A plastic tool (likely Polydimethylsiloxane --PDMS
silicone) molded into a master is used to imprint the
polymer lenses. Each master can be used to make
a large number of PDMS tools, and each PDMS tool
can be used to imprint a large number of lenses.
Wafer-level packaging
The CMOS Image Sensor (CIS) is Wafer-Level
Packaged (WLP) by Xintec, using a ShellCase RT
process.
Xintec obtained a license for the ShellCase CSP
technology from ShellCase Ltd. in 2000 (Tessera
has since acquired ShellCase Ltd. and now licenses
the ShellCase technology to Xintec). The ShellCase
process consists of a redistribution of the CIS pads
to the back side through the edge of the die, using
a “T-contact”.
The packaging process begins with the bonding
of a glass carrier substrate to the CIS wafer.
Strengthened by its carrier substrate, the CIS wafer
Black
coating
T-contact
Silicone
epoxy
OVM7692 ShellCase CIS WLP cross-section
(Courtesy of System Plus Consulting)
can be thinned down to 130µm, and vias can be
etched all around each CIS die. These vias are then
filled with a conductive aluminum layer. Finally, a
protective encapsulation is created and solder balls
are produced.
Cost structure
Glass Carrier wafer
Metal layer
(Silver)
Silicone epoxy
Cavity
Lead
CMOS Image Sensor
Solder
bump
Wafer-level manufacturing of all camera module
elements results in a significant reduction of the
production cost – in fact, the OmniVision OVM7692’s
total production cost is estimated to be under $1.
Compared to standard camera modules where the
cost is equally distributed between the three main
cost drivers, the wafer-level camera module cost
is especially impacted by the image sensor, which
equates to about 50% of the total manufacturing
cost.
Romain Fraux
System Plus Consulting
Romain Fraux,
Electronics Cost
Engineer,
System Plus
Consulting
Romain Fraux is
Project Manager
for Reverse Costing
analyses at System Plus Consulting.
Since 2006, Romain is in charge of
costing analyses of MEMS devices,
Integrated Circuit and electronics
boards. He has significant experience
in the modeling of the manufacturing
costs of electronics components.
Romain has a BEng from Heriot-Watt
University of Edinburgh, Scotland and
a master’s degree in Microelectronics
from the University of Nantes, France.
OVM7692 camera module cost
breakdown
Camera Module
100%
90%
80%
70%
60%
Final test + Scrap
(Omnivision)
7%
WL-Optic +
Assembly (VisEra)
25%
CIS ShellCase
WLP (Xintec)
19%
Glass
wafer #1
Glass
wafer #2
Glass
wafer
#3
Lens #1
IR filter
AP layer
Wafer-level
Optics
50%
Lens #2
40%
Glass
wafer
#4
Black
coating
30%
20%
CIS Manufacturing
(TSMC)
49%
CMOS Image
Sensor
Glass
Wafer #5
(carrier wafer)
Imaging Area
with micro-lenses
Cavity
T-Contact
Wafer-level
Packaging
10%
0%
OVM7692 structure & cost breakdown (Courtesy of System Plus Consulting)
3 D P a c k a g i n g
27

2012 IEEE
IntErnatIonal IntErconnEct
tEchnology confErEncE
IITC
Innovations In Interconnections
The 15th annual IITC, sponsored by the IEEE Electron Devices
Society, is the semiconductor industry’s premier conference for
interconnect technology. It provides a forum for professionals
from industry, academia and national laboratories in
semiconductor processing, advanced materials, equipment
development, and interconnect systems to present and discuss
exciting new science and technology.
Keynote presenters and invited speakers include:
Mike Mayberry, Vice President of Research, Intel Corp
Bill Dally, Chief Scientist, nVIDIA
Subu Iyer, IBM Fellow responsible for 3D IC
Michael van Buskirk, CTO of Adesto/former CTO of Spansion
Dan Edelstein, IBM Fellow responsible for BEOL
Axel Preusse, Fellow at GLOBALFOUNDRIES
Jean Marc-Yannou, Analyst focusing on 3D, Yolé Development
for complete conference and
registration information for
IItc 2012 visit:
http://www.his.com/~iitc/
DoublEtrEE hotEl
San JoSE, ca
JunE 3 – 6, 2012
The northern California venue
is one of three international
locations for this important
technology conference, which
rotates among them annually.
Short courSE
JunE 3, 2012
a one-day short course
on leading-edge
interconnect technology
and emerging materials.
ExhIbItS &
SupplIEr
SEmInarS
new products,
processes,
and materials
will be exhibited
at the conference
and supplier
seminars will be
held in the evenings.
poStEr
SESSIon:
featuring papers
from young Engineers
& Students
IItc tEchnIcal
program
materials &
unit processes
process Integration
characterization
reliability
chip-package
Interaction (cpI)
3D Integration
novel Systems
& packaging
novel materials
& concepts,
back-End memories
& mEmS
fine grain 3D
contacts & local
Interconnects
Interconnects
for biological
applications
networks-on-chip
circuits for
high-Speed &
low-power
Signaling
II043 IITC 2012-Yole Media Partnership Ad Dev & Mat.indd 1
2/2/12 11:31 AM

F E B R U A R Y 2 0 1 2 I S S U E N ° 2 2
How can you capture 60%
and over the LED cost?
LED Packaging
2011 edition
Discover the NEW report on
i-Micronews.com/reports
About Yole Développement
Beginning in 1998 with Yole Développement, we have grown to become a group of companies providing market research, technology analysis,
strategy consulting, media in addition to fi nance services. With a solid focus on emerging applications using silicon and/or micro manufacturing
Yole Développement group has expanded to include more than 40 associates worldwide covering MEMS, MedTech, Advanced Packaging, Compound
Semiconductors, Power Electronics, LED, and Photovoltaics. The group supports companies, investors and R&D organizations worldwide to help
them understand markets and follow technology trends to develop their business.
CUSTOM STUDIES
• Market data, market research and marketing analysis
• Technology analysis
• Reverse engineering and reverse costing
• Strategy consulting
• Corporate Finance Advisory (M&A and fund raising)
MEDIA
• Critical news, Bi-weekly: Micronews, the magazine
• In-depth analysis & Quarterly Technology Magazines: MEMS Trends – 3D Packaging – iLED – Power Dev’
• Online disruptive technologies website: www.i-micronews.com
• Exclusive and editorial webcasts
• Live event with Market Briefings
CONTACTS
For more information about:
• Services : Jean-Christophe Eloy (eloy@yole.fr)
• Reports: David Jourdan (jourdan@yole.fr)
• Media : Sandrine Leroy (leroy@yole.fr)
TECHNOLOGY & MARKET REPORTS
• Collection of reports
• Players & market databases
• Manufacturing cost simulation tools
• Component reverse engineering & costing analysis
More information on www.yole.fr
Editorial Staff
Managing Editor: Jean-Christophe Eloy - Editor in chief: Jean-Marc Yannou - Editors: Jérôme Baron,
Lionel Cadix, Phil Garrou, Sally Cole Johnson - Media & Communication Manager: Sandrine Leroy -
Media & Communication Coordinator: Camille Favre - Production: atelier JBBOX
29 3 D P a c k a g i n g