Editorial

J. Antonio Álvarez y Michael Lindig B.
fracta => fracta_mul,
fractb => fractb_mul,
exp_out => exp_mul, -- FMUL exponent output => registered)
sign => sign_mul, -- FMUL sign output (registered)
sign_exe => sign_exe, -- FMUL exception sign output (registered)
inf => inf_mul, -- FMUL inf output (registered)
exp_ovf => exp_ovf, -- FMUL exponnent overflow output (registered)
underflow => underflow_fmul_d
);
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
sign_mul_r co_d );
-- Add/Sub
-- Fraction A input
-- Fraction B Input
-- SUM output
-- Carry Output
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
fract_out_q clk, opa => fracta_mul, opb => fractb_mul, prod
=> prod);
------------------------------------------------------------------------
--
-- Divide
--
PROCESS (fracta_mul)
BEGIN
IF fracta_mul(22) = '1' THEN div_opa_ldz_d