Power Conversion - SmartData

Application Note 

AN-SMPS-1683X – 1 

Power Conversion 

Version 1.2 , May 2000 

CoolSET 

TDA16831 ... 34 for OFF – Line Switch Mode Power Supplies 

Authors: Harald Zöllinger 

Rainer Kling 

Published by Infineon Technologies AG 

http://www.infineon.com 

N ever stop thinking

Contents: 

TDA1683X for OFF – Line Switch Mode Power Supplies 

CIRCUIT DESCRIPTION............................................................................................ 2 

OPERATING PRINCIPLES ........................................................................................ 2 

SMPS CALCULATION SOFTWARE FLYCAL .......................................................... 2 

CIRCUIT DIAGRAM: .................................................................................................. 4 

DESIGN PROCEDURE 

DEFINE INPUT PARAMETERS:....................................................................................... 5 

INPUT DIODE BRIDGE (BR1):....................................................................................... 5 

DETERMINE INPUT CAPACITOR (C3):............................................................................ 5 

TRANSFORMER DESIGN (TR1): ................................................................................... 7 

WINDING DESIGN: ...................................................................................................... 8 

OUTPUT RECTIFIER (D1):.......................................................................................... 10 

OUTPUT CAPACITORS (C5 & C9): ............................................................................. 10 

OUTPUT FILTER (L3 & C9): ...................................................................................... 11 

VCC – SUPPLY:....................................................................................................... 11 

CALCULATION OF SNUBBER NETWORK:...................................................................... 12 

CALCULATION OF LOSSES: ........................................................................................ 13 

VOLTAGE REGULATION LOOP: ................................................................................... 15 

REGULATION LOOP:.................................................................................................. 16 

TRANSFER CHARACTERISTICS OF REGULATION LOOP ELEMENTS: ................................ 16 

TRANSFORMER CONSTRUCTION ................................................................................ 21 

LAYOUT RECOMMENDATION:.............................................................................. 22 

OUTPUT POWER TABLE........................................................................................ 23 

SUMMARY OF USED NOMENCLATURE ............................................................... 24 

PARAMETERS........................................................................................................... 24 

REFERENCES ......................................................................................................... 26 

Page 1 of 28 AN-SMPS-1683X – 1 

V1.2

Circuit Description 


The TDA 16831 ... 34 is a current mode pulse width modulator with an integrated CoolMOS 

Transistor. It meets the need for minimum external control circuitry for a flyback application. 

Current mode control means that the current (IPRI) through the CoolMOS Transistor and flyback 

transformer is compared with a feedback signal derived from the output voltage (VOUT) of the flyback 

application. The result of that comparision determines the on time (tON) of the CoolMOS Transistor. 

To minimize external circuitry the current sense circuitry is integrated within the CoolSET controller. 

The oscillator resistor and capacitor which determine the switching frequency are also integrated, 

reducing the external connections. Special efforts have been made to compensate temperature 

dependancy of clock frequency and to minimize the number of the passive components. 

Operating Principles 

The TDA 16831 ... 34 is designed for a current mode flyback configuration in discontinous current 

mode. 

The control circuit has a fixed frequency and the duty cycle (D) of integrated CoolMOS Transistor is 

controlled to maintain a constant output voltage (VOUT). 

The diagram below (Fig. 1) shows the input voltage (VDC IN) and the primary (IPRI) and secondary (ISEC) 

transformer current. 

When the CoolMOS Transistor is turned on, the start of all windings on the transformer will go positive. 

The rectifier diode (D1) on the secondary side will be reverse-biased and will not conduct. Therefore 

no current will flow in the secondary while the CoolMOS Transistor is turned on. During this phase, 

energy is being stored in the primary winding inductance and the transformer may be treated as a 

simple series inductor. The diagram shows (Fig. 1) that there will be a linear increase of primary 

current (IPRI) while the primary CoolMOS Transistor is on. 

When the CoolMOS Transistor is turned off, the voltage will reverse on all windings (flyback action) 

until clamped by the secondary side widing through the secondary rectifier diode. Now the secondary 

rectifier diode (D1) will conduct, and the magnetizing energy in the core will now transfer to the 

secondary side during the reset interval. 

This current will decrease from it’s peak value to zero, as shown in the diagram (ISEC). In this period 

the complete stored energy in the primary inductance will be transferred to the secondary side 

(neglecting losses), before the next store cycle starts. The secondary voltage (VSEC) is “reflected” back 

(VR) through the transformer turns ratio to the primary winding and added to the input voltage 

(VDC IN + VR). Additional transient voltage may appear on the primary winding due to energy stored in 

uncoupled “leakage” inductance in the primary winding which isn’t clamped by the secondary side 

winding. If the flyback current does not reach zero before the next “on” – Cycle the converter is 

operating in continous current mode. When this system reverts to the continous operation, the transfer 

function is changed to a two pole system with low output impedance and additional design rules 

become important. 

SMPS Calculation Software FLYCAL 

FLYCAL is an EXCEL spread sheet with all needed Equations for calculating your SMPS easier. 

FLYCAL corresponds with the calculating example in this application note, starting at page 5. You only 

have to put in the main parameters of your application in FLYCAL and to follow 

(like the calculating example in this application note) step by step. FLYCAL contents all used 

equations from the example with the same consecutive numbering. 


V1.2

Voltage 

Current 


Voltage and Current waveforms in discontinous mode operation: 

VDC IN min + VR 

VDC IN min 

IPEAK 

IPEAK 

Fig. 1 

Duty Cycle: D = 0,5 Duty Cycle: D < 0,5 

VDC IN = VDC IN min VDC IN > VDC IN min 

ISEC 

IPRI 

0 T 

tON 

Light load 

tOFF 

Full load 

Duty Cycle: 

t 

D = 

T 

VIN + VR 

ON 

VDC IN 

IPEAK IPRI 

IPEAK 


V1.2 

0 

ISEC 

tON tOFF T

Circuit Diagram: 

Fig. 2 



V1.2


Design Procedure for fixed frequency Flyback Converter with 

TDA16831 ... 34 operating in discontinuous current mode. 

Define input Parameters: 

Procedure Example 

Minimal AC input voltage: VAC min 

Maximal AC input voltage: VAC max 

Line frequency: fAC 

Max. Output power: POUT max 

Min. Output power: POUT min 

Output voltage: VOUT 

Output ripple voltage: VOUT Ripple 

Reflection voltage: VR 

Estimated efficiency: η 

DC ripple voltage: VDC IN Ripple 

Auxiliary Voltage: VAux 

Optocoupler Gain: GC 

Used CoolSET 

There are no special requirements imposed on the 

input rectifier and storage capacitor in the flyback 

converter. The components will be selected to meet 

the power rating and hold-up requirements. 

Maximum input power: 

POUT 

max 

P IN MAX = (Eq 1) 

η 

Input Diode Bridge (BR1): 

P 

IN MAX 

I PRMS = 

(Eq 2) 

VAC 

min ⋅ cosϕ 

V DC max PK = VAC 

max ⋅ 2 

(Eq 3) 

Determine Input Capacitor (C3): 

Minimum peak input voltage at ”no load” condition 

V DC min PK = VAC 

min ⋅ 2 

(Eq 4) 

85V 

270V 

50Hz 

40W 

1W 

12V 

0,05V 

100V 

0,8 

20V 

12V 

1 

TDA16834 for 40W @ 25°C 

PIN MAX 

I PRMS 

VDC max PK 

VDC min PK 

40W 

= = 50W 

0, 

8 

50W 

= = 0, 

98 

85V 

⋅0, 

6 

= 270V 

⋅ 

= 

85V 

⋅ 


V1.2 

A 

2 = 382V 

2 = 120V

V = V min −V 


DC min DC PK Ripple 

(Eq 5) 

Calculating discharging time at each half line cycle: 

V 

arcsin 

V 

= 5ms 

⋅ 1+ 

90 

 

 

DC min 

DC min PK 

T D 

(Eq 6) 

Required energy at discharging time of C3: 

W P ⋅T 

IN 

= (Eq 7) 

IN MAX 

D 

Calculating input capacitor value CIN: 

C 

IN 

V 

2 ⋅W 

= (Eq 8) 

2 

DC min PK 

IN 

2 

VDC 

min 

− 

Alternative a rule of thumb on choosing CIN: 

Input voltage CIN 

115V 2µF/W 

230V 1µF/W 

85V ...270V 2 ...3µF/W.................... 

Postcalculation of input Capacitore: 

Select a capacitor out of Epcos Databook 

of Aluminium Electrolytic Capacitors. 

The following types are preferred: 

For 85°C Applications: 

Series B43303-........ 2000h lifetime 

B43501-........ 10000h lifetime 



B43505-........ 5000h lifetime 

V 

DC 

= 

V 

2 

DC min PK 

2 ⋅W 

− 

C 

min (Eq 9) 

IN 

IN 

 

we choose a ripple voltage of 20V 

VDC min 

T D 

W IN 

= 120V 

− 20V 

= 100V 

100V 

 

arcsin 

= 5 ms • 1+ 

120V 

= 8, 

1ms 

90 

 

 

= 50 W ⋅8, 

1ms 

= 0, 

41Ws 

2⋅ 

0, 

41Ws 

CIN = 

= 185µ 

F 

2 

2 

14400V 

−10000V 

µ F 

50 W ⋅3 

= 150µ 

F 

W 

We choose 180µF 400V (based on Eq 8) 

VDC min 

= 

2 0, 

41Ws 

14400V 99, 

2V 

180 F 

2 ⋅ 

− = 

µ 


V1.2

Transformer Design (TR1): 


Calculation of peak current on primary inductance: 

I 

2 ⋅ PIN 

V ⋅ D 

LPK = 

MAX 

(Eq 10) 

DC min max 

Dmax 

= I ⋅ 

(Eq 11) 

3 

I LRMS LPK 

Calculating of primary inductance within limit of 

maximum Duty-Cycle : 

L 

P 

= 

D 

max 

I 

⋅V 

LPK 

DC min 

⋅ f 

Select core type and inductance factor (AL) from 

Epcos ferrite Databook or CD-ROM 

Passive Components. 

(Eq 12) 

Fix maximum flux density: 

Bmax ≈ 0,2T ...0,3T for ferrite cores depending on core 

material. 

We choose 0,2T for material N27 

The primary turns can be calculated as: 

L 

P 

N P = (Eq 13) 

AL 

Number of secondary turns can be calculated as: 

( V + V ) 

N P ⋅ OUT FDIODE 

Ns = (Eq 14) 

V 

R 

Dmax = 0,5 (see datasheet TDA16834) 

I LPK 

I LRMS 

L P 

2 ⋅ 50W 

= = 2, 

02 

99, 

2V 

⋅ 0, 

5 


V1.2 

A 

0, 

5 

= 2 , 02A 

⋅ = 0, 

83 

3 

0, 

5 ⋅99, 

2V 

= 

= 246µ 

H 

3 

2, 

02A 

⋅100* 

10 Hz 

Selected core: E 32/16/9 

Material = N27 

AL = 244 nH 

s = 0,5 mm 

Ae = 83 mm 2 

AN = 108,5 mm 2 

lN = 64,4 mm 

weight ≈ 30g 

PV = 190mW/g (200mT, 100kHz, 100°C) 

N P 

= 

246µ 

H 

244nH 

= 

31, 

75 

we choose Np = 32 turns 

32 ⋅ 

Ns = 

( 12V 

+ 0, 

7V 

) 

100V 

we choose NS = 4 turns 

= 

A 

turns 

4, 

06


Number of auxiliary turns can be calculated as: 

N 

N 

⋅ 

( V + V ) 

P Aux FDIODE 

Aux = (Eq 15) 

VR 

Postcalculation of primary inductance, primary peak 

current, max. flux density and gap: 

P 

2 

P 

L = N ⋅ A 

I 

LPK 

V 

= 

l 

DC min 

P 

⋅ D 

Lp ⋅ f 

e 

max 

(Eq 16) 

(Eq 17) 

LP 

⋅ I LPK 

Bmax 

= 

(Eq 18) 

N ⋅ A 

4⋅π ⋅10 

s = 

L 

−7 2 

⋅ N P 

P 

⋅ A 

Winding Design: 

(see also page 21 

Transformer Construction) 

e 

(Eq 19) 

The primary winding of 32 turns has to be split into 

16+16 turns in order to get best coupling between 

primary and secondary winding. 

The effective bobbin width and winding cross section 

can be calculated: 

BW e 

A 

Ne 

= BW − 2 ⋅ M 

(Eq 20) 

AN 

⋅ BWe 

= (Eq 21) 

BW 

Calculate copper section for primary and secondary 

winding: 

The winding cross section AN has to be splitted into 

the number of windings. 

Primary winding 0,5 

Secondary winding 0,45 

Auxiliary winding 0,05 

N Aux 

32 ⋅ 

= 

( 12V 

+ 0, 

7V 

) 

100V 

we choose NAux = 4 turns 

L P 

I LPK 

= 

32 2 

4, 

06 


V1.2 

= 

⋅ 244nH 

= 250µ 

H 

99, 

2V 

⋅ 0, 

5 

= 

250µ 

H ⋅100* 

10 

3 

Hz 

250µ 

H ⋅1, 

98A 

Bmax = 

= 186mT 

2 

32 ⋅83mm 

= 1, 

98A 

−7 

2 

2 

4 ⋅π 

⋅10 

⋅ 32 ⋅83mm 

s = 

= 0, 

43mm 

250µ 

H 

From bobbin datasheet E32/16/9: BW = 20,1mm 

Margin determined: M = 4mm 

BW e 

= 

20 , 1mm 

− 2⋅ 

4mm 

= 12, 

1mm

Copper space factor fCu :0,2 ....0,4 

A 

P 

⋅ AN 

= 

N 

5 , 0 

⋅ f 

P 

Cu 

⋅ BW 

⋅ BW 

( 1, 

8277 − ( 2 ( d ) ) ) 

e 


(Eq 22) 

AWG = 9, 97 ⋅ ⋅log 

(Eq 23) 

A 

A 

s 

aux 

⋅ A 

= 

N 

45 , 0 

N 

s 

⋅ A 

= 

N 

05 , 0 

⋅ f 

Cu 

⋅ BW 

N 

aux 

⋅ f 

⋅ BW 

Cu 

⋅ BW 

e 

⋅ BW 

e 

(Eq 24) 

(Eq 25) 

With the effective bobbin width we check the number 

of turns per layer: 

BWe 

N P = (Eq 26) 

d 

P 

We calculate the available area for each winding: 

Used for calculation: fCu =0,3 

A P 

A s 

A aux 

= 

= 

0, 

5 

⋅ 

2 

108, 

5mm 

⋅ 

32 ⋅ 20, 

1 

12, 

1 

= 0, 

31mm 


V1.2 

0 

, 3 

diameter dp ≈ 0,64mm 22 AWG 

0, 

45 

Primary: 

N P 

⋅ 

2 

108, 

5mm 

4 ⋅ 20, 

1 

⋅ 

⋅ 

0, 

3 

⋅ 

12, 

1 

2 

= 2, 

20mm 

diameter ds 2 x 0,8mm 2 x 20 AWG 

2 

0, 

05⋅108, 

5mm 

⋅0, 

3⋅12, 

1 

2 

= 

= 0, 

24mm 

4⋅ 

20, 

1 

diameter da ≈ 0,64mm 22 AWG 

12, 

1mm 

= = 17 turns per layer 

0, 

64mm 

Secondary: 

2 layer needed 

12, 

1mm 

N S = = 4 turns per layer 

2⋅ 

0, 

8mm 

Auxiliary: 

Can be neglected ! 

2

Output Rectifier (D1): 


The output rectifier diodes in flyback converters are 

subject to a large PEAK and RMS current stress. The 

values depend on the load, leakage inductance, 

operating mode and output capacitor ESR. 

Calculation of the maximum reverse voltage: 

 

+ 

V 

 

N 

⋅ 

N 

VRDiode = VOUT 

DC max PK 

S 

P 

(Eq 27) 

Calculation of the maximum current on secondary 

side: 

N 

I ⋅ 

P 

SPK = I LPK 

(Eq 28) 

N S 

= I ⋅ 1 ⋅ D 

3 max 

(Eq 29) 

I SRMS SPK 

Output Capacitors (C5 & C9): 

Output capacitors are highly stressed in flyback 

converters. Normally the capacitor will be selected for 

3 major parameters: capacitance value, low ESR 

and ripple current rating. 

Max. voltage overshoot: ∆VOUT 

Number of clock periods: nCP 

C 

OUT 

= 

I 

∆V 

OUT 

⋅ 

⋅ f 

OUT max n CP 

Select a capacitor out of Epcos Databook 

of Aluminium Electrolytic Capacitors. 

The following types are preferred: 





 

(Eq 30) 

V RDiode 

I SPK 

I SRMS 

4 

= 12 V + 382V 

⋅ = 59, 

8V 

32 

32 

= 1 , 98A 

⋅ = 15, 

8A 

4 

= 15 , 8A 

⋅ 1 ⋅ 0, 

5 = 6, 

5 

3 

To calculate the output capacitor, it is necessary to fix 

the maximum voltage overshoot in case of switching 

off @ maximum load condition. 

After switching off the load, the regulation loop needs 

about 5...10 periods of internal clock to reduce the 

duty cycle. 

∆ 

V OUT 

nCP = 5 

C OUT 

= 0, 

5V 

3, 

33A 

⋅ 5 

= 

= 333µ 

F 

3 

0, 

5V 

⋅100 

* 10 Hz 

We select 470µF 25V (based on Eq 30): 

B41826-A5477-M 

ESR ≈ Zmax = 0,06Ω @ 100kHz 

IacR = 2,2A 

ISRMS = 6,6A (Eq 29) you need 3 capacitor 


V1.2 

A

Output Filter (L3 & C9): 


The output filter consists of one capacitor (C9) and 

one inductor (L3) in a L-C filter topology. 

Zero frequency of output capacitor (C9) and 

associated ESR: 

f 

ZCOUT 

1 

= 

2 ⋅π 

⋅ R 

ESR 

⋅ C 

OUT 

(Eq 31) 

Calculating the needed inductance (L3) for substitute 

the zero of the 3 output capacitors: 

L 

OUT 

R 

= 

2 ⋅π 

⋅ f 

VCC – Supply: 

ESR 

ZCOUT 

⋅ n 

pCOUT 

Start-up Resistor (R6 & R7): 

ICCLmax = max. Quiescent Current (Control IC) 

ILoadC = VCC-Capacitor Load-Current (C4) 

CVCC = Value of VCC-Capacitor (C4) 

R 

Start 

= 

I 

V 

CCL max 

DC min 

Start up Time tStart: 

t 

C 

⋅V 

+ I 

LoadC 

(Eq 32) 

(Eq 33) 

VCC CCH 

Start = (Eq 34) 

I LoadC 

Internal Zener Diode: 

Depending on the transformer construction and load 

condition the auxiliary supply voltage varies within an 

operating range. If VCC exceeds VZ (16V), the 

internal zener diode conducts. In this case we have 

to observe the internal power dissipation limits or 

use an external zener diode on VCC pin. 

f ZCOUT 

L OUT 

1 

= 

= 5, 

6kHz 

2⋅π 

⋅0, 

06Ω 

⋅ 470µ 

F 

0, 

06Ω 

= 

= 0, 

57µ 

H 

2 ⋅π 

⋅ 5, 

6kHz 

⋅3 

ICCLmax = 80µA 

ILoadC = 40µA 

CVCC = 22µF 

R Start 

99, 

2V 

= = 827kΩ 

( 80 + 40) 

µ A 

R6 = R7 =1/2 RStart = 413,5kΩ 

Choose 2 with value: 410kΩ 

t Sstart 

22µ 

F ⋅12V 

= 

= 6, 

6s 

40µ 

A 

Note: 

Before the IC can be plugged into the application 

board, the VCC capacitor has always to be 

discharged! 


V1.2

Calculation of Snubber Network: 

(R10/C12/D3) 

V = V −V 

max −V 

Snub 

BR) 

DSS 

DC 


R 

( (Eq 35) 

For calculating the snubber network it is neccesary to 

know the leakage inductance. Most common way is 

to have the value of the leakage inductance (LLK) in 

percent of the primary inductance (Lp). If it is known 

that the transformer construction is very consistent, 

measuring the primary leakage inductance by 

shorting the secondary windings will give an exact 

number, assuming the availability of a good LCR 

analyser. 

L LK 

C 

R 

Snub 

Snub 

= Lp ⋅ x% 

= 

I 

2 

LPK 

⋅ L 

LK 

( VR 

+ VSsnub 

) ⋅VSnub 

( V + V ) 

2 

Ssnub R −V 

R 

= 2 

0, 

5 ⋅ L ⋅ I ⋅ f 

LK 

2 

LPK 

(Eq 36) 

(Eq 37) 

V Snub 

= 650 V − 382V 

−100V 

= 168V 

In our example we choose 5% of primary inductance 

for leakage inductance. 

L LK 

C Ssnub 

R Snub 

= 250 µ H ⋅5% 

= 12, 

5µ 

H 

= 

( 1, 

98A) 

( 100V 

+ 168V 

) 

⋅12, 

5µ 

H 

= 1, 

1nF 

⋅168V 


V1.2 

2 

( 168V 

+ 100V 

) 

2 

≈ 1,2nF 

2 

−100V 

= = 25, 

3kΩ 

2 

3 

0, 

5⋅12, 

5µ 

H ⋅ ( 1, 

98A) 

⋅100* 

10 Hz 

≈25kΩ

Calculation of Losses: 

Input diode bridge (BR1): 


P DIN = I PRMS ⋅VF 

⋅ 2 

(Eq 38) 

Calculation of copper resistance RCu: 

R 

l 

⋅ N 

⋅ p 

N P 100 

PCu = (Eq 39) 

AP 

Calculating of copper loss (TR1): 

2 

PCu = I LPK ⋅ DMAX 

⋅ 1 ⋅ R 

3 

Output rectifier diode (D1): 

Cu 

1 − Dmax 

PDDIODE = I SPK ⋅ ⋅V 

3 

COOLMOS TRANSISTOR: 

TDA16834 

Calculated @ VDCmin = 99V 

CO ≈ 50pF (CO = COSS + CExtern) 

RDSON = 1,6Ω (@ 150°C) 

Switching losses: 

2 

PSON = ⋅C 

O ⋅V 

2 

DC 

min 

⋅ f 

FDIODE 

(Eq 40) 

(Eq 41) 

1 (Eq 42) 

( VDC 

+ VR 

) ⋅ I LPK ⋅ f tr 

1 (Eq 43) 

PSOFF = ⋅ min 

⋅ 

6 

Conduction losses: 

2 

P 1 

D ⋅ RDSON 

⋅ I LPK ⋅ Dmax 

= (Eq 44) 

3 

P DIN 

= 0 , 98A 

⋅1V 

⋅ 2 = 1, 

96W 

Copper resistivity p100 @ 100°C = 0,0172Ωmm 2 /m 

R PCu 

R SCu 

P PCu 

P SCu 

2 

0, 

0644m 

⋅32 

⋅17, 

2mΩmm 

/ m 

= = 114, 

3mΩ 

2 

0, 

31mm 

2 

0, 

0644m 

⋅ 4 ⋅17, 

2mΩmm 

/ m 

= = 2, 

01mΩ 

2 

2, 

20mm 

2 

= ( 1, 

98A) 

⋅ 0, 

5⋅ 

1 ⋅114, 

3mΩ 

= 74, 

7mW 

3 

2 

= ( 15, 

8A) 

⋅ 0, 

5 ⋅ 1 ⋅ 2, 

01mΩ 

= 84, 

1mW 

3 

P Cu 

P DDIODE 

= 74, 

7mW 

+ 84, 

1mW 

= 158, 

8mW 

1− 

0, 

5 

= 15 , 8A 

⋅ ⋅ 0, 

7V 

= 4, 

52W 

3 

(see also TDA 16831 ... 34 Data Sheet) 

P SON 

P SOFF 

P D 

= 

= 

1 

2 

⋅ 50 pF ⋅99V 


V1.2 

2 

3 

⋅100 

* 10 Hz = 24, 

5mW 

( 99V 

+ 100V 

) ⋅ 2, 

02A 

⋅100kHz 

⋅30ns 

197mW 

= 1 ⋅ 

= 

6 

1 

3 

2 

⋅1, 

6Ω 

⋅ ( 1, 

98A) 

⋅ 0, 

5 = 1, 

05W

Summary of Losses: 

P P + P + P 

Losses 

SON 

SOFF 


= (Eq 44a) 

Thermal Calculation: 

K 

Table of typical thermal Resistance [ ]: 

W 

Heatsink DIP8 SO14 

No 90 112 

3 cm² 64 92 

6 cm² 56 78 

dT P * R 

Losses 

th 

D 

= (Eq 44b) 

Tj dT + Ta 

= (Eq 44c) 

P Losses 

= 25 , 4mW 

+ 197mW 

+ 1005mW 

= 1, 

27W 

K 

dT = 1 , 27W 

* 56 = 71, 

2K 

W 

Tj = 71, 

2K 

+ 50° 

C = 121° 

C 


V1.2

Voltage Regulation Loop: 

Reference: TL431 (IC2) 

VREF =2,5V 

IKAmin=1mA 

Optocoupler: SFH617-3 (IC1) 

Gc = 1 ...2 ≡ CTR 100% ...200% 

VFD = 1,2V 

IFmax =10mA (maximum current limit) 

Primary side: 

Feedback voltage: 

Values from TDA16831...34 datasheet 

VRef int = 5.5V typ. 

VFBmax = 4,8V 

RFB = 3,7k typ. 

I 

I 

FB 

V 

R 

Re f int 

FB 


max = (Eq 45) 

FB min 

V 

Re f int 

−V 

R 

FB 

FB max 

= (Eq 46) 

Secondary side: 

1 

VOUT 

 

= R 

2 −1 

VREF 

R (Eq 47) 

the value of R2 can be fixed at 4,7k 

R 

R 

( V − ( V + V ) ) 

OUT FD REF 

3 ≥ (Eq 48) 

I F max 

4 

V 

FD 

 

+ R 

 

I 

3 

KA min 

I 

⋅ 

Gc 

FB min 

 

≤ (Eq 49) 

Fig. 3 

Fig. 4 

I FB max 

I FB min 

5,5V 

3,7k 

VFB 

R3 

TL431 

5, 

5V 

= = 1, 

5mA 

3, 

7kΩ 

5, 

5V 

− 4, 

8V 

= 

= 0, 

19mA 

3, 

7kΩ 

12V 

 

R1 = 4, 

7k 

⋅ 

−1 

= 17, 

86k 

2, 

5V 

( 12V 

− ( 1, 

2V 

+ 2, 

5V 

) ) 

R3 = 0, 

83k 

10mA 

≥ ≈ 910R 

0, 

2mA 

 

1, 

2V 

+ 910R 

⋅ 

1 

R4 = 1, 

4k 

1mA 

≤ ≈ 1,2k 


V1.2 

FB 

R4 

R5 

C2 

C1 

R1 

R2 

Vout

Regulation Loop: 

Fig. 5 


Transfer Characteristics of Regulation Loop Elements: 

K 

G 

⋅ 3k7 

C 

FB = Feedback 

R3 

R2 

V 

K VD = = 

R1 

+ R2 

V 

F 

F 

PWR 

LC 

VIN 

1 

( p) 

= 

Z 

( p) 

PWM 

⋅ 

REF 

OUT 

 

 

LP 

⋅ f ⋅η 

RL 

⋅ 

2 ⋅ RL 

R 

 

1 

+ p ⋅ 

2 

ZPWM = Transimpedance ∆VFB/∆ID 

1 + p ⋅ R 

FPWR(p) 

KFB 

⋅ C 

( 1 + p ⋅ R ⋅ C ) 

L 

ESR 

+ R 

ESR 

 

⋅ 

5 

C 

5 

 

 

 

Voltage Divider 


V1.2 

 

Power stage 

ESR 9 

= Output filter 

2 

1 + p ⋅ RESR 

⋅ C9 

+ p ⋅ L ⋅ C9 

( C1+ 

C2) 

FLC(p) 

Fr(p) 

1+ 

p ⋅ R5⋅ 

Fr( 

p) 

= Regulator 

R1⋅ 

R2 

p ⋅ ⋅C1⋅ 

( 1+ 

p ⋅ R5⋅ 

C2) 

R1+ 

R2 

KVD 

_ 

+ 

Vout 

Vref


Zero’s and Poles of the transfer characteristics: 

Poles of powerstage @ min. and max. load: 

2 

12 

= = = 3, 

6Ω 

40 

2 

VOUT 

V 

12 

RLH 

= = = 144Ω 

P W 

1 

2 

VOUT 

V 

RLL 

P W 

f 

f 

OH 

OL 

= 

π ⋅ 

= 

π ⋅ 

OUT max 

1 

R ⋅ C5 

LH 

1 

R ⋅ C5 

LL 

f OH 

f OL 

2 

OUT min 

1 

= 

= 

π ⋅ 3, 

6Ω 

⋅1410µ 

F 

62, 

7 

Hz 

1 

= 

= 1, 

57Hz 

π ⋅144Ω 

⋅1410µ 

F 

The gain (Gc) of the optocoupler stage KFB and the voltage divider KVD we use as a constant. 

K 

G 

⋅ 3k7 

C 

FB = KFB = 6,6 GFB = 16,4db 

R3 

R2 

V 

K VD = = 

R1 

+ R2 

V 

REF 

OUT 

KVD = 0,208 GVD = -13,6db 

With adjustment of the transfer characteristics of the regulator we want to have equal gain within the 

operating range and to compensate the pole fo of the powerstage FPWR(ω). 

Because of the compensation of the output capacitors zero (see page 11 Eq31, Eq32) we neglect this zero 

and the LC-Filter pole. 

So the transfer characteristics of the power stage is reduced to a single pole response. 

In order to calculate the gain of the open loop we have to select the crossover frequency. 

We calculate the gain of the Power-Stage with max. output power at the selected crossover frequency 

fg = 3kHz: 

ZPWM of TDA16834 =1,3 V/A 

PWM 

( t ) 

ON 

= Z 

PWM 

⋅ 

t 

 

⋅ t 

 

 

+ 0, 

6 ⋅ − e 

 

1 

ON 

−tON 

T1 

ON − T1 

+ T1⋅ 

e 

1 

−tON 

T 2 

Z (formula according data sheet p. 12) 

 


V1.2


with this formula we calculate ZPWM @ max. duty cycle: 

Z 

PWM 

( t ) 

ON 

V 1 

= 1, 

3 ⋅ ⋅ 4, 

7µ 

s − 850ns 

+ 850ns 

⋅ e 

A 4, 

7µ 

s 

Gain @ crossover frequency: 

F 

PWR 

F PWR 

1 

( fg) 

= 

Z 

( 3kHz) 

= 

PWM 

1 

1, 

7 

⋅ 

⋅ 

R 

GPWR(3kHz) = -22,7db 

Transfer characteristics: 

Fig. 6 

L 

 

 

⋅ L 

p ⋅ f ⋅η 

⋅ 

2 

 

 

 

1 

fg 

1 + 

 

 

 

fo 

 

 

3, 

6R 

⋅ 250µ 

H ⋅100kHz 

⋅ 0, 

8 

⋅ 

2 

 

 

 

 

Gain 

[db] 

50 

G 

PWR 

( ω ) 

Gr( ω ) 

G FB 

G MOD 

0 

50 

50 

0 

GVD 

Gr(ω) 

2 

 

 

+ 0, 

6 ⋅ 1 

− e 

 

− 4, 

7µ 

s 

−4, 

7µ 

s 

850ns 

200ns 

1 

3000 

1+ 

 

62, 

7 

1 10 100 1 10 3 

50 

1 ω( ) i 

2. π 

2 

 

= 

1 10 4 

0, 

073 

GFB 

GPWR(ω) 

1 10 5 

110 . 5 

V 

= 1, 

7 

A 


V1.2


At the crossover frequency (fg) we calculate for the open loop gain: 

Gol(ω) = Gs (ω) + Gr (ω) = 0. 

With the equations of the transfer characteristics we calculate the gain of the regulation loop @ fg. 

The gain of the regulation loop we calculate: 

Gs = GFB + GPWR + GVD = 16,4db – 22,7db – 13,6db 

Gs = -19,9db 

We calculate the separate components of the regulator: 

Gs (ω) + Gr (ω) = 0 Gr = 0 – (-19,9db) = 19,9db 

( C1+ 

C2) 

) 

1+ 

p ⋅ R5⋅ 

Fr( 

p) 

= 

R1⋅ 

R2 

p ⋅ ⋅C1⋅ 

( 1+ 

p ⋅ R5⋅ 

C2) 

R1+ 

R2 

( R1 

+ R2) 

R5⋅ 

Gr = 20⋅ 

log 

R1⋅ 

R2 

1 

fp = 

2⋅π 

⋅ R5⋅ 

C2 

20, 

9 

R5 

= 10 

Gr 

20 

20 R5 10 ⋅3, 

72k 

= 41, 

7k 

R1⋅ 

R2 

⋅ 

R1+ 

R2 

= ≈ 43k 

1 

C2 

= 

2⋅π 

⋅ R5⋅ 

2⋅ 

fg 

1 

C2 = 

= 617 pF 

2⋅π 

⋅ 43k 

⋅6kHz 

≈ 680pF 

fp = 2*fg 

In order to have enough phase margin @ low load condition we select the zero frequency of compensation 

network at the middle between min. and max. load pole of power stage. 

f 

om 

oh 

fol 

0, 

5 log 

foh 

10 ⋅ 

62, 

7 

= f ⋅ 

= 62, 

7Hz 

⋅10 

= 9, 

92Hz 

1 

fz = 

2⋅π 

⋅ R5⋅ 

( C1+ 

C2) 

f om 

1, 

57 

0, 

5⋅log 

1 

C1 = 

− C2 

2⋅π 

⋅ R5⋅ 

fom 

1 

C1 = 

− 680 pF = 384nF 

2⋅π 

⋅ 43k 

⋅9, 

92Hz 

≈ 390nF 


V1.2

Open Loop Gain 

Fig. 7 

Open Loop Phase 

Fig. 8 


70 

Gr( ω ) 

Gs( ω ) 

G( ω ) 

0 

10 

φr( ω ) 

φs( ω ) 

φ( ω ) 

0 

180 

60 

50 

0 

50 

10 

28 

66 

104 

142 

1 10 100 1 10 3 

1 ω( ) i 

2. π 

1 10 100 1 10 3 

180 

1 ω( ) i 

2. π 

1 10 4 

1 10 4 

1 10 5 

110 . 5 

1 10 5 

110 . 5 


V1.2

Transformer Construction 


The winding topology has a considerable influence on the performance and relaibility of the 

transformer. 

To reduce leakage inductance and proximity to acceptable limits, the use of a sandwich construction is 

recommended. 

In order to meet international safety requirements a transformer for Off - Line power supply must have 

adequate insulation between primary and secondary winding. 

This can be achived by using a margin wound construction or using triple insulated wire for the 

secondary winding. 

The creepage distance for universal input voltage range is typically 8mm. This sets a minimum margin 

width as a half of the creepage distance to 4mm. Additional the neccesary insulation between primary 

and secondary winding is provided using three layers of basic insulation tape. 

Example of winding topology for margin wound transformers: 

Fig. 9 

Example of winding topology with triple insulated wire for secondary winding: 

Fig. 10 

Triple Insulated 

Wire 

BW* : value from bobbin datasheet 

Creepage 

distance 

Triple insulation 

BW* 

BWe 

margin margin 

BW* 

Primary 

second half 

Secondary 

Auxiliary 

Primary 

first half 

Primary 

second half 

Secondary 

Auxiliary 

Primary 

first half 


V1.2

Layout Recommendation: 

Fig. 11 


In order to avoid crosstalk between Power- and Signal-Path on the board we have to use care 

regarding the track layout when designing the PCB. 

The Power-Path (see Fig. 11) has to be as short as possible and separated from the VCC-Path and 

the Feedback-Path. All GND-Paths have to be connected together at pin 8 (star ground) (1 and 14 at 

G-type) of TDA16831...34. 


V1.2

Output Power Table 


Output Power @ 

VIN = 190 – 270V 

Package Heatsink Heatsink Heatsink 

No 3 cm² 6 cm² 

Output Power @ 

VIN = 85 – 270V 

Heatsink Heatsink Heatsink 

No 3 cm² 6 cm² 

Device 

TDA 

16831 DIP8 *17W *17W *17W *12W *12W *12W 

16832 DIP8 24W 30W 32W 15W 18W 20W 

16833 DIP8 **36W 49W 55W 26W 31W 34W 

16834 DIP8 **34W 52W 60W 34W 42W 45W 

16831G SO14 *17W *17W *17W *12W *12W *12W 

16832G SO14 **21W 24W 26W 13W 15W 16W 

16833G SO14 **23W 25W 28W 23W 25W 28W 

Output Power Table Notes: 

This output power table was created with the equations of this application note (see „Calculation of 

Losses“ on page 13 / 14), it shows the maximum practical continuous power @ Ta = 50 °C and 

Tj = 125 °C with the recommended heatsink. 

The conduction losses are calculated with the typical RDSON @ Tj = 125°C (see Data Sheet TDA 1683x 

page 13). The OFF switching losses are calculated with a typical fall time of tf = 50 ns (see Data Sheet 

TDA 1683x page 13), the ON switching losses with the effective capacitance (+ estimated external 

capacitances) of the used device (see also Data Sheet TDA 1683x page 13). 

*The current limitation regulates the output power (see Data Sheet TDA 1683x page 13) 

** The power losses are spitted in switching losses (CoolMOS) and conduction losses. It´s depending 

on VDCin witch part on losses having more impact of the power losses (Chart: Select your device). 

Chart: Select your Device (Tj @ 125°C, Ta @ 50°C, Vreflection @ 100V ) 

Power Losses [W] 

1,60 

1,40 

1,20 

1,00 

0,80 

0,60 

0,40 

0,20 

Power Losses of all Devices @ typical Pout 

Small – Range 

0,00 

90 115 140 165 190 215 240 265 290 315 340 365 

Input Voltage - Vdcin [V] 

TDA16834@35W TDA16833_G@35W TDA16831_32_G@15W TDA16822@15W 


V1.2


Summary of used Nomenclature 

Parameters 

Bmax 

Magnetic Inductance 

BW Bobbin Width 

BWe Effective Bobbin Width 

CIN 

Capacitance of Bulk Capacitor 

CO 

Output Capacitance 

COSS 

Output Capacitance of CoolMOS 

CExtern 

Output Capacitance of external Components 

CSnub 

Capacitance of Snubber – Capacitor 

CVCC 

Capacitance of VCC – Capacitor 

D Duty Cycle 

Dmax 

Maximum Duty Cycle 

f Operating Frequency of CoolSET (f = 100kHz) 

fAC 

fg 

fCu 

fOH 

fOm 

fOL 

fZCOUT 

GC 

Line Frequency (Germany FAC = 50Hz) 

Crossover Frequency 

Copper Space Factor (0,2 ... 0,4) 

Frequency Open Loop (High) 

Frequency Open Loop (middle) 

Frequency Open Loop (Low) 

Zero Frequency of output Capacitor 

Optocoupler Gain 

ICCLmax Maximum quiescent Current of CoolSET (Control IC) 

IFBmax 

Maximum Feedback Current 

IFBmin 

Minimum Feedback Current 

IFmax 

Maximum Current (Optocoupler) 

IKAmin 

Minimum Current (TL431) 

ILoadC 

VCC – Capacitor Load – Current 

ILPK 

Peak Current through the primary Inductance 

ILRMS 

Root Mean Square Current through the primary Inductance 

IPRMS 

Root Mean Square Current through the Bridge Rectifier 

IPRI 

Primary Current @ time t 

ISEC 

Secondary Current @ time t 

ISPK 

Peak Current through the secondary Inductance 

ISRMS 

Root Mean Square Current through the secondary Inductance 

LOUT 

Inductance output Filter 

LP 

Primary Inductance 

LLK 

Leakage Inductance 

M Margin (of Transformer) 

nCP 

Number of Clock Periods 

npCOUT 

Number of parallel output Capacitors 

NP 

Number of primary Turns 

NS 

Number of secondary Turns 

NAux 

Number of auxiliary Turns 

PCu 

Power losses of Copper Resistor 

PD 

Conduction losses 

PDIN 

Power losses input Diode 

PDDIODE 

Power losses rectifier Diode (secondary side) 

PIN MAX 

Maximum Input Power 

POUT max 

Maximum Output Power 

POUT min 

Minimum Output Power 

PPCu 

Power losses of Copper Resistor (primary Inductance) 

PSCu 

Power losses of Copper Resistor (secondary Inductance) 

PSOFF Switching losses of CoolMOS Transistor (Off – Operation) 

PSON Switching losses of CoolMOS Transistor (On – Operation) 


V1.2


RCu 

Copper Resistor (Transformer) 

RDSON Resistance of switching CoolMOS Transistor (On – Operation) 

RL 

Load - Resistance 

RLH 

Maximum Load 

RLL 

Minimum Load (defined by Designer) 

RFB Internal Feedback Resistor (CoolSET ) 

RPCu 

Copper Resistor of primary Inductance 

RSCu 

Copper Resistor of secondary Inductance 

RSnub 

Snubber Resistor 

Start up Resistor 

RStart 

1 1 

T µ 

3 

f 100* 

10 sec 

T Time of one Period = = 

= 10 s 

TD 

Discharging Time of Input Capacitor C3 

tON On Time (CoolMOS ) 

tOFF Off Time (CoolMOS ) 

tr 

Rising Time (Voltage) 

tStart 

Start up Time 

VAC min 

Minimal AC Input Voltage 

VAC max 

Maximal AC Input Voltage 

VAux 

Auxiliary Voltage 

V(BR)DSS 

Drain Source Breakdown Voltage 

VCCH Turn On Threshold for CoolSET @ Vcc - Pin 

VDC IN 

DC Input Voltage 

VDC IN max Maximum DC Input Voltage 

VDC IN min Minimum DC Input Voltage 

VDC max PK Maximum DC Input Voltage Peak 

VDC min PK Minimum DC Input Voltage Peak 

VDC min 

Minimum DC Input Voltage @ maximum load 

VDDIODE 

Reverse Voltage rectifier Diode (secondary side) 

VFBmax Maximum Feedback Voltage (CoolSET ) 

VFDIODE 

Output Diode Forward Voltage 

VFD 

Forward Diode Voltage (Optocoupler) 

VOUT 

Output Voltage (secondary Side) 

VOUT Ripple Output Ripple Voltage (secondary Side) 

VR 

Reflected Voltage (from secondary side to primary side) 

VRDiode 

Reverse Voltage Diode 

VRefint Internal Reference Voltage (CoolSET ) 

VREF 

Reference Voltage TL431 

VRipple 

DC Ripple Voltage (on primary Side) 

VSEC 

Voltage on Sekondary Inductor 

VSnub 

Maximum Voltage overshoot @ snubber 

WIN 

Discharging Energie Input Capacitor 

Transimpedanz 

ZPWM 


V1.2

References 


[1] Keith Billings, 

Switch Mode Power Supply Handbook 

[2] Ralph E. Tarter, 

Solid-State Power Conversion Handbook 

[3] R. D. Middlebrook and Slobodan Cuk, 

Advances in Switched-Mode Power Conversion 

[4] Herfurth Michael, 

Ansteuerschaltungen für getaktete Stromversorgungen mit Erstellung eines 

linearisierten Signalflußplans zur Dimensionierung der Regelung 

[5] Herfurth Michael, 

Topologie, Übertragungsverhalten und Dimensionierung häufig eingesetzter 

Regelverstärker 

[6] Infineon Technologies, 

Datasheet TDA16831 ... 34 Off – Line SMPS Controller with 600V CoolMOS 

Transistor on Board, 

Revision History 

Application Note AN-SMPS-1683X-1 

Actual Release: V1.2 Date:11.05.2000 Previous Release: V1.1 

Page of 

actual 

Rel. 

Page of 

prev. Rel. 

28 21 Formatting 

Subjects changed since last release 


V1.2


For questions on technology, delivery and prices please contact the Infineon 

Technologies Offices in Germany or the Infineon Technologies Companies and 

Representatives worldwide: see the address list on the last page or our webpage at 

http://www.infineon.com 

CoolMOS and CoolSET are trademarks of Infineon Technologies AG. 

Edition 2000--05--11 

Published by Infineon Technologies AG, 

St.-Martin-Strasse 53, 

D-81541 München 

© Infineon Technologies AG 2000. 

All Rights Reserved. 

Attention please! 

The information herein is given to describe certain components and shall not be considered as warranted characteristics. 

Terms of delivery and rights to technical change reserved. 

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts 

stated herein. 

Infineon Technologies is an approved CECC manufacturer. 

Information 

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in 

Germany or our Infineon Technologies Representatives worldwide (see address list). 

Warnings 

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your 

nearest Infineon Technologies Office. 

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon 

Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the 

safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support 

and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be 

endangered. 


V1.2


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Beijing Office 

Room 2106,Building A 

Vantone New World Plaza 

No.2 Fu Cheng Men Wai Da Jie 

Jie 

100037 Beijing 

T (+86)10 -68 57 90 -06,-07 

Fax (+86)10 -68 57 90 08 



Chengdu Office 

Room14J1,Jinyang Mansion 

58 Tidu Street 

Chengdu, 

Sichuan Province 610 016 

T (+86)28-6 61 54 46 /79 51 

Fax (+86)28 -6 61 01 59 



Shanghai Office 

Room1101,Lucky Target Square 

No.500 Chengdu Road North 

Shanghai 200003 

T (+86)21-63 6126 18 /19 

Fax (+86)21-63 61 11 67 



Shenzhen Office 

Room 1502,Block A 

Tian An International Building 

Renim South Road 

Shenzhen 518 005 

T (+86)7 55 -2 28 91 04 

Fax (+86)7 55-2 28 02 17 

ZA 

Siemens Ltd. 

Components Division 

P.O.B.3438 

Halfway House 1685 

T (+27)11-6 52 -27 02 

Fax (+27)11-6 52 20 42 


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Power Conversion - SmartData

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