슬라이드 1 - Flash Memory Summit
슬라이드 1 - Flash Memory Summit
슬라이드 1 - Flash Memory Summit
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Seaung Suk Lee<br />
Vice President<br />
<strong>Flash</strong> Product Planning Group<br />
Hynix Semiconductor Inc.<br />
Emerging Challenges<br />
in NAND <strong>Flash</strong> Technology<br />
August 10, 2011
Presentation Agenda<br />
NAND <strong>Flash</strong> Market Overview<br />
Technology Scaling Trend & Forecast<br />
Technology Scaling Limitation & Hurdle<br />
Future Technology Development Direction<br />
1
Presentation Agenda<br />
NAND <strong>Flash</strong> Market Overview<br />
Technology Scaling Trend & Forecast<br />
Technology Scaling Limitation & Hurdle<br />
Future Technology Development Direction<br />
2
Market Revenue Forecasting<br />
[Source; WSTS2011]<br />
3
Prospective Application Trend<br />
[Source; Hynix Marketing 2011]<br />
4
General Market Requirement<br />
Low Cost<br />
Bit growth<br />
High Performance<br />
+ Controller SW solution<br />
High Reliability<br />
+ Controller SW solution<br />
5
Standard Interface Trend; Performance<br />
6<br />
1.6GB/s
Presentation Agenda<br />
NAND <strong>Flash</strong> Market Overview<br />
Technology Scaling Trend & Forecast<br />
Technology Scaling Limitation & Hurdle<br />
Future Technology Development Direction<br />
7
Further Scaling Solution?<br />
Conventional FG NAND cell has been scaled down over 18 years.<br />
[ Effective Cell Size : nm 2 ]<br />
1,000,000<br />
100,000<br />
10,000<br />
1,000<br />
100<br />
10<br />
64M<br />
256M<br />
1G<br />
512M<br />
1G<br />
SLC<br />
2G<br />
2G 4G 8G<br />
MLC<br />
‘98 ‘02 ‘06 ‘10 ‘14 ‘18<br />
8<br />
4G 8G 16G 32G<br />
16G<br />
▶ 0.7um → 2Xnm (Cell size : ~1/2000)<br />
▶ 1.5year/gen. (18 years / 12 gen.)<br />
32G<br />
32G 64G<br />
250 160 130 90 70 5X 4X 3X 2X 2Y 1X 1Y 1Znm …… ??<br />
[ Year ]<br />
?
Presentation Agenda<br />
NAND <strong>Flash</strong> Market Overview<br />
Technology Scaling Trend & Forecast<br />
Technology Scaling Limitation & Hurdle<br />
Future Technology Development Direction<br />
9
Scaling Limitation of FG Cell<br />
Physical Limitation;<br />
Patterning<br />
Structure formation : FG, CG, IPD …<br />
Electrical Limitation;<br />
Interference<br />
Capacitive coupling ratio<br />
No. of electron in FG<br />
Dielectric leakage<br />
10
Cell Scaling Limitation; x-direction<br />
ASA-FG Advanced Self-Aligned Floating Gate<br />
R R<br />
• BL Loading;<br />
RC<br />
STI<br />
M1<br />
ILD<br />
CG<br />
IPD<br />
FG<br />
Active<br />
• Cell Current ∝ W<br />
Width<br />
• IPD & CG gap-fill;<br />
Space<br />
11<br />
M1<br />
ILD<br />
SAC NIT<br />
SPACER<br />
WSix<br />
POLY2<br />
ONO<br />
POLY1<br />
Tunnel Ox<br />
ISO HDP<br />
P-Substrate
Cell Scaling Limitation; y-direction<br />
Drain<br />
• WL Loading;<br />
RC delay<br />
••• •••<br />
DSL DCT DSL WL31 WL30 WL15 WL1 WL0 SSL SCT SSL<br />
• Cell S/D Punch;<br />
0ff leakage<br />
ILD<br />
CG FG<br />
12<br />
• Interference;<br />
Source<br />
Vt distribution<br />
M1<br />
ILD<br />
DCT<br />
SAC NIT<br />
SPACER<br />
WSix<br />
POLY2<br />
ONO<br />
POLY1<br />
Tunnel Ox<br />
P-Sub
NAND Program Speed<br />
Program Speed = t (PROG + Verify) X N<br />
• tPROG ; unit program & verify time<br />
• N ; no. of ISPP<br />
NAND<br />
Program<br />
Speed<br />
1/∝<br />
t (PROG)<br />
t (Verify)<br />
13<br />
∝<br />
1/∝ ∝<br />
W/L loading<br />
B/L loading<br />
No. of Pulse PGM Vt<br />
∝ ∆ ISPP 1/∝<br />
Distribution<br />
@ fixed bias
Normalized Unit<br />
WL & BL Loading Improvement<br />
WL Loading<br />
0.8<br />
0.6<br />
0.4<br />
– Material; Poly- Si CoSix W<br />
– WL Space; Vertical Profile Low-k dielectric Air Gap<br />
) 1.0<br />
WL Capacitance (b)<br />
BL Loading<br />
– Material; W Al Cu<br />
– BL Space; Vertical Profile Low-k dielectric Air Gap<br />
0.2<br />
0 10 20 30 40 50 60 70<br />
Airgap Portion between WLs[%]<br />
14<br />
WL<br />
Cell Vth [V]<br />
6<br />
3<br />
0<br />
-3<br />
0 10 2<br />
Airgap Po
Number of Electron per bit, [N]<br />
1000<br />
100<br />
No. of stored electrons in FG<br />
10<br />
∆Vth-max= 3V Program Operation<br />
10<br />
NOR <strong>Flash</strong> Projection<br />
2ynm<br />
1xnm<br />
(ITRS 2003) ●<br />
◎ ■<br />
◇<br />
▲<br />
□<br />
2xnm<br />
NOR <strong>Flash</strong> Projection<br />
(ITRS 2003)<br />
IEDM Papers<br />
<strong>Flash</strong> Technology Node [nm]<br />
100<br />
15<br />
FG<br />
CG (Positive)<br />
e e e eh e eh e eh e eh e<br />
eh e eh e<br />
eh e<br />
e e<br />
P- Well<br />
e e e<br />
e e<br />
ONO<br />
Oxide
~2xnm<br />
L0<br />
1xnm ~<br />
Read Window Margin Solution<br />
0V<br />
0V<br />
L1 L2 L3<br />
Vt Distribution Overlap due to;<br />
16<br />
Process Variation<br />
Data Retention Shift<br />
FG-FG Interference<br />
Controller<br />
Solution<br />
Smart Read Algorithm<br />
Strong ECC
Enhanced Solution Products<br />
Hynix; E2NAND<br />
[embedded-ECC]<br />
17<br />
Embedded Strong ECC Engine
Presentation Agenda<br />
NAND <strong>Flash</strong> Market Overview<br />
Technology Scaling Trend & Forecast<br />
Technology Scaling Limitation & Hurdle<br />
Future Technology Development Direction<br />
18
Planar FG with High-k IPD<br />
CG Gap-filling & Interference<br />
Thin FG structure with High-k IPD<br />
FG vertical scaling<br />
Conventional FG Structure<br />
19<br />
High-k IPD<br />
FG<br />
Active<br />
CG<br />
STI<br />
Planar FG Structure
3D Cell Structure Approach<br />
Stacked 3D with SONOS structure<br />
Stacked 3D with FG structure<br />
Si Pillar 3D with wafer bonding technology<br />
20
FG<br />
SONOS / TANOS<br />
History of 3D NAND <strong>Flash</strong><br />
~2006 2007 2008 2009 2010 2011<br />
Stacked NAND<br />
IEDM 2006<br />
Multi TFT<br />
IEDM2006<br />
S-SGT<br />
IEDM 2001<br />
BiCS<br />
VLSI Symp<br />
Si Pillar 3D NAND<br />
Semi. International 2007<br />
P-BiCS<br />
VLSI Symp<br />
TCAT<br />
VLSI Symp<br />
VG-NAND<br />
VLSI Symp<br />
VSAT<br />
VLSI Symp<br />
VG TFT<br />
VLSI Symp<br />
DC-SF<br />
IEDM<br />
High Process Cost 21 Low Process Cost<br />
: Macronix<br />
: The University of Tokyo<br />
Hybrid 3D<br />
IMW
Stacked 3D NAND <strong>Flash</strong> Concept<br />
SSL<br />
SCT<br />
DSL<br />
WL<br />
3D NAND Cell string<br />
DCT<br />
String 1 String 2 String 3 String 4<br />
Block<br />
22
Stacked 3D Cell Structures<br />
P-BiCS<br />
[VLSI 2009 by Toshiba]<br />
CG<br />
Charge<br />
Trap Layer<br />
Poly-Si<br />
Channel<br />
23<br />
TCAT<br />
[VLSI 2009 by Samsung]<br />
W Gate<br />
Charge<br />
Trap Layer<br />
Poly-Si<br />
Channel
Stacked 3D Cell Structures<br />
Hybrid Stacked 3D<br />
3D Cell Structure with Horizontal Poly-Si Channel<br />
[IMW 2011 by Hynix]<br />
24
Dual CG – Surrounding 3D FG Cell<br />
New 3D Structure Concept with FG cell<br />
Surrounding FG is controlled by two control gates.<br />
CG<br />
(upper)<br />
CG<br />
(lower)<br />
Single cell<br />
Channel poly<br />
Surrounding FG<br />
[IEDM 2010 by Hynix]<br />
25<br />
Tunnel oxide<br />
IPD<br />
*) Sung Jin Whang, et al, IEDM. 2010, pp.668-671
Si Pillar<br />
Si Pillar 3D Structure<br />
[Semi. International 2007 by BeSang Tech.]<br />
26<br />
Cell Strings<br />
Peripheral<br />
Region
Future Technology Analysis<br />
Technology Strong Points Weak Points<br />
Planar FG Friendly Structure High-k Dielectric Stability<br />
FG-3D<br />
Stacked 3D<br />
Si Pillar<br />
Reliability<br />
Small Interference<br />
Low Cost<br />
Small Interference<br />
Approved Materials<br />
Scalability<br />
27<br />
Scaling Limitation<br />
Stacking Limitation<br />
New Materials<br />
SONOS Reliability<br />
Wafer Bonding Cost<br />
SONOS Reliability
What are Decision Points ?<br />
Process<br />
Cost<br />
28<br />
Production Yield<br />
Reliability
Who is Winner at Post 1x or 1y nm ?<br />
?<br />
29
Somebody will find a solution.<br />
Thank you!
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