Annual Report 2002 and the Final Report of Stage 2

Annual Report 2002 

and the Final Report of Stage 2 

(2000 – 2002)

CCCD Annual Report 2002 (v1) Page 2(64) 

Summary 

The Competence Center for Circuit Design (CCCD) completed its second stage operation at the 

end of 2002. The evaluation of stage 2, performed by an international reviewing team, was a 

complete success. Since its formal foundation on January 1, 1998, CCCD has gone through two 

stages: stage 1 (1998-1999) and stage 2 (2000-2002). The collaboration agreement of stage 1 was 

signed by NUTEK (now VINNOVA), Lund University, and six companies: AgroVision AB (now 

Pharma Vision Systems AB), Cadence Design Systems AB, Ericsson Components AB (later as 

Ericsson Microelectronics AB, now Infineon Technologies Wireless Solutions Sweden AB), 

Ericsson Mobile Communications AB (now Ericsson Mobile Platforms AB), Ericsson Radio 

Systems AB (now Ericsson AB) and Telia Research AB. All partners of stage 1 signed the 

collaboration agreement of stage 2. In addition, AXIS Communications AB and SwitchCore AB 

joined CCCD in January 2000, and St. Jude Medical AB joined CCCD in September 2000, 

increasing the number of industrial partners to nine. Moreover, the National University of 

Singapore (NUS) has been the partner of Lund University since the beginning of the center. The 

annual budgets increased from 12.1 MSEK (1999) to 16.5 MSEK (2000) and 16.9 MSEK (2001, 

2000) respectively, contributed by the industry (40.8%), VINNOVA (35.5%) and Lund University 

(23.7%). 

The purpose of the center has been clear and unchanged since the beginning, i.e. to support 

Swedish industry by developing advanced competence in circuit and system design, producing 

trained personnel, transferring intellectual properties, and creating commercial opportunities. The 

major scientific goal of CCCD is to achieve a world leading position in system-on-chip design for 

future wireless communication systems, by means of carrying out active research in three major 

areas: Radio Frequency Analog Circuits, Mixed Signal Circuits, and Digital Application Specific 

Integrated Circuits. 

In stage 2, the center engaged 1 professor and 4 associate professors in Circuit Design, 5 

professors in other areas in the department, 2 professors in other departments, 4 industrial adjunct 

professors, 2 adjunct researchers and 36 research students (8 finished their studies). Among the 

students, 21 are financed and supervised through CCCD, and 15 are financed through other 

projects but supervised within or through the center. The research program includes 7 research 

projects and totally 31 work packages. To date, CCCD owns a spectrum of competence from 

monolithic radio front-end through analog and mixed signal ASIC to digital and ASIC-DSP. The 

competence in RF front-end circuitry, transmitter linearization, analog filters, high speed CMOS 

circuit technique, high performance A/D and D/A converters, DSP methodology and algorithm, 

digital arithmetic units, and on-chip clocking, is particularly well developed. 

Cooperation and contacts include 17 universities (13 abroad), 5 research institutes (4 abroad) and 

19 companies (10 abroad). Collaboration between academia and industry, including personal flow, 

has been improved continuously. Courses, seminars, workshops and project meetings were held 

regularly to promote knowledge dissemination. In stage 2, the research and collaboration have 

resulted in 3 Ph.D. degrees, 5 Licentiate degrees, 18 international journal papers or letters (6 in 

2002), 68 international conference papers (25 in 2002), 1 book chapter, 12 national conference 

papers (6 in 2002), 3 Ph.D. theses (2 in 2002), 5 Licentiate theses (1 in 2002), and 6 patents (1 in 

2002, all transferred to industrial partners). In addition, 8 graduate and 13 undergraduate courses 

were given, and 46 Master theses (17 in 2002) were supervised through the center. 

Jiren Yuan, Professor 

Director of CCCD


Table of contents 

Summary 2 

1. Performance and development 4 

1.1 Long-term goals and performance 4 

1.2 Internal cooperation and linkages 6 

1.3 International collaboration and contacts 8 

1.4 Technical Advisory Board to CCCD 9 

1.5 Relation to the host university 9 

1.6 The end-of-stage evaluation 10 

2. Research program and technical results 12 

2.1 Research projects 12 

2.2 Summary of work packages 15 

2.3 Technical results 19 

3. Academic outputs, education and other activities 26 

3.1 Academic outputs 26 

3.2 Education and training 27 

3.3 Workshops and meetings 28 

3.4 Other activities 30 

4. Partners and personnel 32 

4.1 Academic groups 32 

4.2 Industrial partners 32 

4.3 People engaged in CCCD 32 

5. Economic accounting 35 

5.1 Budget – result stage 2 35 

5.2 Allocation of resources per sub-area 35 

Appendix 1: Work packages, milestones and results 37 

Appendix 2: Publications 57 

Appendix 3: Collection of papers in CD


1. Performance and development 

1.1 Long-term goals and performance 

In stage 2 (2000-2002), CCCD has been adhered to the goal of supporting Swedish industry by 

developing advanced competence in circuit and system design, producing trained personnel, 

transferring intellectual properties, and creating commercial opportunities. The center has been 

working to achieve a world-class position in system-on-chip design for future wireless 

communications, focusing on developing integrated, low-voltage, low-power, analog/RF, mixed 

signal and digital circuits. With the major research area in wireless communication, the 

competence profile has been appropriately broadened to also cover other applications. 

The strategies to achieve the long-term goals have been the following. 

1. Collaborating with industrial partners: 

• To interact with industrial partners in strategy planning, project design, research education 

and knowledge dissemination. 

• To encourage Ph.D. students to interact with the research counterparts in the industrial 

partners. 

• To attract and engage new industrial partners related to circuit and system designs. 

• To properly broaden the research scope in order to support more industrial partners. 

2. Developing scientific competence: 

• To address advanced and challenging topics, e.g. low voltage, low power, and system-onchip. 

• To enroll dedicated Ph.D. students and leading scientists. 

• To invite internationally renowned scientists and to promote international cooperation. 

• To use advanced tools and technologies in research. 

• To create an active academic atmosphere through internal cooperation and discussion. 

• To encourage and to identify inventions with the help from the industry. 

3. Expanding the center. 

• To increase the mass of the center towards a world-class center by recruiting more 

industrial partners. 

• To attract more research and education funds from other funding sources than CCCD. 

• To recruit more faculty members and to engage more in-house professors as well as 

industrial adjunct professors and researchers. 

4. Educating people 

• To recruit more Ph.D. students, including industrial Ph.D. students, with attractive research 

topics and environment. 

• To educate Ph.D. students with both fundamental knowledge and creative skills by 

addressing real challenging problems. 

• To individually plan and evaluate the Ph.D. studies and to arrange at least two supervisors, 

a main and an assistant, for each Ph.D. student. 

• To improve the master education. 

The strategies have been proven crucial to CCCD’s success. In order to give an overall view of the 

development of CCCD in stage 2, three diagrams are given below. Fig. 1 is the number of Ph.D.


students engaged in CCCD in stage 2, increasing with time. Fig. 2 is the number of industrial 

partners and the annual budgets in stage 2, also increasing. Fig. 3 is the accumulative number of 

publications in stage 2. In all figures, data of stage 1 are shown as the background. 

Number 

of 

Ph.D. 

Studets 

Number 

of 

Industrial 

Partners 

40 

35 

30 

25 

20 

15 

10 

5 

0 

10 

8 

6 

4 

2 

0 

Other projects 

Supervised through CCCD 

Fully CCCD 

1998 1999 2000 2001 2002 

Fig. 1 The number of Ph.D. students engaged in CCCD. 

1998 1999 2000 2001 2002 

Fig. 2 The number of industrial partners and the annual budgets. 

18 

16 

14 

12 

10 

8 

6 

4 

2 

0 

Annual 

Budget 

in 

MSEK


Accumulative 

Number of 

Published 

Papers 

110 

100 

80 

60 

40 

20 

Fig. 1 concerns the goal of producing trained people. In stage 2, six students finished their studies 

and went to industry directly. Fig. 2 concerns the partners and budgets of stage 2. The annual 

budgets increased from 12.1 MSEK (1999) to 16.5 MSEK (2000) and 16.9 MSEK (2001, 2000) 

respectively, contributed by the industry (40.8%), VINNOVA (35.5%) and Lund University 

(23.7%). As can be seen from Fig. 1 and Fig. 2, the mass of the center has significantly increased. 

Fig. 3 concerns the publications. The journals include renowned journals like IEEE Journal of 

Solid-State Circuits and IEEE Transaction on Circuit and Systems etc., and the conferences 

include ISSCC, VLSI Symposium, ESSCIRC, CICC, ISCAS etc. Detailed technical results and 

scientific outputs can be found in Chapters 2 and 3. Concerning the goal of transferring intellectual 

properties, six patents (assigned or pending) have been transferred to our industrial partners in 

stage 2. A large number of activities, including annual workshops, seminars and courses, were 

carried out to disseminate knowledge and research results, with the participation of a large number 

of industrial people. 

1.2 Internal cooperation and linkages 

Collaboration within the center 

0 

Stage 2, international conferences 

Stage 2, international journals 

Stage 1, international conferences 

Stage 1, international journals 

1998 1999 2000 2001 2002 

Fig. 3 The accumulative number of publications. 

The CCCD Board consists of ten members, nine from industrial partners (one per partner) and one 

from Lund University, and is chaired by Dr. Peter Olanders of Ericsson AB. The Board holds five 

meetings in average every year of stage 2, making important decisions to steer the center’s 

performance and direction. The director of CCCD reports the progress and the issues to be 

decided to the Board. It has been shown that the Board is crucial to the success of CCCD, not only 

for its decisions but also the interactions at the highest level between the members and between the 

industry and academia. 

At the management level, the director, the senior administrative officer and the head of the 

department along with the faculty members manage the center. Faculty meetings were held every


two weeks to examine progress and make practical decisions. The secretarial work has been 

excellent. The management team as a whole has shown a highly cooperative manner in managing 

the center. 

In the center, there are three groups in Circuit design, i.e. Analog/RF, Mixed Signal and Digital 

ASIC. Close and constructive collaboration relationships have been established between them 

since the beginning and consolidated with time. The Analog/RF and Mixed Signal groups held 

meetings together every two weeks to report the progress and to disseminate the research results 

through formal and informal seminars, while the Digital ASIC group has its own meetings in the 

same manner. All three groups meet together once a month with the exchange of information and 

invited seminars. 

Initially, the academic involvement in CCCD was limited to the Circuit Design Group at the 

department, and since then it has engaged professors in Electromagnetic Theory, Signal 

Processing, and Radio Communications at the same department. Collaboration relations were also 

established with professors in other departments. In the first stage, only one non-Circuit-Design- 

Group professor was involved while five more have been gradually engaged in the research 

program since the second stage started. 

• Prof. Leif Sörnmo in Signal Processing has been involved since the first stage in the 

project Ultra Low Power DSP for Pacemakers (now WP 4-1). 

• Prof. Ove Edfors in Radio Communications has been involved in WP 4-3 Implementation 

of Iterative Decoders, WP 4-5 An OFDM Synchronizer: Algorithm to Silicon, WP 4-6 

Flexible Coding and Decoding for PAN, WP 4-7 Flexible FFT with Variable Scalability 

and Variable Dynamic Ranges for PAN, and WP 4-8 Algorithms and Hardware for MIMO 

Systems. 

• Prof. Gerhard Kristiansson and Associate Prof. Mats Gustavsson have been also involved 

in Project 6 Digital Holographic Imaging. 

• Professor Anders Karlsson in Electromagnetic Theory and Adjunct Professor Anders 

Derneryd in Antenna theory & Design have been involved in Project 7 Ultra Low Power 

Wireless Access Link. 

• Prof. Krzysztof Kuchcinski in Embedded System Design at the Department of Computer 

Science has been involved in WP 4-9 Design Space Exploration for SoC. 

• Prof. John B. Anderson in the Department of Information Technology has been involved 

in WP 4-10 Algorithm/HW Co-design of Coding Schemes. 

This created a very useful multi-disciplinary collaboration within the department and between 

departments. The collaboration with industrial partners is described in Chapter 3. 

Linkages to other Research Programs 

Besides the VINNOVA Competence Center program, CCCD has also been involved in the 

following research programs: 

• Telecommunication, a separate NUTEK program, 0.44 MSEK/year, finished June 2000. 

• INWITE (Integrated Technologies for Wireless Telecommunications), a separate 

VINNOVA/ VR and TEKES program, 0.9 MSEK/year. 

• INTELECT (Integrated Electronic Systems), an SSF financed program, 2.67 MSEK/year. 

• PCC (Personal Computing and Communication), an SSF financed program, 3.1 

MSEK/year. 

• Socware (system-on-chip-ware), a government financed program, 6 MSEK/year from 

2000.


• Pacwoman, an EU project, started March 2002, 0.6 MSEK/year in three years. 

Compared with all other programs, the VINNOVA Competence Center program is the most 

important one, in which CCCD is one of the 28 centers and the only one in Circuit Design. The 

importance is that without the VINNOVA Competence Center program, it is very difficult to 

establish a center like CCCD with a critical mass covering major research areas in circuit and 

system design. The center behaves as a core, a base and a carrier to host other programs. The 

funding of CCCD, presently 16.9 MSEK/year, occupies 56% of the overall funding in circuit and 

system design. Not only the faculty but also a substantial number of Ph.D. students (58%) are 

directly financed through the center. It should also be mentioned that the cooperation and 

interaction with industry have been more effective through the center. While research activities do 

not directly finance teaching, it is safe to assert that without a living research environment it 

would be difficult to offer students the highest level of teaching. Because CCCD, Socware and 

other funding agencies provide research opportunities for teachers, LTH’s Department of 

Electroscience is able to offer a level of education comparable to that offered by major research 

institutions. 

1.3 International collaborations and contacts 

The center is known internationally, and collaborations and contacts were established and 

continued worldwide: 

• UCLA (USA), Oulu University (Finland) and Victoria University (Australia), concerning RF 

front-end circuitry and architectures 

• UCLA (USA), Purdue University (USA), University of Minnesota (US), UCB/BWRC (USA), 

IMEC (Belgium) and SINTEF (Norway), concerning low power and high performance digital 

design 

• UCSB (USA), concerning implementation of synchronization algorithms 

• Nordic VLSI (Norway) concerning digital video broadcasting 

• VINNOVA/TEKES-program INWITE, concerning low voltage integrated receiver and 

transmitter structure in cooperation with Oulu University (Finland), NOKIA (Finland), 

Ericsson AB (Sweden) and Ericsson Mobile Platforms (Sweden) 

• National University of Singapore, concerning co-training of Ph.D. students 

• Agere Systems (USA), concerning chip manufacturing 

• Texas Instruments (USA), concerning potential co-operation 

• VIA Technologies (Taiwan), concerning potential co-operation 

• Kyocera Corporation (Japan), concerning potential co-operation 

• Sony Corporation (Japan), concerning potential co-operation 

• Nokia Danmark A/S (Nokia Mobile Phones R&D), concerning master's projects and beyond 

• Semiconductor Technology Research Center (Japan), concerning potential co-operation 

CCCD is a member of HERMES (a European research network in the field of wireless 

communication) consisting of major centers and organizations in this field in Europe: 

• IMEC (Leuven, Belgium) 

• CSEM (Neuchâtel, Switzerland) 

• NTUA (Athens, Greece) 

• VTT (Helsinki, Finland) 

• Lund University, CCCD (Lund, Sweden) 

• University of Cantabria (Cantabria, Spain) 

• CPK, University of Aalborg (Aalborg, Denmark) 

• LETI (Grenoble, France)


• Aachen University of Technology (Aachen, Germany) 

• FTW (Wien, Austria) 

• CMPC, Delft University of Technology (Delft, the Netherlands) 

• FOCUS, the Fraunhofer Institute for Open Communication Systems (Berlin, Germany) 

• CCSR, University of Surrey (Guildford, UK) 

From March 2002, CCCD also participates in the EU project Pacwoman. 

1.4 Technical Advisory Board to CCCD 

In 2000, three international experts were invited to form the Technical Advisory Board to CCCD. 

They are 

Professor Jan Rabaey, University of California at Berkeley, USA, 

Dr. Ivo Bolsens, IMEC, Leuven, Belgium, (now at Xilinx, USA) and 

Professor Ernst Bonek, Technical University of Wien, Austria. 

The first advisory meeting was held in August 2000. The Technical Advisory Board was 

impressed by the depth and scope of the high quality individual projects and in the same time gave 

the recommendation on the need of global focus. The faculty carefully studied the advice and 

responded with corresponding adjustments in the research program. As a result, the separate small 

projects were integrated into seven projects with totally 20 work packages, focusing on the circuit 

core research and closely related to each other 

The second advisory meeting was held in August 2001 in conjunction with CCCD Workshop 

2001. The Technical Advisory Board congratulated the excellent progress of CCCD. The advisors 

were interested in the overview talks, the selected student talks, the posters and the demonstrations 

of the Workshop. In particular, the advisors were impressed by the high quality of individual 

projects, the enthusiasm, the involvement of industry, the growing interest, and the work on 

relevant problems. The major recommendations were the need of milestones, self-assessment, and 

integrated perspective. After the meeting, milestones, deliverables and final goals were defined for 

every work packages, and progress reports were required, see Appendix 1 of this report. New work 

packages in different projects aiming at a flexible radio terminal were installed in the middle of 

2002, which requires the united effort of students in different areas from three groups, which 

improves the interacted perspective. 

The third advisory meeting was held in October 2002 in conjunction with CCCD Workshop 2002. 

The advisors congratulated the success of the workshop, the great results, in particular the 

increased focus and the new project being the common integrator. The major recommendations 

were the need of system design via chosen drivers, and keeping eyes on the future. The responses 

to the recommendations can be found in section 1.6 “The end-of-stage evaluation” and chapter 3 

“Research program and technical results” in this report. 

More detailed descriptions of the recommendations and responses can be found in “Report to the 

International Evaluation Group”, distributed in September 2002. 

1.5 Relation to the host university 

CCCD is one of four VINNOVA competence centers at Lund University. Lund University is one 

of the three parties of CCCD (the other two is VINNOVA and the industry) and the host 

university. It contributes 4 MSEK in emolument, i.e. 23.7% of the total CCCD annual budget. The 

representative of Lund University is the member of CCCD Board, steering the center along with


other members from each of the industrial partners. Lund University is obligated to assign the 

director and the board members of CCCD. 

During its earliest developmental stage, CCCD initiated the System-on-Chip research that led to 

LTH’s receiving a host position for the university-related sub-programs in the Socware program, a 

nation-wide program, which is financed by the government. LTH hosts both the Education and the 

Research sub-programs within Socware, and CCCD has played an important role in promoting the 

programs. One of the faculty members, Dr. Peter Nilsson, is the manager of the aforementioned 

two sub-programs, and the representative of LTH, Dr. Clas Agnvall, is in the Socware Board. The 

1.5-year Socware Master Education program started in September 2000 and went well in 2001 and 

2002. New courses related to system-on-chip were developed, and highly industry-relevant new 

master projects in Socware were implemented. The Education program in Socware has already 

produced new Masters of Science in this field. The Socware Research program started in the 

beginning of 2002, and will be as successful as the Education program. 

As the Dean of LTH (Lund Institute of Technology), Prof. Gunilla Jönson, puts it, LTH is proud to 

be the host of CCCD. The presence of CCCD has increased the industrial relevance of research, 

improved the graduate and undergraduate education at LTH. During the last decade, the 

information technologies have introduced new demands on university research and education, 

concerning system knowledge and industrial relevance. The activities within CCCD are one way 

of meeting these demands. The research program of CCCD lies well within the strategic research 

plan of LTH and forms a vital part of the effort in Infocom (a united name of research and 

education in information & communication technology, involving six departments) at LTH. The 

Infocom program involves six departments, four externally financed research program and a new 

Master of Science program. 

1.6 The end-of-stage evaluation 

On the 3 rd of October, 2002, the scientific experts of the international evaluation team, Professors 

Marc Engels, IMEC, LoraNet N.V., Belgium, and Veikko Porra, Helsinki University of 

Technology, Finland, visited the Competence Centre for Circuit Design at Lund University. They 

were briefed by the technical staff of CCCD on seven established scientific projects. The 

presentations were delivered by professors, project managers and scientists. 

On the following day, the 4 th of October, 2002, the entire review committee, made up of the 

aforementioned scientific experts and the Competence Centre experts, Professors John S. Baras, 

University of Maryland, USA, and Per Stenius, Helsinki University of Technology, Finland, was 

briefed on general issues concerning CCCD, impact on education, as well as research issues with 

emphasis on the Competence Centre concept, interaction with industry, vision and strategy. 

Representatives of the Department of Electroscience and industrial partners of CCCD made 

presentations, and actively participated in the general discussion. 

The international review committee considers the evaluation of stage 2 was a success, not only 

because it produced a good evaluation report, but also because it showed a very good team work 

and cooperation within CCCD fulfilled by the industrial partners, the faculty, the students, the 

department, and the management team, which is even more important for the future. 

The international review committee highly evaluated the performance of CCCD in stage 2: 

• Impressive progress since 1999, and responded very well to the recommendations of 

review’99. 

• Successful cooperation with industrial partners.


• Attractive scientific program with broadened disciplines and research scope since 1999. 

• Achievements are beyond initial expectations. 

• Well recognized technical competence in Europe and good academic contacts 

internationally. 

• Substantial contributions to research and education. 

• Very satisfactory industrial involvement and added values. 

In the same time, the committee gave the general recommendations in its evaluation report, see 

below. 

• Develop a plan that explicitly involves components in system level design and integration, 

and in particular joint top-down and bottom-up design methodologies. This would require 

organization of part of the work programme around a limited number of driver 

applications. 

• Special attention should be paid in the next strategic plan towards the following topics: 

• the dissemination strategy for design technology 

• a more active publication policy 

• a coordinated effort towards continuing education. 

• Faculty from outside Circuit Design should be more actively involved not only in single 

project planning and execution but also in overall strategic planning, especially in view of 

the first recommendation above. 

CCCD appreciated the recommendations and responded with new actions to be taken and special 

attention to be paid in stage 3, see below. 

(1) The following actions will be taken in the third stage. 

• The major action will be to modify the research plan in such a way that the system 

design is appropriately emphasized: 

- A new project named Flexible Radio Terminal has been added to the research plan 

of stage 3. 

- New driver applications and/or new work packages in existing driver applications 

such as the Ultra Low Power Wireless Link and Digital Holographic Imaging will 

be identified. The model of “Application – System level – Implementation” will 

be applied for both long-term and short-term driver applications. 

• The competence profile will be expanded by involving (recruiting) experts in system 

level design. 

• Detailed system level specifications of driver applications will be identified. 

• Components for the system level design and integration of the driver applications will 

be identified and implemented. 

• The publications plans are required in the milestones. 

• Clear milestones and progress reports for all work packages are required. 

(2) Special attention will be paid in the third stage in the following aspects 

• Development of a more efficient mechanism for disseminating project results to the 

industry, e.g. distribute CDs of paper-collection from now on 

• More active in marketing and delivering short courses and project results to industry. 

• Improvement of university education in the area of circuit and system design.


2. Research program and technical results 

2.1 Research projects 

The research program in stage 1 (1998-1999) was divided into three main areas: Analog and Radio 

Frequency Circuit Design, Mixed Signal Circuit Design, and Digital ASIC Design. The areas were 

further divided into 10 sub-areas and 20 projects. This program was revised in the beginning of 

stage 2 (2000-2002) into 7 lumped projects, with the purpose of increasing the interaction between 

individual small projects and broadening the research scope, see below. To the end of stage 2, 

there were totally 31 work packages, see Table 1 in section 2.2. 

Project 1: Monolithic Transceivers 

Project leader: Dr. Henrik Sjöland, LU, CCCD-financed 

Dr. Pietro Andreani, LU, CCCD-financed (until Nov 2001) 

Supervisors: Dr. Pietro Andreani, LU, CCCD-financed (at DTU from Dec 2001) 

Dr. Henrik Sjöland, LU, CCCD-financed 

Adj. Prof. Lars Sundström, Ericsson Mobile Platforms 

Adj. Prof. Sven Mattisson, Ericsson Mobile Platforms 

Prof. Jiren Yuan, LU, Faculty-financed 

Industrial partners: Ericsson Mobile Platforms AB 

Ericsson Radio Systems AB (now Ericsson AB) 

Ericsson Microelectronics AB (now Infineon Technologies Wireless 

Solutions Sweden AB) 

Industry researchers: Dr. Thomas Mattsson, Ericsson Mobile Platforms AB 

Students: 7 students, see Table 1 in next section 

Project description: With the increased requirements on the performance of analog circuits 

and the use of mainstream CMOS technologies, a large effort is required to further develop circuit 

theory, design methodologies and circuit topologies for traditional analog building blocks such as 

amplifiers, filters, oscillators, mixers etc. It is also necessary to study what can be gained by 

breaking the limitations imposed by the partitioning of the transceiver into building blocks. For 

instance, two or more traditional building blocks can be merged into one in order to increase the 

performance. Furthermore, the undesired interactions between different parts of a monolithic 

transceiver should be studied. To reduce power consumption, the analog circuits should be 

adaptive, so that they can provide just the performance needed at that moment, since a higher 

performance would result in a waste of power. 

Project 2: Linear Transmitter Architecture 

Project Leader: Adj. Prof. Lars Sundström, Ericsson Mobile Platforms AB 

Supervisors: Adj. Prof. Lars Sundström, Ericsson Mobile Platforms AB 

Prof. Pietro Andreani, DTU 


Industrial partners: Ericsson Mobile Platforms AB 




Industry researchers: Dr. Scott Leyonhjelm, Ericsson Radio Systems AB (now Ericsson AB) 

M.Sc. J. Mannerstråle, Ericsson Mobile Platforms AB 

Students: 4 students, see Table 1 in next section


Project description: One of the most challenging parts of a wireless communication system is 

the transmitter as it consumes a substantial amount of power, and its power efficiency is therefore 

crucial. Several prospective systems will use modulation schemes that will substantially increase 

the requirements on the transmitters in terms of linearity. To obtain a high degree of linearity 

while maintaining a high power efficiency, linearization techniques must be applied. Both analog 

and digital techniques are studied, to find out which is best suited for different applications. It 

should also be investigated what can be accomplished with monolithic systems featuring power 

amplifier and linearization circuitry on the same chip. 

Project 3: Mixed Signal Circuit Design 

Project leader: Prof. Jiren Yuan, LU, Faculty-financed. 

Supervisors: Prof. Jiren Yuan, LU, Faculty-financed 


Industrial partners: Ericsson Microelectronics AB (now Infineon Technologies Wireless 



Ericsson Mobile Platforms AB 

Industry researchers: Dr. Gunnar Björklund, Ericsson Microelectronics AB 

Dr. Jan-Erik Eklund, Ericsson Microelectronics AB (now Infineon 

Technologies Wireless Solutions Sweden AB) 


Project description: A/D and D/A converters are the bottlenecks of high performance 

heterogeneous systems. Embedded A/D and D/A converters are especially challenging. The 

research topics to be addressed in the project are wide dynamic range, accurate signal sampling, 

high speed, high resolution and low glitch operation. The intention is to design embedded A/D and 

D/A converters specialized for broadband radio signals. Efficient and non-traditional approaches 

are to be identified in achieving high performance. Low voltage and low power are considered as 

important merits for the solutions. Another important topic of this project is the design techniques 

for mixed signal systems on chip. With the highest density and lowest cost, CMOS is considered 

the main technology for a single chip system. Unfortunately, the digital part emits strong transition 

noise, seriously disturbing the on-chip receiver and A/D converter. In the analog part, the strong 

transmitter and oscillator signals also cause problems. The performance of such a chip will to a 

large extent depend on design techniques capable of decoupling different parts. This is one of the 

necessary conditions for a successful system-on-chip approach. Techniques for reducing substrate 

noise and cross talks are to be explored. 

Project 4: System Integration and Hardware Accelerators 

Project leader: Dr. Peter Nilsson, LU, CCCD-financed 

Dr. Viktor Öwall, LU, CCCD-financed 

Supervisors: Dr. Peter Nilsson, LU, CCCD-financed 


Adj. Prof. Mats Torkelson, Ericsson Radio Systems AB (now Ericsson 

AB) 

Dr, Bengt-Arne Molin, AXIS Communications AB 

M.Sc. Anders Olsson, AXIS Communications AB 

M.Sc. Kerstin Lindh, AXIS Communications AB 

Prof. Ove Edfors, LU, CCCD-financed 

Prof. Leif Sörnmo, LU, CCCD-financed


Prof. John B. Anderson, LU, Dept of IT 


Industrial partners: AXIS Communications AB 





Telia Research AB 

St. Jude Medical AB 

Industry researchers: Dr. Shousheng He, Ericsson Mobile Platforms AB 

M.Sc. Erik Hertz, Ericsson Mobile Platforms AB 

Dr. Christian Bergljung, Telia Research AB 

Dr. Peter Karlsson, Telia Research AB 


Project description: A larger research project regarding both system integration and 

architectural design considerations has been initiated. The project will investigate new design 

methodologies and new architectures on a system level to reach efficient solutions, taking into 

account all levels of circuit design. One area is the development of hardware accelerators to reach 

a higher calculation capacity and/or reduced power consumption than is achievable with off-theshelf 

solutions. By working together with theoretical researchers to investigate the field of 

algorithm/hardware co-optimization, algorithmic trade-offs between performance and 

implementation complexity can be made. Furthermore, by investigating application specific 

solutions with a tailored architecture and a streamlined dataflow, the performance in any measure 

can for most algorithms be reduced by one or several orders of magnitude. One key question is 

system partitioning into different hardware entities and how to schedule the dataflow between 

them. Another key issue is how to be able to use implementation feedback at an early stage of the 

system and algorithm development process. Issues of controller synthesis, system partitioning and 

system level architectural design will be addressed. 

Project 5: Digital Building Blocks and Implementations 

Project leader: Dr. Peter Nilsson, LU, CCCD-financed 

Dr. Viktor Öwall, LU, CCCD-financed. 



Adj. Prof. Mats Torkelson, Ericsson Radio Systems AB (now Ericsson 

AB) 

Dr. Lars Svensson, Ericsson Mobile Platforms AB (when he was there) 


Industrial partners: Ericsson Radio Systems AB (now Ericsson AB) 




Industry researchers: Dr. Shousheng He, Ericsson Mobile Platforms AB 


Project description: Key components of digital circuits have to be implemented and are then 

used in other projects as building blocks. There are also the generic design techniques regarding 

for instance arithmetic explorations and on-chip clocking strategies. Complex multiplier/divider 

implementation, clocks, encoder/decoder, and FFT design are part of this research.


Project 6: Digital Holographic Imaging 

Project leader: Peter Egelberg, Neural AB, CCCD-financed. 

Supervisors: Dr. Viktor Öwall, LU, CCCD-financed 

Dr. Peter Nilsson, LU, CCCD-financed 

Prof. Gerhard Kristiansson, LU 

Dr. Mats Gustafsson 

Dr. Sven-Göran Pettersson, LU 


Industrial partners: Pharma Vision Systems AB 

Industrial researcher: M.Sc. Mikael Sebesta 

Student: 1 student, see Table 1 in next section 

Project description: The objective is to recreate the image of an object from the interference 

pattern generated on the sensor surface by a reference laser beam and the reflections from the 

object. Inverse algorithms and VLSI implementations are to be explored. The goal is to create 

computer-based high resolution and live images for medical and other microscopy applications. A 

very high calculation complexity and a very high data flow calls for application specific solutions. 

Project 7: Ultra Low Power Wireless Access Link 

Project leader: Prof. Anders Karlsson, LU, CCCD-financed 


Supervisors: Prof. Anders Karlsson, LU 




Industrial partners: St. Jude Medical AB 

Industry researchers: M.Sc. Hans Abrahamson, Senior Engineer, St. Jude Medical AB 

Adj. Prof. Anders Derneryd, Ericsson Microwave Systems AB 

Students: 1 student, see Table 1 in next section 

Project description: The objective is to explore a near-distance wireless access link with one 

end being either passive or consuming ultra low power. This is significant in medical applications, 

for instance to extract data from implanted medical instruments or sensors. It is also very useful in 

other applications where the power consumption must be kept extremely low. 

2.2 Summary of work packages 

Table 1: Summary of work packages 

No. Work package Student/researchers Supervisor(s) 

1. WP 1-1 Monolithic Oscillators and 

Filters 

2. WP 1-2 Adaptive Front-End for 

GSM 

3. WP 1-3 Low-Noise Amplifiers and 

Mixers 

Dr. Pietro Andreani, LU, 

CCCD-financed ( 9801- 

0111) 

M.Sc. Laurent Durkalec, 

CCCD-financed (9901- ) 

M.Sc. Torbjörn Sandström, 

SSF-financed (9801-0010) 

M.Sc. Anna-Karin Stenman, 

SSF-financed (9705-0205) 

Dr. Lars Sundström, 

EMP, CCCD-financed 


EMP, CCCD-financed


4. WP 1-4* Low-Voltage Oscillators 

with Quadrature Generation 

5. WP 1-5* Low-Voltage Low-Noise 

Amplifiers and Mixers 

6. WP 1-6* Integrated transmitters for 

3 rd generation mobile 

phones 

7. WP 2-1 Linearization Using Analog 

Circuit Techniques 

8. WP 2-2 Linearization Using Analog 

Predistortion 

9. WP 2-3 Linearization Using Digital 

Predistortion 

10. WP 2-4 High-Efficiency Linear 

Transmitter Architectures 

11. WP 3-1 Wide Dynamic Range A/D 

Converters 

12. WP 3-2 Low-Glitch and RF D/A 

Converters 

13. WP 3-3 High Speed Early Sampling 

and Digitizing Technique 

14. WP 3-4 Design Techniques for 

Single Chip Mixed Signal 

Circuits and Systems 

15. WP 3-5* Re-configurable Low- 

Power A/D converter for a 

Flexible Radio Terminal 

16. WP 4-1 Ultra Low Power DSP for 

Pacemakers 

17. WP 4-2 Controller Synthesis and 

Processor Communication 

M.Sc. Niklas Troedsson, 

CCCD-financed (0101-) 

M.Sc. Fredrik Tillman, 

SSF-financed (0007-) 

Tech. Lic. Pieternella 

Cijvat, CCCD-financed 

(0102-) 

M.Sc. Bo Shi, Facultyfinanced 

(9709-0109) 

M.Sc. Eric Westesson, 

VINNOVA-financed 

(INWITE) (9806-0110) 

M.Sc. Weiyun Shan, 

VINNOVA-financed 

(INWITE) (9910-0208) 

M.Sc. Roland Strandberg, 

Faculty-financed (9808-) 

M.Sc. Johan Piper, Facultyfinanced 

(9902-) 

M.Sc. Yijun Zhou, Facultyfinanced 

(9905-) 

B.Sc. Lixin Yang, CCCD- 

financed (0011-) 

M.Sc. Gang Xu, CCCDfinanced 

(9910-) 

M.Sc. Konstantinos 

Theodoropoulos, CCCDfinanced 

(0009-) 

M.Sc. Martin Andersson, 

Socware-financed (0204-) 

Dipl. Ing. Joachim 

Rodrigues, CCCD-financed 

(9909-) 

M.Sc. Hongtu Jiang, SSFfinanced 

(0010-) 

Dr. Henrik Sjöland, 

LU, CCCD-financed 













Dr. Pietro Andreani, 

DTU 

Prof. Jiren Yuan, LU, 

CCCD-financed 

Dr. Jan-Erik Eklund, 

Ericsson 

Microelectronics, 

CCCD-financed 


CCCD-financed 




CCCD-financed 


Ericsson 


CCCD-financed 


CCCD-financed 


Ericsson 


CCCD-financed 


CCCD-financed 



Dr. Viktor Öwall, LU, 

CCCD-financed 

Prof. Leif Sörnmo, 



CCCD-financed 

Adj. Prof. Mats


18. WP-4-3 Implementation of Iterative 

Decoders 

19. WP 4-4 Hardware/Software Co- 

Optimization for Echo 

Cancellation 

20. WP 4-5 

An OFDM Synchronizer: 

Algorithm to Silicon 

21. WP 4-6* Flexible Coding/Decoding 

for PAN 

22. WP 4-7* Flexible FFT with variable 

scalability and variable 

dynamic ranges for PAN 

23. WP 4-8* Algorithms and Hardware 

for MIMO Systems 

24. WP 4-9* Design space exploration 

for SoC 

M.Sc. Pontus Åström, SSF- 

and CCCD-financed 

(9801-0212) 

M.Sc. Anders Berkeman, 

CCCD-financed (9801-) 

M.Sc. Stefan Johansson, 

CCCD- and SSF-financed 

(9801-0005) 

Dipl. Ing. Matthias Kamuf, 


Fredrik Kristensen, CCCDfinanced 

(AXIS, Hermes) 

(0109-) 

M.SC. Zhan Guo, SSFfinanced 

(0104-) 

M.Sc. Henrik Svensson, 


Torkelson, Ericsson, 

CCCD-financed 

Dr. Peter Nilsson, LU, 

CCCD-financed 

Prof. Ove Edfors, LU, 

CCCD-financed 

Adj. Prof. Mats 


CCCD-financed 


CCCD-financed 



CCCD-financed 


CCCD-financed 


CCCD-financed 



CCCD-financed 


CCCD-financed 


CCCD-financed 


CCCD-financed 

Prof. John B. 

Anderson, LU 


CCCD-financed 


CCCD-financed 


CCCD-financed 

Dr. Bengt-Arne Molin, 

AXIS 

M.Sc. Anders Olsson, 

AXIS 

M.Sc. Kerstin Lindh, 

AXIS 


CCCD-financed 


CCCD-financed 


CCCD-financed 



CCCD-financed 


CCCD-financed


25. WP 4- Algorithm/HW co-design M.Sc. Karl Thoren, SSF- 

Prof. Krzysztof 

Kuchcinski, LU 


10* of Coding Schemes financed (0201-) 

CCCD-financed 

Prof. John B. 

Anderson, LU 

26. WP 4- ASIC Implementation of M.Sc. Fredrik Edman, SSF- Dr. Viktor Öwall, LU, 

11* Algorithms for Adaptive financed (0201-) 

CCCD-financed 

Antennas 



CCCD-financed 

Dr. Peter Karlsson, 

Telia Research 

27. WP 5-1 Implementation of M.Sc. Anders Berkeman, Dr. Viktor Öwall, LU, 

Complex Multiplier CCCD-financed (9801- CCCD-financed 

0212) 



CCCD-financed 

28. WP 5-2* Content Addressable M.Sc. Hugo Hedberg Dr. Peter Nilsson, LU, 

Memories – CAMs starting 2003-03-01, CCCD-financed 

CCCD-financed 


CCCD-financed 

Dr. Lars Svensson, 

Chalmers University 

of Technology 

29. WP 5-3* Distributed asynchronous M.Sc. Thomas Olsson, Dr. Peter Nilsson, LU, 

custom DSP-systems SSF-financed (0201-) CCCD-financed 


CCCD-financed 

30. WP 6-1* HW accelerators for Two- M.Sc. Thomas Lenart, Dr. Viktor Öwall, LU, 

dimensional signal CCCD-financed (0112-) CCCD-financed 

processing 

Dr. Mats Gustavsson, 

CCCD-financed 

31. WP 7-1* Link budget and antennas Lic. Anders Johansson, Prof. Anders Karlsson, 

CCCD-financed (0105-) CCCD-financed 



1. The first number (X) in WP X-Y indicates the number of project it belongs. 

2. The work packages written in italic text are in the sleep mode to the end of stage 2. 

3. The work packages with * are new or relatively new projects which have impacts on the 

coming 3-5 year, i.e. the 3 rd stage and beyond. Their starting time can be found in the table. 

From Table 2, one can see that among the 31 work packages, 6 work packages went to the sleep 

mode due to the departure of finished students, but totally 13 new work packages have be 

installed. These new work packages are designed to more closely link each other for the purpose 

of demonstrating the concept of system-on-chip, and some of them directly serve for a flexible 

radio terminal, a new part of the research program. The research in the coming 3-5 years is 

therefore highlighted, and the continuation of the research in these key areas is secured. See below 

for the description of Flexible Radio Terminal, a new project co-funded by CCCD, Socware, 

INTELECT, and the EU project Pacwoman.


Description of the new project Flexible Radio Terminal 

In the future, it is envisioned that systems with both high and low bit rates will co-exist and 

exchange information. Furthermore, there will be several types of standards working together with 

completely different sets of requirements. Applications such as battery-operated very low bit rate 

sensor networks will operate together with radio LAN’s at considerably higher rates, i.e. some 

devices will be multiple standard radios while others will be single functions in the personal area 

environment. Therefore, there will be a need for new flexible platforms that are able to adapt to 

different system configurations. Communication gadgets will vary from extremely low power 

devices with very low communication possibilities to high-end devices covering the full range of 

communication standards. Instead of optimizing for one particular system, the circuitry, hardware, 

and software, analog as well as digital, will have to be able to change depending on the 

requirements. 

The Flexible Radio project focuses on developing circuits and system specifications for such a 

scenario, where System-on-Chip is the leading theme. All types of silicon design are used, 

including, analog/RF, mixed signal, and digital baseband. All abstraction levels are included as 

well, from physical layer to system level. A SoC radio can be a small, low-bit-rate radio 

containing RF circuitry, AD/DA-conversion, and application specific digital circuitry. Another 

example is a high bit rate radio where the baseband circuitry consists of both optimized hardware 

and embedded software. In both cases, CMOS is a suitable technology, since it is feasible to 

design both analog and digital circuitry at low cost. Several projects are planned within the area of 

Flexible Radio for the next five-year period. These include, flexible CMOS radio front-ends, 

flexible AD/DA-converters, flexible OFDM building blocks, flexible multiple-adaptive antenna 

systems, flexible coding/decoding algorithms, and SoC platforms for flexible terminals. 

2.3 Technical results 

Project 1: Monolithic Transceivers 

Oscillators 

A novel technique for reducing oscillator phase noise in differential oscillators was discovered by 

Henrik Sjöland together with Emad Hegazi and Asad Abidi. By adding an LC-filter to the tail 

current source, the high frequency noise of the current source was prevented from reaching the 

oscillator and being converted into phase noise. Furthermore, by tuning the inductor correctly the 

noise of the differential pair was also reduced. This work was very well received, and has been 

presented at ISSCC and in JSSC. 

A new technique for low phase noise monolithic CMOS VCO's was invented by Pietro Andreani 

and Henrik Sjöland. By adding an off-chip inductor in series, the low-frequency noise of the tail 

current source can be prevented from being up-converted into phase-noise. The technique is most 

effective when combined with the on-chip noise filtering technique (described above), which 

eliminates the effect of high frequency tail current noise. The work has been presented at CICC, 

VLSI symposium, and in JSSC. 

A new high-performance quadrature oscillator topology was discovered by Pietro Andreani. The 

conventional quadrature oscillator is made from two coupled differential oscillators. The coupling 

is realized by transistors controlled by one oscillator being parallel to and injecting current into the 

other, and vice versa. The new idea is to use series connected coupling transistors. The result is a 

dramatic improvement in both power consumption and phase noise. This work has been presented 

at ISSCC.


A very low voltage differential CMOS oscillator designed by Niklas Troedsson has been 

fabricated at Agere Systems. The oscillator uses an inductor tuned to twice the operating 

frequency instead of an active tail current source, as described by Emad Hegazi, Henrik Sjöland 

and Asad Abidi. The idea was to combine such a topology with an amplitude control adjusting the 

gate bias, to get control of the current consumption and to keep the node voltages within bounds. 

The oscillator works fine, and has been presented at Asia-Pacific and RawCon. 

A new technique for improved switched frequency tuning of differential CMOS circuits was 

discovered by Henrik Sjöland. The idea is to use only one switch device in the differential signal 

path, instead of the usual two. This results in a doubled performance in terms of quality factor, or 

frequency of operation. This has been published in TCAS-II. 

LNA’s and mixers 

A very low voltage CMOS chip containing a low-noise amplifier and a mixer designed by Fredrik 

Tillman has been fabricated. At a supply voltage of just 1V, the measured performance by far 

exceeds the Bluetooth requirements. This has been presented at ESSCIRC’2002. 

A new technique for optimizing the noise performance of a CMOS LNA has been invented by 

Henrik Sjöland and Pietro Andreani. The idea is to add an additional capacitance between gate and 

source of the input device in an inductively source degenerated LNA. The result is a suppression 

of the influence of the gate-induced noise, which otherwise typically dominates. This work has 

been published in TCAS-II, and is also the subject of a patent application. 

A front-end for a W-CDMA direct conversion receiver in 0.35um CMOS has been designed by 

Henrik Sjöland together with Ali Karimi and Asad Abidi. The idea was to merge an inductively 

source-degenerated LNA and an double-balanced active mixer, thereby gaining linearity and 

reducing power consumption. The measurements proved this to fulfil the requirements of W- 

CDMA, and the work has been presented at VLSI symposium, and submitted to JSSC. 

Anna-Karin Stenman has defended her licentiate thesis “Some Design Aspects on RF CMOS 

LNAs and Mixers”, which mainly dealt with matching between passive CMOS mixers in imagereject 

receivers, and the effect of gate-drain capacitance on the input impedance and noise figure 

of CMOS Low Noise Amplifiers. She has now left the university to work at Acreo. Torbjörn 

Sandström also presented his Licentiate Thesis, with the title “CMOS Receiver Design”. He has 

also left the university and now works at the company Semcon. 


Linearization using analog circuit techniques 

Bo Shi has designed CMOS circuits for power feedback linearization of RF power amplifiers. The 

idea is that the circuit becomes simpler by regarding only the power of the input and the output 

signals. In a feedback system including power detectors, a variable-gain amplifier (VGA) is 

controlled to make the output power proportional to the input. The result is a high operating 

frequency and a low power consumption. In 0.6um CMOS the power consumption is 62mW and a 

power amplifier operating at 850MHz can be linearized. The reduction of out of band power is 

about 10dB. A journal paper was recently published, in addition to the previous publications. 

Bo Shi has also made signal component separator (SCS) circuits for the LINC architecture. In this 

architecture the signal is separated into two constant envelope signals, with are separately 

amplified in two non-linear power amplifiers. After the two amplifiers the signals are added


together (combined). The work of the SCS is to generate the two constant envelope signals. The 

realization of this requires synthesis of non-linear functions, and to achieve high bandwidth and 

low power this was done analog. Circuits have been designed in BiCMOS as well as pure CMOS. 

The measurements have shown a high performance, and the work has resulted in a number of 

recent publications in conferences and journals (JSSC, VLSI symposium, CICC, ESSCIRC, 

Vehicular Technology Conf., ISCAS). Bo Shi received his Ph.D. degree in September 2001 and 

returned to Singapore afterwards. 

Linearization using analog predistortion 

Eric Westesson has designed a predistortorter chip in 0.35um CMOS, which worked well. It was 

presented at a recent conference (ESSCIRC). Eric Westesson is currently writing his licentiate 

thesis. 

Linearization using digital predistortion 

Predistortion is a powerful method for linearization of RF power amplifiers; however, the linearity 

performance of a predistortion system is limited by various memory effects. In this project, we 

investigate the effects of filters between the predistorter and the power amplifier. Filters are used 

to provide sufficient rejection of image signals, and can be of low pass type, like the reconstruction 

filters in the baseband predistorter, or bandpass type, like the filters in IF predistorters. The effects 

of these filters are studied by means of both analysis and simulation for multi-carrier signals. 

The work has resulted in three recent conference papers (Vehicular Technology Conf., MTT-S 

Microwave Symposium, ECCTD), in addition to the Licentiate Thesis. Weiyun Shan received her 

Licentiate degree in August 2002, and then returned back to Singapore. 

High-Efficiency Linear Transmitter Architectures 

The CALLUM 2 architecture was chosen due to its limited computational complexity for the 

generation of the drive signals. Roland Strandberg has implemented several blocks in a 0.35um 

CMOS process at schematic level. Apart from the core of the architecture, add on circuitry such as 

frequency synchronization and DC level control was also implemented. New issues have been 

detected during the work, as the architecture’s limited ability to acquire lock. One solution to this 

problem is to use a VGA to be able to adjust the loop gain during the pull-in process. The work 

has resulted in a conference paper this year (ISCAS). 


There are totally five work packages in this project. Among them, the latest started in April 2002. 

The research topics include Wide Dynamic Range A/D Converters, Low-Glitch and RF D/A 

Converters, High Speed Early Sampling and Digitizing, and Design Techniques for Single Chip 

Mixed Signal Circuits and Systems. Circuit implementations include floating-point ADC, 

interpolation DAC, direct digital RF quadrature modulator, charge-sampling ADC and FIR filter, 

interpolation multiphase clock generators, and silent digital logic circuits etc. Achievements in 

successful chip designs and tests are summarized below. 

A Floating-Point ADC 

A floating-point ADC is constructed for achieving a wide dynamic range without demanding a 

high resolution so the dynamic range and resolution can be independently designed. The test chip 

ZDV LPSOHPHQWHG LQ P &026, achieving a 12-bit dynamic range and an 8-bit resolution at a 

sampling rate of 30MS/s. It works with a 3.3V power supply and consumes 25mW.


A Charge sampler with embedded filter function 

Charge sampling is proposed to replace the conventional voltage sampling. By introducing a 

window function, the sampler is simultaneously a low phase anti-alias filter. The chip was 

LPSOHPHQWHG LQ P &026 DFKLHYLQJ D VDPSOLQJ UDWH RI 06 V :LWK D 0+] EDQGZLGWK 

the suppression at 15MHz is more than 60 dB. It works with a 3.3V power supply and consumes 

35mW. 

An 8-bit 100-MHz Low Glitch Interpolation DAC 

The linear interpolation function, realized by a time-interleaved structure, reduces both image 

components and the glitch. The 8-bit 100-MHz DAC using a 16-point linear interpolation was 

designed and fabricated in 0.35µm standard CMOS. The chip was tested successfully at VDD = 

3.3V with a power consumption of 54.5mW. The SFDR is 60.94dB with an input at 3.79MHz, and 

the attenuation of its image component is 59.66dB. The two-tone (2.37 and 3.79MHz) SFDR is 

61.69dB. DNL < ±0.32 LSB, and INL < 0.12 LSB. The results show a good agreement with the 

theoretical analysis. 

A Direct RF-Modulator with a 10-bit 100-MHz Low Glitch Interpolation DAC 

In this chip, the output current of a 10-bit 100-MHz linear interpolation DAC is directly used for 

modulating an RF power amplifier without analog filters. The chip was fabricated in 0.35µm 

standard CMOS and tested successfully. The SFDR is 56.1dB with an input at 7.37MHz, and the 

attenuation of its image component is 45.35dB. The three-tone (7.39, 8.39 and 9.39MHz ) SFDR is 

58dB, and the attenuation of their image components has reached the theoretical limit. For the RF 

amplitude modulator, with a carrier frequency at 1.2GHz and a modulation bandwidth of 5.2MHz, 

the measured maximum distortion and image component are -55dB and -49dB respectively. The 

chip consumes 430mW with a 3.3V power supply. 

A Non-Feedback Multi-phase Clock Generator 

The technique can produce multiple clocks with accurate and arbitrarily small skews (equal or 

unequal), which is very essential for many applications. It does not rely on PLL, DLL or any 

IHHGEDFN VROXWLRQV 7KH WHVW FKLS IDEULFDWHG LQ P &026 SURGXFHV FORFNV HYHQO\ GLVWULEXWHG 

in one period of the input clock in a frequency range of 0.5-1.5GHz. 

Other finished circuits under fabrication or testing: 

• A 10+5 bit floating point ADC. 

• A direct digital RF quardrature modulator. 

• A 500MHz 8-bit CMOS sampler. 

• A 100 MS/s low power 2-step A/D converter using current-mode comparators. 

• A single-stage direct interpolation multiphase clock generator with phase error average. 

• A 16-bit parallel adder using a new silent digital technique. 

Papers and patents: 

• Based on these results and the theoretical work, scientific papers were produced, including 2 

refereed journal paper and 20 refereed international conference papers, see Appendix 2. 

• To date, three patents (assigned or pending) have been transferred to the industrial partners. 


Ultra Low Power DSP for Pacemakers


The next generation of pacemakers will require more sophisticated classification algorithms to be 

implemented to detect disturbances in the heartbeats. Since pacemakers run on the same battery 

for very long time periods, preferably several years, circuits with extremely low power 

consumption have to be designed. The initial phase of this project has been focused on algorithm 

exploration. The idea of using an artificial neural network (ANN) for a non-linear adaptive filter to 

pace the heart in a more "intelligent" way was investigated. The ANN has good performance but 

suffers from a high complexity making it unsuitable for pacemaker implementation. Therefore, 

two additional structures have been developed and investigated. Following the algorithmic 

investigations the project is now ready for a hardware implementation phase to be conducted with 

special emphasis on ultra low power solutions. 

Controller Synthesis and Processor Communication 

An existing tool has been modified to fit the present designing environment, i.e. controller 

structures are generated for implementation in an environment based on VHDL. This makes it 

possible to target designs for both FPGA and full-custom implementation from the same 

description. A rather complex test design, a 2-dimensional image convolver, has been 

implemented and evaluated on an FPGA platform. Specific topics that have been pursued is how 

different memory structures affect the over all performance. Two different memory structures have 

been implemented, using two or three levels of image memories respectively. 

Implementation of Iterative Decoders 

During the period a complete UMTS turbo decoder has been designed that fully complies with the 

3GPP-TS-25.212 channel coding specification. Several innovative architectural optimizations have 

been developed. The core critical path has been shorted with up to 20% compared with today’s 

state of the art designs. For the crucial interleaver an architecture has been developed that 

compared with today’s state of the art designs (ISSCC’2002) has an estimated 40% of the power 

consumption at 65% of the area with a 40% increase of speed. The turbo decoder has been 

designed with a newly developed fast handshaking protocol that operates at the register level. This 

protocol provides unified interfaces, flexibility, speed, simplified controller design and makes the 

submodules autonomous. It has the added advantage that it can micro manage power down in 

individual pipeline stages and be used with advanced clock gating techniques that essentially 

doubles the buffering capacity of pipelines. 

Hardware/Software Co-Optimization for Echo Cancellation 

A delay less acoustic echo cancellation scheme has been chosen to explore the properties of 

hardware/algorithm co-design. The complete processor has been fabricated in a 0.35µm standard 

CMOS process and has an area of 29mm 2 . The design consists of less than 50000 cells, 250kbits of 

RAM and 30kbits of ROM. The chip has been targeted for a clock frequency of 50MHz, while 

16MHz is enough to fulfill real-time performance. The excess frequency can be traded for lower 

supply voltage and reduced power consumption. The design has been successfully tested for 

functionality, and performance measurements have been performed. At the target frequency of 

16MHz, the chip consumes 55mW. 

An OFDM Synchronizer: Algorithm to Silicon 

The synchronization algorithms have been implemented and simulated in a C program. This C 

program has been used to test various modifications and make appropriate simplifications to the 

algorithm. The C program has been gradually refined to model all the details of a hardware 

implementation, which includes fix-point arithmetic, memory accesses etc. The C program is also 

used together with a system model in Matlab to perform system simulations, which is used to see 

what impact algorithmic tradeoffs had on the system performance. The C program is compiled to


the fastest available general purpose DSP from Texas Instruments. Simulations verify that it is 

impossible to achieve desired performance with a standard DSP implementation. With the help of 

the C program, the hardware architecture is described in the hardware modeling language VHDL. 

The VHDL model is verified by comparing simulation results with the C program. The VHDL 

code is synthesized to a cell library and a final layout has been obtained with the help of a place 

and route tool. The finished chip is fabricated and tested. The VHDL code has also been 

synthesized to an FPGA, which is used to compare performance between FPGA and ASIC 

implementations. A licentiate degree was achieved in May 2000. 

Flexible Coding/Decoding for PAN 

A flexible convolutional encoder has been implemented on an FPGA. However, the VHDL 

description can easily be used for an implementation in an ASIC. Encoder memory m and code 

rate b/c are variable and can be configured freely in the specified range of m=2..10 and b=1..15, 

c=2..16, b


0.5µm CMOS process and verified for functionality, speed, and power consumption. Running at 

40 MHz, a multiplier with input word lengths of 16+16 times 10+10 bits consumes 54% less 

power compared to an distributed arithmetic array multiplier fabricated under equal conditions. A 

divider architecture has been designed, fabricated and successfully tested. The divider operates on 

16 bit integer inputs and generates a 16 bit quotient in four clock cycles. However, the structure 

can be configured for a wide range of parameters during synthesis. The circuit was fabricated with 

standard cells in a 0.35µm three metal layer CMOS process. The divider is a part of the echo 

cancellation implementation. 

Distributed asynchronous custom DSP-systems 

The activity of the project is in particular focused on low power, low voltage, and low digital clock 

interference. Clock generators with and without phase lock technique are investigated and 

prototype chips are implemented. A focus for the clock generators is implementation with only 

digital cell-library components and without off-chip components. The results also include a novel 

strategy for handling dual supply voltage in large digital designs. This approach is particularly 

suitable for digital hardware with varying requirement on supply voltage level, such as any course 

grain reconfigurable structure. A silicon implementation testing the dual supply voltage approach 

is also made. A Ph.D. graduation is expected during the fall year 2003. 


HW accelerators for Two-dimensional signal processing 

A new scaling method for FFTs has been developed which requires less memory than block 

scaling, since it does scaling on the fly. A comparison to convergent block floating point shows a 

memory reduction of approximately 25% for a 2048 points FFT.A chip has been designed in a 

0.35µm CMOS process and was sent for fabrication, August 2002. The fabricate chip has a core 

size of 7.5mm 2 , and at a supply voltage of 1.8V it consumes 234mW at 50MHz. 


Link budget and antennas 

• A software package for simulation of the radio channel between an implant and a receiver 

outside the body has been developed. 

• Very accurate simulations of the radio channel have been done. 

• New types of patch antennas have been designed and simulated. 

• A system for measuring noise at hospitals has been developed. The measurements are 

performed during February and March. 

The detailed descriptions, milestones and results of all work packages can be found in 

Appendix 1.


3. Academic outputs, education and other activities 

3.1 Academic outputs 

The list of scientific papers can be found in Appendix 2. The statistics of publications 2000-2002 

in different categories is given in Table 2 and Table 3. 

Table 2: Publications in refereed scientific journals 

Names of Journals 


publications 

IEEE Journal of Solid-State Circuits 7 

IEEE Transaction on Circuit and Systems 3 

IEEE Transaction on Vehicular Technology 1 

Analog Integrated Circuits and Signal Processing: an International Journal 4 

Electronics Letters 3 

Total number of publications in refereed scientific journals 2000-2002 18 (6 in 2002) 

Table 3: Publications in refereed proceedings of international conferences 

Names of conferences 


publications 

ISSCC (International Solid-State Circuits Conference) 3 

ESSCIRC (European Solid-State Circuits Conference) 8 

VLSI Symposium 3 

CICC (Custom Integrated Circuits Conference) 3 

ISCAS (International Symposium on Circuits and Systems) 20 

ICECS (International Conference on Electronic, Circuits and Systems) 1 

IEEE Vehicular Technology Conference 3 

ECCTD (European Conference on Circuit Theory and Design) 2 

MWSCAS (Midwest Symposium on Circuits and Systems) 3 

NORCHIP (NORCHIP Conference) 7 

MSE (Microelectronic Systems Education conference) 1 

AP-ASIC (Asia-Pacific Conference on ASIC) 2 

ICMMT (International Conference on Microwave and Millimeter Wave 

1 

Technology) 

ISIT (International Conference on Information Theory) 1 

ASICON (International Conference on ASIC) 1 

ISSS (International Symposium on System Synthesis) 1 

EWME (European Workshop on Microelectronics Education). 1 

IMS (International Microwave Symposium) 1 

RAWCOM 1 

NSM (Nordic Semiconductor Meeting) 1 

Nordic Signal Processing Symposium 1 

IEEE Conference on Engineering in Medicine and Biology 1 

ICONIP ( International Conference on Neural Information) 1 

Word Wireless Congress, 3Gwireless 2003 1 

Total number of publications on international conferences 2000-2002 68 (25 in 2002) 

In addition, there have been 12 national conference papers (6 in 2002), see Appendix 2.


Book & Book chapters 

1. Joachim Neves Rodrigues, A.Th. Schwarzbacher and J. B. Foley, “Fast Dynamic Power 

Comparison at the VHDL Netlist Level,” In Problems in Modern Applied Mathematics, 

Edited by Nikos Mastorakis, 2000. 

Patent and Patent Application 

1. Jiren Yuan, “Floating-Point Analog-to-Digital Converter,” No. 9802787-3, granted February 

2000. 

2. Shousheng He and Mats Torkelson, “Real-Time Pipeline Fast FourierTransform Processors,” 

No. US6098088, granted August 2000. 

3. Jiren Yuan and Yijun Zhou, “A Direct Digital Amplitude Modulator,” No. 0004031-1, filed 

November 2000. 

4. Anders Karlsson, “An optimized VHF/UHF telemetry antenna suitable for miniaturized 

implantable devices”, Reference No. A00 E 2092, August 24, 2001. 

5. Magnus Åström, Salvadol Olmos and Leif Sörnmo, “Cardiac Event Detector”, Swedish 

"Patentverket" Reference No. 0103562-5, filed October 23, 2001. 

6. Henrik Sjöland and Pietro Andreani, “Enhanced Low-Noise Amplifier”, P.C.T. Patent 

Application No. PCT/EP02/03889. 

Ph.D. theses 

1. Bo Shi, “Linear Transmitter Design Using Nonlinear Analog Circuits”, Department of 

Electroscience, ISSN 1402-8662, No. 25, August 2001. 

2. Martin Lantz, “Systematic Design of Linear Feedback Amplifiers”, Department of 

Electroscience, ISSN 1402-8662, No. 29, November 2002. 

3. Anders Berkeman, “ASIC Implementation of a Delayless Acoustic Echo Canceller”, 

Department of Electroscience, ISSN 1402-8662, No. 32, December 2002. 

Licentiate theses 

1. Stefan Johansson, “ASIC Implementation of an OFDM Synchronization Algorithm,” 

Department of Applied Electronics, Lund University, Sweden, No. 15, ISSN 1402-8662, May 

2000. 

2. Anders J. Johansson, “Theory and Use of Chaotic Oscillators in Electronic Communications,” 

Department of Applied Electronics, Lund University, Sweden, No. 20, ISSN 1402-8662, 

September 2000. 

3. Torbjörn Sandström, “CMOS Receiver Design”, Department of Electroscience, ISSN 1402- 

8662, April 2001. 

4. Anna-Karin Stenman, “Some Design Aspects on RF CMOS LNAs and Mixers”, Department 

of Electroscience, ISSN 1402-8662, December 2001. 

5. Weiyun Shan, “Study of Imperfection in Predistortion Linearizer Systems”, Department of 

Electroscience, ISSN 1402-8662, August 2002. 

In addition, 46 Masters' theses were produced during 2000-2002 (17 in 2002), see Appendix 2. 

3.2 Education and training 

Industrial courses 

• RF IC Design 

• Analog IC Design


• Digital IC-Design 

• AD/DA Design 

• Low Switching Noise, Substrate Coupling and Crosstalk 

Graduate courses 

• “Integrated Radio Electronics”, Henrik Sjöland. 

• “Frequency Synthesis”, Henrik Sjöland. 

• “Analog IC Design”, Pietro Andreani. 

• “System-on-Chip - Low Switching Noise Design”, Jiren Yuan. 

• “Integrated A/D and D/A converters”, Jiren Yuan. 

• “Computer Arithmetic Circuits”, Peter Nilsson. 

• “DSP Design”, Viktor Öwall. 

• “Low Power Design”, Viktor Öwall. 

Undergraduate courses 

Name of the course Number of students 

(2002) 

ETI031 Radio (Göran Jönsson) 69 

ETI032 Radio Electronics (Göran Jönsson) 41 

ETI041 Radio Project (Göran Jönsson) 9 

ETI051 Radio Systems (Ove Edfors) 21 

ETI063 Integrated Circuit Design (Henrik Sjöland) 30 

ETI130 Digital IC-design (Peter Nilsson) 64 

ETI140 Digital IC Verification (Peter Nilsson) 2 

ETI160 Biomedical Signal Processing (Leif Sörnmo) 9 

ETI170 Integrated Radio Electronics (Henrik Sjöland) 21 

ETI180 DSP Design (Viktor Öwall) 27 

ETI200 System-on-Chip Design (Jiren Yuan) 27 

ETI210 IC-project and Verification (Henrik Sjöland) 27 

ETI220 Integrated A/D and D/A converters (Jiren Yuan) 26 

ETI250 Electronics: Possibilities and Limitations (Viktor Öwall) 15 

ETI260 Computational Electromagnetics (Mats Gustafsson) 18 

ETI280 Intellectual Property Right Management (Peter Nilsson) 24 

ETI290 Advanced Analogue Design (Johan Piper) 47 

3.3 Workshops and meetings 

A number of workshops, seminars, courses and lectures were organized in year 2001, see below. 

Workshops 

• Workshop on “Hardware design in C++”, Pontus Åström, Lund, February 22, 2000. 

• CCCD Workshop 2000, March 9-10, 2000, Lund, about 100 participants from universities and 

companies attended the workshop. The workshop includes invited talks (Dr. Sven Mattisson, 

Ericsson Mobile Communication; Prof. Christian Piguet, CSEM; Prof. Lars-Erik Wernersson; 

and Prof. Kjell Lindström, LTH) 

• The Hermes OFDM workshop, Lund, November 21, 2000. 

• AD/DA Workshop 2001, Linköping, Sweden, January 16, 2001, 3 contributions from the 

Mixed Signal Circuit group of CCCD.


• The Swedish System-on-Chip Conference 2001 (SSoCC’01) in Arild, March 20-21, 2001, coorganized 

by CCCD, which is the first conference in System-on-Chip in Sweden. There were 

20 presentations and more than 70 participants. 

• CCCD Workshop 2001, August 23-24, 2001, Lund. More than 100 participants from 

universities and companies attended the workshop. The workshop includes invited talks (Prof. 

Jan Rabaey of UCB, USA; Prof. Qiuting Huang of SFIT, Switzerland; and Dr. Christian Björk 

of Ericsson Mobile Platforms), oral presentations, posters, and demonstrations. 

• Socware EDU Workshop, November 7, 2001, Kista, Sweden, co-organized by CCCD. 

• GigaHertz 2001 Symposium, November 26-27, 2001, Lund, co-organized by CCCD, with 

more than 90 participants. The symposium is in the field of components and circuit 

technologies for microwave and RF applications. 

• Swedish System-on-Chip Conference 2002 (SSoCC'02), March 18-19, 2002, Falkenberg, 

Sweden, co-organized by CCCD. 

• CCCD Workshop 2002, October 24-25, 2002, in Lund, about 100 participants from 

universities and companies attended the workshop. The workshop includes invited talks (Prof. 

Rinaldo Castello, University of Pavia; Mr. Tord Wingren, Ericsson Mobile Platforms; Prof. 

Rudy Lauwereins, IMEC, Leuven, Belgium; and Mr. Anders Olsson, AXIS Communications), 

oral presentations, posters, and demonstrations. 

• Jiren Yuan and Peter Nilsson contributed presentations to Socware Day Workshop, November 

13, 2002, Kista, Sweden. 

Major meetings 

• Peter Nilsson, LU, “SoC Research & Education,” for Post och Telestyrelsen, Lund, January 

28, 2000 

• Peter Nilsson, LU, “Wireless Access Systems: ASIC activities within the Intelect Program,” 

Kista, April 11, 2000 

• Viktor Öwall, presentations of CCCD at meeting with Texas Instruments, Lund, May 10, 2000 

• Peter Nilsson, LU, “SoC Research & Education,” for Riksdagens Näringsutskott, Lund, June 

29, 2000 

• Viktor Öwall and Peter Nilsson, LU, Presentation of Digital ASIC for ECS, Lund, October 27, 

2000. 

• Jiren Yuan, “CCCD - a research center heading for future wireless systems on chip,” 

presentation at meeting with VIA Technology, Lund, October 18, 2000 

• Jiren Yuan, LU, “Research in Circuit Design at LTH,” Socware meeting, Norrköping, October 

24, 2000 

• Jiren Yuan, Peter Nilsson and Pietro Andreani, presentations about CCCD at the meeting with 

Kyocera Corporation, Lund, January 29, 2001 

• Jiren Yuan, Peter Nilsson, Viktor Öwall and Pietro Andreani, presentations about CCCD at the 

meeting with Sony Corporation, Lund, February 9, 2001 

• The 2 nd CCCD Advisory meeting in conjunction with CCCD Workshop 2001, Lund, August 

2001. Advisors of CCCD, Prof. Jan Rabaey, Prof. Ivo Bolsens and Prof. Ernst Bonek, attended 

the meeting. 

• Meeting with Sony Corporation, February 9, 2001, Lund. Jiren Yuan, Peter Nilsson, Viktor 

Öwall and Pietro Andreani presented CCCD and its research. 

• Meeting with Semiconductor Technology Research Center of Japan, September 21, 2001, 

Lund. Clas Agnvall presented the department, and Jiren Yuan, Viktor Öwall and Pietro 

Andreani presented CCCD and the researches. 

• The 2 nd CCCD Advisory meeting in conjunction with CCCD Workshop 2001, Lund, August 

2001. Advisors of CCCD, Prof. Jan Rabaey, Prof. Ivo Bolsens and Prof. Ernst Bonek attended 

the meeting.


• Strategy Meeting of CCCD, February 19, 2002, Lund, attended by Prof. John B Anderson, Dr. 

Christian Bergljung, Prof. Ove Edfors, Dr. Johan M Karlsson, Dr. Peter Karlsson, Dr. Bengt- 

Arne Molin, Dr.. Mats Torkelson, Dr. Sven Mattisson (separate meeting), and CCCD senior 

researchers. 

• Meeting with International Evaluation Group: Prof. Marc Engels, IMEC, LoraNet N.V., 

Belgium; Prof. Veikko Porra, Helsinki University of Technology, Finland; Prof. John S. 

Baras, University of Maryland, USA; and Prof. Per Stenius, Helsinki University of 

Technology, Finland; Lund, October 3-4, 2002. 

• The 3 rd CCCD Advisory meeting in conjunction with CCCD Workshop 2002, Lund, October 

25, 2002, attended by Prof. Jan Rabaey, Prof. Ernst Bonek attended and CCCD researchers.. 

• Meeting with Dr. Josef Fenk, Infineon Technologies Wireless Solutions, Munich, Germany, 

and Dr. Gunnar Björklund, Infineon Technologies Wireless Solutions Sweden AB, Lund, 

November 4, 2002. 

3.4 Other activities 

Opponents 

Henrik Sjöland was the opponent on the licentiate thesis "Design Aspects of Low-Noise 

Amplifiers in Low-IF Receivers for Wireless Applications" by Adiseno, KTH, May 2001. 

Editors 

Viktor Öwall was the Associate Editor of IEEE Transactions on Circuits and Systems II: Analog 

and Digital Signal Processing. 

Committee members 

Peter Nilsson is a member of ISCAS-2002/03 VLSI Systems Track Program Committee. Peter 

Nilsson was a program committee member in the 2003 Microelectronic Systems Education 

conference (MSE'03). He was a member of doctoral examination committee for Bengt Oleman, 

“Asynchronous and Mixed Synchronous/Asynchronous Design Technique for Low Power”, KTH, 

June 5, 2000. He was a member of doctoral examination committee for Imed Ben Dhaou, ”Low 

Power Design Techniques for Deep Submicron Technology with Application to Wireless 

Transceiver Design”, KTH August 27, 2002 

Jiren Yuan is a member of the Management Committee of NORCHIP conference 2000-2002 and a 

member of the Management Committee of GigaHertz conference 2001. 

Viktor Öwall is a member of the Technical Program Committee of The 20 th International 

Conference on Computer Design, 2002. He was a member of doctoral examination committee for 

Yonghong Gao, “Architecture and Implementation of Comf Filters and Digital Modulators for 

Oversampling A/D and D/A Converters”, KTH 2001, and a member of doctoral examination 

committee for Mikael Karlsson Rudberg, “DSP Algorithms and Architectures for 

Telecommunication”, LiTH 2001. 

Reviewers 

Peter Nilsson was a reviewer for Bengt Oelman to be a lecturer at Mitthögskolan, April 2001, and 

a reviewer of International Symposium on Circuits and Systems (ISCAS) 2002, Design 

Automation Conference, 1999, 2000, 2001, Eusipco, 2000, Norsig, 2000, MSE 2003. He was the 

Reference group member for the Nano Science Master Education in Lund, 2002. 

Thomas Olsson was a reviewer of International Journal of Electronics 2002.


Jiren Yuan is a reviewer of EU project MADBRIC, a reviewer of EU project BANDIT, a reviewer 

of IEEE Solid-State Circuits, a reviewer of IEEE Transactions on Circuits and Systems II, and a 

reviewer of IEE Electronics Letters. He was a reviewer for the professorship of Turku University 

(Finland), a reviewer for the lectureship of Royal Institute of Technology and a reviewer for the 

professorship of Linköping University, during 2000-2002. 

Viktor Öwall was a reviewer for the Norweigian Research Council (2000 and 2001), a reviewer 

for the Dutch Technology Foundation STW, a review for IEEE Transaction Circuits and Systems 

II, a review for IEE Transaction on VLSI Systems, and a review for ISCAS conference. 

Most students in Digital ASIC group were the reviewers of ISCAS 2003.


4. Partners and personal 

4.1 Academic groups 

Research groups (at the Department of Electroscience, Lund University) 

• Circuit Design 

- Analog/RF Circuit Design 

- Mixed Signal Circuit Design 

- Digital ASIC Design 

• Radio Communications 

• Signal Processing 

• Electromagnetic Theory 

University partner 

• Center for Wireless Communications (CWC), now Institute for Infocomm Research, National 

University of Singapore 

4.2 Industrial partners 

Industrial partners 

• AXIS Communications AB 

• Cadence Design Systems AB 

• Ericsson Microelectronics AB (now Infineon Technologies Wireless Solutions Sweden AB) 

• Ericsson Mobile Platforms AB 

• Ericsson Radio Systems AB (now Ericsson AB) 

• Pharma Vision Systems AB 

• St. Jude Medical AB 

• SwitchCore AB 

• Telia Research AB 

4.3 People engaged in CCCD 

During stage 2, people engaged in CCCD are listed below: 

Board members 

Peter Olanders, Ericsson AB, Chairman of the Board 

Clas Agnvall, Lund University, Vice chairman of the Board 

Mats Arturson, St. Jude Medical AB 

Erik Björk, Cadence Design Systems AB 

Gunnar Björklund, Ericsson Microelectronics AB (now Infineon Technologies Wireless Solutions 

Sweden AB) 

Björn Ekelund, Ericsson Mobile Platforms AB 

Kerstin Lindh, AXIS Communications AB 

Charlotte Mattisson, Pharma Vision Systems AB 

Kenny Ranerup, SwitchCore 

Johan Wickman, Telia Research AB


Technical Advisory Board 

Professor Jan Rabaey, University of California at Berkeley, USA, 

Professor Ivo Bolsens, XILINX, San Jose, USA, and 

Professor Ernst Bonek, Technical University of Wien, Austria. 

Management and Administration 

Jiren Yuan, Director (30%, 9805-) 

Stina Ahlenius, Senior Administrative Officer (40%, 9806-) 

Pia Bruhn, Secretary (50%, 0005-) 

University Professors 

Department of Electroscience 

Jiren Yuan, Professor chairing Circuit Design (40%, 9801-) 

Pietro Andreani, Associate Professor (70%, 9906-0111) 

Ove Edfors, Professor in Radio Communications (10%, 0001-) 

Mats Gustafsson, Associate Professor in Electromagnetic Theory (10%, 0101-) 

Anders Karlsson, Professor in Electromagnetic Theory (10%, 0101-) 

Gerhard Kristiansson, Professor in Electromagnetic Theory (10%, 0101-) 

Peter Nilsson, Associate Professor (50% during 9801-9912, 30% form January 2000) 

Henrik Sjöland, Associate Professor (50%) 

Leif Sörnmo, Professor in Signal Processing (15%, 0001-) 

Viktor Öwall, Associate Professor (50% during 9801-9912, 30% form January 2000) 

Lars Sundström, Associate Professor (65%, 9801-0007) 

Department of Computer Science 

Krzysztof Kuchcinski, Professor in Embedded System Design (0201-) 

Department of Information Technology 

John B. Anderson, Professor in Information Technology (0201-) 

Industrial Adjunct Professors 

Sven Mattisson Ericsson Mobile Platforms (20%, 9801-) 

Mats Torkelson Ericsson Radio Systems (20%, 9801-) 

Lars Sundström, Ericsson Mobile Platforms (20%, 0008-) 

Anders Derneryd, Ericsson Microwave Systems (0101-) 

. 

Industrial researchers 

Shousheng He, Ericsson Mobile Platforms (20%) 

Thomas Mattsson, Ericsson Mobile Platforms (20%) 

Technicians 

Erik Jonsson (50%, 9801-) 

Stefan Molund (25%, 9901-) 

Göran Jönsson (10%, 0001-) 

Martin Nilsson (50%, 0107-) 

Bengt Bengtsson (75%, 0109-) 

Ph.D. students financed and supervised through CCCD


Anders Johansson (80%, - 0104, and 50%, 0105-) 

Bo Shi (100%, 9709-0109) 

Roland Strandberg (80%, 9808-) 

Laurent Durkalec (80%, 9901-0110) 

Johan Piper (80%, 9902-) 

Joachim Rodrigues (80%, 9909-) 

Yijun Zhou (100%, 9905-) 

Gang Xu (80%, 9910-) 

Pontus Åström, (20% from CCCD and 60% from SSF’s program INTELECT) 

Stefan Johansson (20% from CCCD and 60% from SSF during 0001-0005) 

Anders Berkeman (80% from July 2000, and by NUTEK's Telecom program during 9708-0006) 

Niklas Troedsson (80%, 0008-) 

Konstantinos Theodoropoulos (80%, 0009-) 

Lixin Yang (100%, 0011-) 

Niklas Troedsson (80%, 0101-) 

Pieternella Cijvat (80%, 0102-) 

Magnus Åström (10%, 0105-) 

Fredrik Kristensen (80%, 0109-) 

Thomas Lenart (80%, 0112-) 

Hugo Hedberg (80%, 0203-) 

Ph.D. students supervised through CCCD 

Anna-Karin Stenman (9705-0205), SSF’s program INTELECT 

Martin Lantz (9710-0211), SSF's program PCC 

Torbjörn Sandström (9801-0010), SSF’s program INTELECT 

Thomas Olsson (PCC, 9802-), SSF's program PCC 

Eric Westesson (9806-0110), VINNOVA’s program INWITE 

Karl Thoren (9903-), SSF's program PCC 

Fredric Edman (80%, 9905-), SSF’s program INTELECT 

Weiyun Shan (100%, 9910-0208), VINNOVA’s program INWITE 

Hongtu Jiang (0010-), SSF’s program INTELECT 

Fredrik Tillman (0007-), SSF’s program INTELECT 

Lars Aspemyr (0004-), Ericsson Microwave 

Zhan Guo (0104-), SSF’s program INTELECT 

Matthias Kamuf (0110-), Socware-financed 

Henrik Svensson (0203-), Socware-financed 

Martin Andersson (0204-), Socware-financed 

Kittichai Phansathitwong (0208-), Socware-financed


5. Economic accounting 

5.1 Budget-result stage 2 

The total budget for stage 2, i.e. from 2000-01-01 to 2002-12-31, was settled to totally 48 900 kkr 

with 59% in cash and 41% in emolument. As can be seen today the outcome of the result is mostly 

in line with the budget. The company part is 40%, VINNOVA 36% and Lund University 24%. 

The cash part of the contribution has been higher, 61%, than planned due to the new industrial 

partner, St Jude Medical AB, engagement in CCCD and to the contribution of Pharma Vision 

Systems AB in cash instead of emolument. During 2002, SwitchCore AB announced that they had 

no possibilities to pay the fees for Q3 and Q4. 

Incomes: 

Budget Results 

Cash Emolument Sum Cash Emolument 

Company LU Company LU Sum 

VINNOVA 18,000 18,000 18,000 18,000 

AXIS Communications 

AB 720 1,080 1,800 720 990 1,710 

Cadence AB 3,000 3,000 3,000 3,000 

Ericsson Microelectronics 

AB 1,050 450 1,500 1,050 290 1,340 

Ericsson Mobile 

Platforms AB 3,000 1,500 4,500 3,000 1,745 4,745 

Ericsson AB 3,000 600 3,600 3,000 965 3,965 

Pharma Vision 

Systems AB 600 600 400 35 435 

St Jude Medical 

AB 0 1,400 50 1,450 

SwitchCore AB 1,800 1,800 1,500 20 1,520 

Telia Research 

AB 1,500 600 2,100 1,500 600 2,100 

Lund University 12,000 12,000 12,171 12,171 

29,070 7,830 12,000 48,900 30,570 7,695 12,171 50,436 

Costs: 

Salary 13690 4650 6285 24625 14,718 4,378 7,519 26,615 

Travel 2115 465 2580 1,949 479 2,428 

Equipment 3730 1800 5530 3,079 162 440 3,681 

Other costs 900 3180 4080 1,514 3,155 207 4,876 

OH-costs 8635 3450 12085 9,035 3,526 12,560 

29070 7830 12000 48900 30,294 7,695 12,171 50,160 

5.2 Allocation of resources per sub-area 

During this stage the projects in the Operating Plan have been revised. The original projects 

become work packages with some of them being removed or renamed due to personnel changes,


and some new work packages are introduced. Due to these changes the allocation below is 

presented in subareas. 

The total number of full-time equivalent persons engaged in the center management was 1.15 

divided in 30% director, 35 administrative director and 50% secretary. 

Emolument 

companies Emolument LU Total 

Cash Personnel Other Personnel Other 

Subarea CCCD costs costs costs costs kSEK % 

Mixed Signals Design 5,977 165 700 5,135 259 12,236 24 

ASIC/DSP Design 8,459 2,783 1,099 1,356 223 13,920 28 

Analog and RF Design 9,477 1,393 1,435 4,355 376 17,036 34 

Digital Holographic 3,541 35 83 213 41 3,913 8 

Center Management 2,838 211 3,049 6 

30,292 4,376 3,317 11,270 899 50,154 100


Appendix 1: Work packages, milestones and results 

Project 1: Monolithic Oscillators and Filters 

WP 1-1: Monolithic Oscillators and Filters 

Researcher: Dr. Pietro Andreani, LU, CCCD-financed, moved to DTU in December 2001 

Description: High frequency oscillators and RF filters are two of the few remaining building 

blocks that are still partially or completely implemented off-chip. The objective is to develop 

design methods for fully integrated oscillators and filters. This is seen as a critical challenge that is 

associated with implementation of reactive circuit elements whose quality has a large influence on 

the performance of these building blocks. 

Results: A new technique for low phase noise monolithic CMOS VCO’s was invented by Pietro 

Andreani and Henrik Sjöland. By adding an off-chip inductor in series, the low-frequency noise of 

the tail current source can be prevented from being up-converted into phase-noise. The technique 

is most effective when combined with the on-chip noise filtering technique invented by Henrik 

Sjöland together with Emad Hegazi and Asad Abidi, which eliminates the effect of high frequency 

tail current noise. 

A new topology for high-performance quadrature oscillators was discovered by Pietro Andreani. 

The conventional quadrature oscillator is made from two coupled differential oscillators. The 

coupling is realized by transistors controlled by one oscillator being parallel to and injecting 

current into the other, and vice versa. The new idea is to use series connected coupling transistors. 

The result is a dramatic improvement in both power consumption and phase noise. 

This work package has resulted in several recent publications in well recognized conferences and a 

journal paper. 

Dr. Pietro Andreani has become a full professor at DTU in the end of 2001, and there is therefore 

currently no activity in this WP. 

WP 1-2: Adaptive Front-End for GSM 

Student: M.Sc. Laurent Durkalec, CCCD-financed 

Supervisor: Dr. Lars Sundström, Ericsson Mobile Platforms AB, CCCD-financed 

Description: The objective is to invent new circuit techniques for the radio front-end that should 

be adaptive in order to provide just enough performance during operation for continuous 

minimization of power consumption. The GSM system and its derivatives should by used as a 

platform for evaluating new concepts. The process technology is provided by Ericsson 

Microelectronics. 

Results: PhD student Laurent Durkalec has designed a low noise RF bandpass amplifier (center 

frequency 950MHz). The amplifier is using frequency selective and positive feedback to enhance 

and tune the Q-factor. The circuit has been simulated in a BiCMOS process from Ericsson. A 

paper has been presented at Norchip 2001 in Kista. 

Milestone:


1 Design a 950MHz Q-enhanced LNA, send to fabrication. (2002) Done 

2 Measure the LNA. (2002) Waiting for the chip 

WP 1-3: Low-Noise Amplifiers and Mixers 

Students: M.Sc. Anna-Karin Stenman, SSF-financed 

M.Sc. Torbjörn Sandström, SSF-financed 

Supervisor: Dr. Lars Sundström, Ericsson Mobile Platforms AB, CCCD-financed. 

Description: Following the one-chip radio theme of the Mobile Radio Consortium, the aim of this 

work package is to investigate front-end designs in CMOS for cellular wideband systems. The 

objective is to develop circuit solutions for low supply voltage and adaptive power consumption so 

that just enough performance is obtained from the receiver. 

Results: Anna-Karin Stenman presented her Licentiate Thesis, which mainly dealt with matching 

between passive CMOS mixers in image-reject receivers, and the effect of gate-drain capacitance 

on the input impedance and noise figure of CMOS Low Noise Amplifiers. Torbjörn Sandström 

also presented his Licentiate Thesis, with the title CMOS Receiver Design. The two students have 

now left the university and moved to industry. 

A new technique for optimizing the noise performance of a CMOS LNA has been invented by 

Henrik Sjöland and Pietro Andreani. The idea is to add an additional capacitance between gate and 

source of the input device in an inductively source degenerated LNA. The result is a suppression 

of the influence of the gate-induced noise, which otherwise typically dominates. This work has 

resulted in a journal paper and a patent application. 

WP 1-4: Low-Voltage Oscillators with Quadrature Generation 

Student: M.Sc. Niklas Troedsson, CCCD-financed 

Supervisor: Dr. Henrik Sjöland, LU, CCCD-financed 

Description: Receiver architectures suitable for complete integration, such as direct conversion 

and low-IF, requires local oscillator signals with quadrature phases. One way to generate such 

signals is through poly-phase RC networks, which, however, attenuate the signal. This technique 

therefore requires power consuming buffer amplifiers. Another way is through the use of 

quadrature oscillators, which directly generates the four phases. It has just been discovered how 

such an oscillator can be built with low phase-noise, and not much is yet investigated on this topic. 

Due to the ever decreasing channel lengths, and thereby supply voltage, it is also important to 

investigate the limits in supply voltage for oscillators and quadrature generation. When it comes to 

oscillators, the implementation of the frequency tuning component (varactor) is a major challenge, 

and new ways to tune oscillators compatible with low supply voltages must be studied. 

Results: 

A very low voltage differential CMOS oscillator designed by Niklas Troedsson has been 

fabricated at Agere Systems. The oscillator uses an inductor tuned to twice the operating 

frequency instead of an active tail current source, as described by Emad Hegazi, Henrik Sjöland 

and Asad Abidi. The idea was to combine such a topology with an amplitude control adjusting the 

gate bias, to get control of the current consumption and to keep the node voltages within bounds. 

The oscillator works fine, and two conference papers has been presented on various aspects. 

A very low voltage quadrature oscillator has also been sent to fabrication as well as a front-end 

with the quadrature VCO together with colleague Fredrik Tillman. The chips returned in January 

2003, and the measurements have now started.


A new technique for improved switched frequency tuning of differential CMOS circuits was 

discovered by Henrik Sjöland. The idea is to use only one switch device in the differential signal 

path, instead of the usual two. This results in a doubled performance in terms of quality factor, or 

frequency of operation. This has been presented in a journal paper. 

Milestones: 

1 To design a low phase-noise CMOS differential (non-quadrature) VCO 

for a 1V supply. (2001) 

Done 

2 Measurement results for the CMOS differential VCO. (2002) Done 

3 To design a low phase-noise quadrature CMOS VCO for a 1V supply. 


Done 

4 To put together a chip with quadrature VCO, VCO buffers, LNA and 

mixers to make a complete 1V Bluetooth frontend together with Fredrik 

Tillman (WP 1-5). (2002) 

Done 

5 Measurement results for the quadrature VCO and the front-end. (2003) 

WP 1-5: Low-Voltage Low-Noise Amplifiers and Mixers* 

Student: M.Sc. Fredrik Tillman, SSF-financed 


Description: As the CMOS technology develops towards shorter and shorter channel lengths, the 

supply voltage must be reduced. In a few years the maximum supply voltage will be just 1V. To 

anticipate this we already now examine how to design CMOS LNA’s and mixers at 1V. Bluetooth 

is used as a performance target. Novel topologies avoiding stacked transistors must be used to 

achieve maximum performance at such a low supply voltage. 

Results: 

A very low voltage CMOS chip containing a low-noise amplifier and a mixer designed by Fredrik 

Tillman has been fabricated. At a supply voltage of just 1V, the measured performance by far 

exceeds the Bluetooth requirements. This has been presented at a conference. 

A very low voltage CMOS front-end containing LNA, quadrature mixers, quadrature VCO plus 

buffers has been fabricated, and is to be measured. This circuit was designed by Fredrik Tillman 

together with Niklas Troedsson. 

An effort is currently done to analyze the nonlinearity of CMOS passive mixers. These mixers are 

very suitable for low voltage. 

Milestones: 

1 To design a 1V CMOS LNA and mixer for Bluetooth. (2001) Done 

2 Measurement results for the 1V LNA and mixer. (2002) Done 

3 To design an LNA and mixer circuit with improved linearity. (2002) Done 

4 To put together a chip with LNA, mixers, quadrature VCO, and VCO 

buffers to make a complete 1V Bluetooth frontend together with Niklas Done 

Troedsson (WP 1-4). (2002) 

5 Measurements for the improved LNA and mixer chip and the frontend. 

(2003)


WP 1-6: Transmitter architectures for 3 rd generation mobile phones* 

Student: Tech. Lic. Pieternella Cijvat, CCCD-financed 


Description: The 3 rd generation mobile systems put great demands on both linearity and output 

power range. This combined with the need for high efficiency in mobile phones (battery operated) 

creates a major challenge. The aim of the project is to investigate what can be accomplished in 

CMOS technology, which is less suitable for power amplifiers than some more expensive 

technologies like GaAs. 

Results: A fully integrated differential power amplifier was designed and submitted for 

manufacturing in 0.25um CMOS. The total output power is estimated to be 21dBm. The output 

power can be controlled in 2 settings, using parallel stages in the output stage with different 

impedance transformation networks to optimize the efficiency in each setting. The chips returned 

in January 2003, and are now being measured. 

Milestones: 

1 To design and measure a CMOS power amplifier with two 

different output power level settings. The power level is 

controlled by CMOS switches, and the efficiency should be high 

for both settings. (2002) 

2 To design and measure a CMOS power amplifier or whole 

transmitter, with an output power range of about 20dB, and 

sufficient linearity for WCDMA. The efficiency should be high 

across the whole output power range. (2003) 


WP 2-1: Linearization Using Analog Circuit Techniques 

It has been designed 

and fabricated, and is 

under measurement. 

Student: M.Sc. Bo Shi, Faculty-financed 


Description: The objective is to exploit the properties of analog integrated circuit techniques 

more efficiently to be able to accommodate new ideas on linearization of RF power amplifiers. 

Results: 

Bo Shi has designed CMOS circuits for power feedback linearization of RF power amplifiers. The 

idea is that the circuit becomes simpler by regarding only the power of the input signal and the 

output signal. In a feedback system including power detectors, a variable-gain amplifier (VGA) is 

controlled to make the output power proportional to the input. The result is a high operating 

frequency and a low power consumption. In 0.6um CMOS the power consumption is 62mW and a 

power amplifier operating at 850MHz can be linearized. The reduction of out of band power is 

about 10dB. A journal paper was recently published, in addition to the previous publications. 

Bo Shi has also made signal component separator (SCS) circuits for the LINC architecture. In this 

architecture the signal is separated into two constant envelope signals, with are separately 

amplified in two non-linear power amplifiers. After the two amplifiers the signals are added 

together (combined). The work of the SCS is to generate the two constant envelope signals. The 

realization of this requires synthesis of non-linear functions, and to achieve high bandwidth and 

low power this was done analog. Circuits have been designed in BiCMOS as well as pure CMOS.


The measurements have shown a high performance, and the work has resulted in a number of 

recent publications in conferences and journals. 

Bo Shi received his Ph.D. degree in September 2001 and since then has returned back to 

Singapore, so there is currently no activity in this work package. 

WP 2-2: Linearization Using Analog Predistortion 

Student: M.Sc. Eric Westesson, CCCD-financed 


Description: The objective is to develop simple low voltage/low power linearization systems 

based on analog techniques, primarily for use in handsets with moderate requirements on 

transmitter linearity. 

Results: The pre-distortorter chip in 0.35um CMOS worked well, and was presented at a recent 

conference. 

Eric Westesson is currently writing his licentiate thesis. 

WP 2-3: Linearization Using Digital Predistortion 

Student: M.Sc. Weiyun Shan, VINNOVA-financed (through INWITE) 

Superviser: Dr. Lars Sundström, Ericsson Mobile Platforms AB, CCCD-financed 

Description: The objective is to build a test system based on digital techniques to be able to 

emulate and thereby evaluate different predistortion techniques mainly for use in handsets but also 

base-station transmitters. 

Results: Predistortion is a powerful method for linearization of RF power amplifiers; however, the 

linearity performance of a predistortion system is limited by various memory effects. In this 

project, we investigate the effects of filters between the predistorter and the power amplifier. 

Filters are used to provide sufficient rejection of image signals, and can be of low pass type, like 

the reconstruction filters in the baseband predistorter, or bandpass type, like the filters in IF 

predistorters. The effects of these filters are studied by means of both analysis and simulation for 

multi-carrier signals. 

The work has resulted in three recent conference papers, in addition to the Licentiate Thesis. 

Weiyun Shan received her Licentiate degree in August 2002, and then returned back to Singapore, 

so there is currently no activity in this work package. 

WP 2-4: High-Efficiency Linear Transmitter Architectures 

Student: M.Sc. Roland Strandberg, Faculty-financed 

Supervisors: Dr. Lars Sundström, Ericsson Mobile Platforms AB, CCCD-financed 

Dr. Pietro Andreani, LU, CCCD-financed, moved to DTU in December 2001 

Description: 

Many techniques including CALLUM require an efficient recombination of high-power signals. It 

is considered to be the most critical issue for these solutions. A prestudy should be carried out to 

investigate the properties of pairs of power amplifier stages of various classes more or less with 

directly connected outputs. Main issues are linearity properties (assuming ideal LINC signal drive) 

and efficiency. Initially, the purpose of this study is to support further work on the architectures 

but later on the topic might very well constitute a project of its own.


As a first step, simple analysis and simulations should be used to support the implementation of a 

first prototype chip. The choice of architecture for this first chip is open until more knowledge has 

been obtained but if simplicity is given the highest priority the vector-locked loop or the simplest 

CALLUM architecture are the most obvious choices. 

Results: Several blocks have been implemented in a 0.35 um CMOS process at schematic level, 

such as signal component generator, variable gain amplifier, differential to single-ended signal 

converter with common mode feedback LP-filter, PLL for VCO (using phase-frequency detector, 

third order). Apart from the core of the architecture, add on circuitry such as frequency 

synchronization and DC level control is also implemented. New issues have been detected during 

the work, as the architectures limited ability to acquire lock. One solution to this problem is to use 

a VGA to be able to adjust the loop gain during the pull-in process. The work has resulted in one 

conference paper in 2002. 

Milestones: 

1 Implementation on chip of a complete CALLUM2 system or important 

sub-blocks. (2002) 

2 Refinements of the critical signal component generator. Translinear 

techniques will be used to implement the mathematical functions 

needed moving towards CALLUM1. Both CMOS and bipolar circuits 

will be examined. (2003) 


WP 3-1: Wide Dynamic Range A/D Converters 

Done with most 

of the blocks. 

Student: M.Sc. Johan Piper, Faculty-financed 

Supervisors: Prof. Jiren Yuan, LU, CCCD-financed 

Dr. Jan-Erik Eklund, Ericsson Microelectronics AB, CCCD-financed 

Description: The objective is to expand the dynamic range of an A/D converter without imposing 

high resolution and, in the same time, to improve the ratio of signal-to-quantization noise under a 

given resolution. A new type of topology named floating-point A/D converter is to be explored in 

order to achieve the goals. 

Results: The investigation on floating-point A/D converters was continued during 2001. A paper 

titled “Realization of a floating-point A/D converter,” was published at ISCAS'2001 in May 2001. 

The latest 12 (8+4) bit floating point AD converter was measured, and the results was presented at 

the CCCD workshop in August 2001. The circuit showed 65 dB dynamic range which is a bit 

lower than expected. The reason was judged to be the high noise with the test setup. The total 

power consumption is 32 mW. A new test PCB was manufactured for further measurements with 

expected better noise performance. In order to optimize the performance of a pipeline A/D 

converter, which is a part of the floating-point A/D converter, an investigation of the step response 

of the amplifiers has been initiated in late 2001. 

Milestones: 

1 Complete the measurement of the latest FP-ADC chip by March 2002. Done 

2 Finish the design of a new FPADC chip with 10+5 bits by April 2002. Done 

3 Complete the measurement of the10-bit pipeline ADC during June 2002. Debugging 

4 Write an article about optimization of amplifier step responses before 

August 2002. 

Postponed


5 Prepare the measurements for the new FPADC chip in August 2002. Done 

6 Measure the new FPADC chip and write an article about it during Postponed 

August-September 2002. 

7 Prepare the Licentiate thesis before the end of 2002. Done 

Note: Johan Piper was heavily involved in constructing and teaching a new course, Advanced 

Analog Design, which consumes more time than expected. The design of the new FPADC chip 

was more extensive than anticipated and was not finished until the end of July. However a 

thorough analysis of noise and speed was made during this time and will contribute to the thesis. 

The new chip has been designed with a new feature that expands the dynamic range one more bit. 

The simulated performance is 10+5 bits floating-point A/D conversion with a sampling frequency 

of 100 MHz. Due teaching and the effort on the new chip, some other milestones were postponed. 

WP 3-2: Low-Glitch and RF D/A Converters 

Student: M.Sc. Yijun Zhou, Faculty-financed 

B.Sc. Lixin Yang, CCCD-financed 

Supervisors: Prof. Jiren Yuan, LU, CCCD-financed 


Description: The objective is to reduce the amplitude of unwanted frequency components at the 

output of a D/A converter so the reconstruction filter can be made simple or even removed. The 

final goal is to build a direct RF D/A converter to replace traditional analog power amplifiers, 

making a radio transmitter simpler, more efficient and linear. 

Results: 

• A new 8-bit 100-MHz interpolation D/A converter was designed and fabricated in 0.35µm 

standard CMOS. A new interpolation timing method has been developed for this chip based on 

the old one. The chip was tested successfully at VDD = 3.3V. The results are SFDR = 60.94 

dB at 3.79MHz, and the attenuation of its image component is 59.66 dB. The two-tone SFDR 

= 61.69 dB at 2.37 and 3.79 MHz. DNL < ±0.32 LSB, and INL < 0.12 LSB, with a power 

consumption of 54.5 mW. The D/A converter uses a 16-point linear interpolation to achieve a 

frequency response of (sinc) 2 instead of sinc function so the mirror frequency around 100 MHz 

(the clock frequency) can be substantially attenuated. The results show a good agreement with 

the theoretical analysis. 

• Another 10-bit 100-MHz interpolation D/A converter chip aiming for an RF D/A converter 

has been fabricated and tested. The results are SFDR = 56.1 dB at 7.37 MHz, and the 

attenuation of its image component is 45.35 dB. The three tone SFDR = 58 dB at 7.39, 8.39 

and 9.39 MHz, and the attenuation of their image components have reached the theoretical 

limit. 

• A direct digital RF amplitude modulator with a current fold has been designed and fabricated. 

A paper about this chip has published at ISCAS'2002. 

• A non-feedback multiphase clock generator chip has been designed. A paper about this chip 

has been published at ISCAS'2002. 

• A direct digital RF amplitude modulator without a current fold has been designed and 

fabricated. 

• A patent application named "A Direct Digital Amplitude Modulator" has been assigned to 

Ericsson Microelectronics. 

• A paper titled “10-bit, 100MHz CMOS linear interpolation DAC” has been accepted by 

ESSCIRC 2002. 

• The test of the two direct digital RF amplitude modulator chips has finished.


• A paper for the direct digital RF amplitude modulator without a current fold has been 

published at ESSCIRC 2002. 

• A paper cooperated with Lixin Yang for non-feedback multiphase clock generator using direct 

interpolation has been published at MIDWEST 2002. 

• Two direct digital RF quadrature modulator chips have been fabricated. 

• One paper, “An 8-Bit, 100 MHz CMOS Linear Interpolation DAC”, has been accepted for 

publication in IEEE Journal of Solid-state Circuits. 

• A chip of a single-stage direct interpolation multiphase clock generator with phase error 

average aimed for 500MHz input clock has been designed by Lixin Yang. The chip has been 

fabricated, and a paper about the chip has been published at Norchip 2002. 

• A chip of a 1GHz single-stage direct interpolation multiphase clock generator with phase error 

average has been designed, fabricated, and tested by Lixin Yang. 

• A paper titled “An arbitrarily skewable multiphase clock generator combining direct 

interpolation with phase error average” accepted for publication at ISCAS’2003. 

Milestones: 

1 A paper titled “10-bit CMOS linear interpolation DAC” based on the 

above measurements will be sent for publication in March 2002. 

2 The test of the two chips (direct digital RF amplitude modulators) will 

be finished in June 2002. 

3 A paper for the direct digital RF amplitude modulator without a current 

fold will be completed in August 2002. 

4 To explore a high frequency compensation technique for a high 

resolution and high speed D/A converter, and to write a paper on the 

result before September 2002. 

5 To design a high resolution and high speed D/A converter demonstrating 

the high frequency compensation technique before December 2002, 

which was replaced by constructing two direct digital RF quadrature 

modulator chips (one without current-fold and another one with) before 


6 Testing the direct digital RF quadrature modulator chips without currentfold 

in October 2002. 

7 Testing the direct digital RF quadrature modulator chips without currentfold 

in January 2003. 

8 To write two journal papers about the direct digital RF amplitude 

modulators with and without current fold before February 2003. 

9 To finish Ph.D. thesis before February 2003. 

Done 

Done 

Done 

Postponed to 

January 2003 

Postponed and 

done 

Postponed and 

done 

WP 3-3: High Speed Early Sampling and Digitizing Technique 

Student: M.Sc. Gang Xu, CCCD-financed 

Supervisors: Prof. Jiren Yuan, LU, Faculty-financed 


Description: The objective is to explore alternative sampling methods to overcome the 

shortcomings of traditional sub-sampling. The goals are high speed, high signal-to-noise ratio, low 

clock-and-charge feedthrough, and embedded anti-alias filtering. A/D converters with the 

improved sampling method and parallel structures are to be built to achieve high speed and early 

digitization. 

Results:


• Charge sampling technique is studied. The noise, clock jitter and clock feedthrough in charge 

sampling is compared with traditional voltage sampling and summarized in a paper. 

• A sampler with embedded FIR filter was fabricated and tested. The bandwidth of the filter is 3 

MHz and the side-band attenuation is 60 dB. The group delay in band is about 11 ns. The 

power consumption of the tested version is 35 mW. . In this FIR filter, the number of taps is 

not directly related to the hardware cost. 

• Based on the principle of charge sampling, a 500 MS/s CMOS sampler with an 8-bit accuracy 

was designed and sent for fabrication. 

• A current mode comparator is proposed for high speed AD converter. In traditional multi-step 

AD converter, the capacitor coupling method is the most commonly used for internal DA 

conversion. However, in a high-speed multi-step ADC, the set-up time of the capacitor 

coupling method is stringent. The proposed current comparator intends to break through the 

bottleneck of setting up time of capacitor coupling method and realize high speed multi-step 

AD conversion. The internal DA conversion is realized by current mode operation. A 2-step 

200 MS/s CMOS AD converter was designed and sent for fabrication based on this 

comparator. 

• 8 papers were published or accepted for publication: 

“Comparison of Charge Sampling and Voltage Sampling,” Midwest Symposium on Circuits 

and Systems, August 2000; 

“An Embedded Low Power FIR Filter,” ISCAS'2001, May 2001; 

“A Low Voltage High Speed Sampling Technique,” ASICON'2001, October 2001; 

“A 500 MS/s 8-bits CMOS Sampler,” GigaHertz'2001, November 2001; 

“A CMOS Analog FIR Filter with Low Phase Distortion,” ESSCIRC2002, September 2002. 

“Charge sampling analogue FIR filter”, accepted for publication on Electronics Letters. 

“Performance analysis of general charge sampling”, accepted for publication at ISCAS’2003. 

“A differential difference comparator for multi-step ADC”, accepted for publication at 

ISCAS’2003 

Milestones: 

1 To finish and to send the design of a revised 500 MS/s 8 bit CMOS Done at the 

sampler for fabrication in the middle of April 2002. 

end of July. 

2 To finish and to send the design of a 100 MS/s low power 2-step A/D 

converter using the current-mode comparators for fabrication in the end 

of May 2002. 

Done 

3 To finish the testing and redesign the above chips in December 2002. Done 

4 To write papers based on the test results in spring of 2003. 

WP 3-4: Design Techniques for Single Chip Mixed Signal Circuits and Systems 

Student: M.Sc. Konstantinos Theodoropoulos, CCCD-financed 

Supervisosr: Prof. Jiren Yuan, LU, Faculty-financed 


Description: The objective is to look for robust design techniques for the cohabitation of analog 

and digital circuits on a single chip, which is one of the key issues for system-on-chip. Noise 

coupling through the substrate and wires are the major topics to be addressed. Effective methods to 

suppress and/or to cancel such a noise are to be found. 

Results: 

• New digital circuit techniques with low noise injection were investigated to reduce the overall 

switching noise in a system-on-chip environment.


• A single input current-sensing differential logic (SCSDL) was proposed and published on 

ISCAS in May 2000. 

• A silent digital circuit technique was invented. This technique forces every stage in a pipeline 

to generate identical pre-charge current. The shape and magnitude of the current is controllable 

to adapt different clock frequencies. The total current therefore presents very small dI/dt noise 

in a time-interleaved system. 

• A parallel adder test chip using this technique was constructed in July 2002, and currently is 

under fabrication. 

Milestones: 

1 To design a chip implementing digital arithmetic units for testing the Done at the end of 

silent digital gates in order to confirm the noise manipulation and 

reduction technique before June 2002. 

July 

2 A paper tentatively titled “Low noise injection gates for system on Postponed and 

chip” will be prepared based on the above design in July 2002. under preparation 

3 To test the chip and to prepare a paper before October 2002. Postponed and 

ongoing 

4 To design an overall cell library and a second test chip in low 

switching noise IC design before January 2003. 

5 A paper regarding the second test chip will be prepared in February 

2003. 

6 To test the second chip and to prepare a paper before June 2003. 

WP 3-5: Re-configurable Low-Power A/D converter for a Flexible Radio Terminal 

Student: M.Sc. Martin Andersson, Socware-financed 

Supervisosr: Prof. Jiren Yuan, LU, Faculty-financed 

Dr. Henrik Sjöland, CCCD-financed 

Description: This is a new work package started April 2002. With the rapid development of 

mobile communication, the co-existence of different generation protocols will be inevitable. In 

such a scenario, a flexible radio terminal becomes necessary. The goal is therefore to implement a 

complete embedded re-configurable low power ADC in a real system-on-chip environment for 

such a terminal. The ADC should be scalable in dynamic range and bit rate, adaptive to different 

networks, and re-configurable to have minimum power consumption for different functionalities. 

Results: Simulation and identification of the best architecture for such an ADC is currently 

performing, and a time-interleaved structure based on recursive ADC cells was preliminarily 

identified as a promising architecture for this type of ADC. 

Milestones: 

1 Simulation and identification of the best architecture for an embedded 

re-configurable low power ADC. (April 2003) 

2 Design, implementation and test of the building blocks such as the S/H 

circuit, the low power ADC unit etc. (April 2004) 

3 Simulation and comparison of different correction strategies. (April 

2004) 

4 Understanding the impact of substrate noise to the ADC. (April 2005) 

5 To implement and test a complete embedded re-configurable low power 

ADC. (2005) 

Ongoing



WP 4-1: Ultra Low Power DSP for Pacemakers 

Student: Dipl. Ing. Joachim Rodrigues, CCCD-financed 


Dr. Leif Sörnmo, LU, CCCD-financed 

Description: The next generation of pacemakers will require more sophisticated classification 

algorithms. Such new classification algorithms have to be robust against various types of 

interferences. Since the longevity of a pacemaker is dependent on a single battery, circuits with 

extremely low power consumption have to be designed. Several different algorithms/architectures 

are developed, designed and evaluated on both theoretical and hardware level. 

Results: 

The initial phase of this project has been focused on algorithm exploration. The idea of using an 

artificial neural network (ANN) for a non-linear adaptive filter to pace the heart in a more 

"intelligent" way was investigated. The ANN has good performance but suffers from a high 

complexity. Therefore, two additional structures have been developed and investigated. Those 

studies have been performed with MATLAB simulations in cooperation with the medical signalprocessing 

group at the department. Achieved results have been presented at different international 

conferences. Following the algorithmic investigations the project is now ready for a hardware 

implementation phase to be conducted with special emphasis on ultra low power solutions. 

Milestones 

1 Hardware implementation of wavelet structure. (2002) FPGA is due by 03/03 

2 Hardware implementation of newly developed structure. (2002) FPGA is due by 04/03 

3 Comparative study between the two structures. (2002) Postponed after 1&2 

WP 4-2: Controller Synthesis and Processor Communication 

Student: M.Sc. Hongtu Jiang, SSF-financed 


Adj. Prof. Mats Torkelson, Ericsson AB, CCCD-financed 

Description: This project considers how to take a system or algorithm specification from a high 

level simulation to a efficient time-shared hardware architecture. For time-shared architectures the 

control structures are of main concern and such structures is the focus of this project. The main 

application area is MIPS intensive signal processing algorithms but both protocol and/or control 

dominated processor will be considered. 

Results: The project focuses on pursuing design automation concepts for controller structures for 

time-shared architectures. Work is being pursued in obtaining a design-flow of controller 

structures to be used in other accelerator projects. An existing tool has been modified to fit the 

present designing environment, i.e. controller structures are generated for implementation in an 

environment based on VHDL. This makes it possible to target designs for both FPGA and fullcustom 

implementation from the same description. A rather complex test design, a 2-dimensional 

image convolver, has been implemented and evaluated on an FPGA platform. Specific topics that 

have been pursued is how different memory structures affect the over all performance. Two 

different memory structures have been implemented, using two or three levels of image memories 

respectively.


Milestones: 

1 Existing tool for controller synthesis will be modified to support HWdesign 

in existing CAD-frameworks, e.g. VHDL. (2002) 

Done 

2 Target application will be implemented to show the functionality. (2002) Done 

WP 4-3: Implementation of Iterative Decoders 

Student: M.Sc. Pontus Åström, SSF-financed 


Dr. Ove Edfors, LU, CCCD-financed 


Description: This project aims at hardware realization of a high data rate channel encoder/decoder 

which will operate at a very low signal to noise ratio. The decoder utilizes iterative decoding, a 

recently discovered decoding algorithm, which operates closer to the Shannon limit than any 

previously reported algorithms. The drawback of the new algorithm is the high decoding 

complexity and large signal delay. These are the main problems that have to be solved to make this 

type of algorithms a competitive alternative. 

Results: The design of the turbo decoder has progressed rapidly and is now in the final design 

stages. All sub blocks are finished or close to be finished. The remaining steps are the design of a 

system-connect module, complete final system simulation and synthesis. The design is planned to 

be finished by April 15 to be sent for fabrication in a .35u process. The design of the macro block 

generator has progressed since the first release (a ROM only generator). The next version will be a 

general macro block generator for regular cell structures. Due to time limitations, the design of the 

macro generator is currently postponed. The first generation macro generator has been verified by 

a test chip, a 16 kbit ROM structure. The test chip was fully functional and worked in higher 

speeds than expected (Over 100 MHz, which is the limit of the test equipment). 

Milestones: 

1 A Hardware design of the Turbo Decoder will be sent for 

fabrication in April 2002. 

Postponed and done 

2 The Ph.D. graduation is expected during the fall of 2002. Postponed to 04/03 

WP 4-4: Hardware/Software Co-Optimization for Echo Cancellation 

Student: M.Sc. Anders Berkeman, CCCD-financed 



Description: The project will consider algorithm/hardware co-optimization, which is a crucial and 

underdeveloped field in the area of digital signal processing. As an application example a delayless 

echo-cancellation algorithm will be used. Cancellation of network echoes is a mature research 

area while acoustic echo-cancellation is an expanding area becoming increasingly more important 

in mobile communication and video-conferencing. Due to the delay introduced in mobile systems, 

it is crucial to have a delay-less algorithm resulting in an increased complexity. Previous 

algorithmic developments have been performed in a MATLAB environment with no consideration 

to a hardware implementation. In this project a complete hardware accelerator design is being 

developed. 

Results: A delay less acoustic echo cancellation scheme has been chosen to explore the properties 

of hardware/algorithm co-design. Such algorithms are likely to be more important in the future


with IP telephony requiring short delays and preferably hands-free implementation in for instance 

laptops. The algorithm has been studied from a complexity perspective with special emphasis on 

memories and the results have been published at international conferences. A strategy for cooptimization 

of FFT/FIR structures has been developed. A complete design is in it’s final stage to 

be sent for fabrication. 

Milestones: 

1 Complete hardware design will be completed and sent for fabrication 

April 2002. 

Done 

2 Ph.D. examination is expected during the 2 nd half of 2002. Done 

WP 4-5: An OFDM Synchronizer: Algorithm to Silicon 

Student: Tech. Lic. Stefan Johansson, CCCD- and SSF-financed 




Description: The project ended year 2000 with Licentiate degree. However the project is still 

relevant for other projects concerning OFDM systems This project concerns the realization of 

synchronization algorithms in wideband communication systems, especially OFDM systems. To 

synchronize such systems, two methods are known: to add pilot symbols and to correlate on a 

copy of the data. The second method is interesting since it can be done without affecting the 

transmitted data; the copy of the data is placed in the cyclic prefix, which is a guard interval that 

can not be used for data. 

Results: The synchronization algorithms have been implemented and simulated in a C program. 

This C program has been used to test various modifications and make appropriate simplifications 

to the algorithm. The C program has been gradually refined to model all the details of a hardware 

implementation, which includes fix-point arithmetic, memory accesses etc. The C program is also 

used together with a system model in Matlab to perform system simulations, which is used to see 

what impact algorithmic tradeoffs had on the system performance. The C program is compiled to 

the fastest available general purpose DSP from Texas Instruments. Simulations verify that it is 

impossible to achieve desired performance with a standard DSP implementation. With the help of 

the C program, the hardware architecture is described in the hardware modeling language VHDL. 

The VHDL model is verified by comparing simulation results with the C program. The VHDL 

code is synthesized to a cell library and a final layout has been obtained with the help of a place 

and route tool. The finished chip is fabricated and tested. The VHDL code has also been 

synthesized to an FPGA, which is used to compare performance between FPGA and ASIC 

implementations. A licentiate degree was achieved in May 2000. 

Milestones: 

1 A licentiate degree was achieved in May 2000 and the project is in the 

sleep mode. 

WP 4-6: Flexible Coding/Decoding for PAN 

Student: Matthias Kamuf, Socware-financed (Pacwoman) 


Dr. Peter Nilsson, LU, CCCD-financed 


Done


Prof. John B. Anderson, LU, Dept of IT 

Description: The main topic of the project is to investigate the trade-off between flexibility and 

performance/power in wireless communication architectures. For Personal Area Networks (PAN), 

flexibility will be desired to cope with varying applications and transmission conditions. However, 

there are several orders of magnitude in power efficiency between a software and a fully hardware 

mapped solution, unacceptable for battery operation. Therefore, new architectural strategies have 

to be developed. To limit the scope, the research will focus on hardware efficient implementation 

of multiple coding/decoding algorithms. The project is a part of the EU-project “Pacwoman”. 

Results: A flexible encoder has been implemented in VHDL and can be configured for a wide 

range of convolutional codes. The design has been tested on a FPGA platform. Encoder memory 

can be chosen between 1 and 10, with 16 feed-forward paths and 1 feedback path that can be 

configured for any set polynomial. Currently an interleaver is implemented for turbo coders. 

Further research is targeted on architectural solution for a flexible decoded structure, a much more 

challenging task. 

Milestones: 

1 Initial phase: implementation of flexible channel coder architectures. (1 st 

half 2002) 

Done 

2 Implementation of flexible channel decoder architectures. (2002) Ongoing 

3 Studies regarding trade-off between flexibility and power consumption. 


Ongoing 

WP 4-7: Flexible FFT with variable scalability and variable dynamic ranges for PAN 

Student: M.Sc. Fredrik Kristensen, CCCD-financed (AXIS, Hermes) 




Dr. Bengt-Arne Molin, AXIS Communications AB 

M.Sc. Anders Olsson, AXIS Communications AB 

M.Sc. Kerstin Lindh, AXIS Communications AB 

Description: The WP will study on high-end FFTs with main focus on scalability and bit loading. 

The first goal will be to find architectures for flexible FFTs. In a second stage, such structures will 

be implemented and tested. A main target is also to find good trade-offs strategies between 

flexibility and power consumption. The project is a part of the EU-project “Pacwoman” 

Results: Initial studies are targeted towards flexible FFT structures suitable for e.g. personal area 

network applications. A first test structure of a flexible FFT is designed and sent for fabrication. 

Milestones: 

1 Completion of pre-study. (2002) Done 

2 Fixed point model for a bitloading architecture will be developed. (2002) Ongoing 

3 Silicon implementation of crucial blocks will be sent for fabrication 

during the fall 2002. 

Done 

WP 4-8: Algorithms and Hardware for MIMO Systems 

Student: Zhan Guo, SSF-financed 

Supervisors: Dr. Peter Nilsson, LU, CCCD-financed




Description: This WP concerns system level modeling from the circuit design perspective of 

MIMO systems. The MIMO technique is very promising. Studies show that the data rates can be 

increased by one or two orders of magnitude. However, MIMO systems are very complex. The 

complexity is also the reason why such systems are not implemented today. New sub-micron 

technologies will however be capable to handle the increased complexity. The complexity will 

also accentuate the need for good models, not only for the single parts in the system. One main 

topic will be to trade-off circuit aspects as low power consumption and complexity to the system 

requirements. 

Results: A Ph.D. student started in April 2001. Initial literature studies on MIMO systems have 

been performed. MIMO systems like V-BLAST, D-BLAST, Turbo-BLAST, STTC and STBC 

have been studied. System simulations have been initiated. The project will go over in an 

implementation phase during the spring 2002. 

Milestones: 

1 Completion of pre-study. (2002) Done 

2 A system architecture will be developed. (2002) Ongoing 

3 Silicon implementation of crucial blocks will be sent for fabrication 

during the fall 2002. (Square root algorithm for MIMO detection) 

Done 

WP 4-9: Design Space Exploration for SoC 

Student: M.Sc. Henrik Svensson, Socware-financed 

Supervisors: Prof. Krzysztof Kuchcinski, Dept. of CS 


Description: By applying early estimations techniques, the impact of different architectural 

solutions can be investigated early on and the iteration loops in the design process can be 

shortened. These estimations have to be close enough approximations of the final implementation 

to give the designer enough guidance to chose between different design alternatives, but it need 

not be hardware/software specific. Early estimates can be based on full utilization of hardware 

modules, which is later refined to include bus structures and memory management techniques. 

Late estimates are based on hardware simulators, e.g. VHDL simulators, and power estimation 

tools. The WP is a cooperation between the Computer Science and the Electro Science 

departments, LTH. 

Results: Initial work has been focused on recapitulate previous research in the area of system 

design: Design methodologies, specification languages, formal representations, academic and 

industrial tools. Efforts have been made to capture specific design space exploration problem 

formulations valid for hardware/software system design, as well as suggested solutions to those 

problems. 

Milestones: 

1 A student will be hired during March 2002. Done 

2 Initial studies will be targeted towards existing algorithms and tools and 

their application to the design of a complete system, e.g. Bluetooth. 


Ongoing


WP 4-10: Algorithm/HW Co-design of Coding Schemes 

Student: Karl Thoren, SSF-financed 


Prof. John B. Anderson, LU, Dept. of Information Technology 

Description: The proposed research investigates the area of algorithm/hardware co-optimization 

applied to efficient channel coding for packet transmission. The BCJR algorithm is an interesting 

algorithm applicable both to channel and source coding modules, e.g. turbo- and tailbitingdecoders. 

Therefore, the main focus of the algorithm/hardware co-optimization will be this BCJR 

scheme. The main focus of the performed research is not only to implement a single coder, but 

also to study the concepts of algorithm/hardware co-design. 

Results: The BCJR algorithm deals bit probabilities and can suffer from precision problems when 

implemented in fixed point. A structure concerning bit-shifts has been investigated resulting in 

reduced complexity with a limited reduction in performance. Furthermore, investigations 

regarding the influence of correct channel estimation have been considered in the light of overall 

algorithmic properties. A novel approach for matrix multiplication, working both in logarithmic 

and linear domains, has been developed. 

Milestones: 

1 The results of the specific implementation of the 

BJCR algorithm, shown for tailbiting decoders will 

be investigated for a Turbo-decoder structure. (2002) 

2 New hardware efficient alternatives will be 

investigated in more detailed. (2002) 

3 Initialization of a close cooperation with the “Flexible 

Coding/Decoding for PAN” project. (2002) 

Postponed, Instead an investigation 

regarding higher rate codes 

has been performed. 

Done 

WP 4-11: ASIC Implementation of Algorithms for Adaptive Antennas 

Not done. The “Flexible … PAN” 

project is still in an early phase. 

Student: Fredrik Edman, SSF-financed 


Adj. Prof. Mats Torkelson, Ericsson AB 

Dr. Peter Karlsson, Telia Research AB 

Description: Signal processing algorithms for adaptive antenna arrays have very high demands on 

calculation capacity, which is difficult to achieve with standard processors in real time. Therefore, 

efficient implementation of these algorithms is required for adaptive antennas to be a feasible 

solution for future systems. Spatio-temporal receive algorithms are studied and efficient ASIC 

implementations of key building blocks are developed. 

Results: Matrix inversion is a key building block in many adaptive antenna algorithms. An array 

architecture, initially targeted for matrix inversion, has been developed. Ongoing work is being 

performed in pursuing a complete hardware implementation. This work is also being implemented 

for use in a radio channel measurement testbed in cooperation with other research groups and 

Telia Research. 

Milestones: 

1 An array structure for matrix inversion will be 

implemented, primarily for an FPGA. (2002) 

VHDL description done; FPGA 

implementation ongoing


2 This structure will be used in the channel measurement 

testbed. (2002) 

Ongoing 

Project 5: Digital Building Blocks and Implementation Technique 

WP 5-1: Implementation of Complex Multiplier and Divider 

Student: M.Sc. Anders Berkeman, CCCD-financed 



Description: Complex multiplication/division is one key component in several DSP algorithms. 

Initially, a novel multiplier architecture has been developed which has a higher clock frequency 

and/or a lower power consumption than previous architectures. A divider module has also been 

developed for use in larger accelerator designs. 

Results: Complex multiplication is one of the most important operations in signal processing 

applications. A novel architecture based on distributed arithmetic and a Wallace tree has been 

developed and silicon has been fabricated and tested. The multiplier part of the project was 

published in the IEEE Journal of Solid State Circuits. A divider architecture has been designed, 

fabricated and tested. It will be a part of the echo cancellation implementation. 

Milestones: 

1 Divider architecture has been designed and fabricated and is to be tested. 


2 The design will be incorporated into the echo canceller during spring 

2002. 

WP 5-2: Content Addressable Memories – CAMs 

Done 

Done 

Student: M.Sc. Hugo Hedberg, CCCD-financed (SwitchCore) 



Description: In high bitrate switches, CAM memories are important. This research project 

concern full custom design of memories addressed by the content. Throughput and power 

consumption is two important parameters. However, full custom implies long design time and less 

portability. Other methods will therefore also be studied. An alternative might be hash coded RAM 

structures. 

Results: The project has changed its focus. 

Milestones: 

1 Memory structures will be studied. (2002) Done 

2 Small test structures will be sent for fabrication. (2002) Postponed 

Note that this work package was started mid-2002 and was changed to a new work package titled 

Design Space Exploration for SoC in a new project titled Flexible Radio Terminal in the end of 

2002.


WP 5-3: Distributed asynchronous custom DSP-systems 

Student: M.Sc. Thomas Olsson, SSF-financed 



Description: In large area chips, clock distribution is an issue of great interest if high clock speeds 

are to be attainable. The clock line often suffers from a huge load, causing problems with clock 

skew, meaning different delays of the clock signal on different parts of the chip. In this project 

inter-processor and I/O-communication strategies for large systems on chip will be developed. The 

idea is to have locally clocked processors in self-contained modules. Of special interest is system 

partitioning. The project will answer questions about how to separate a system in different 

modules, when parallel or serial computing is applicable, how to transfer data, parameters, 

variables, interrupts, and control commands. 

Results: The activity of the project is in particular focused on low power, low voltage, and low 

digital clock interference. Clock generators with and without phase lock technique are investigated 

and prototype chips are implemented. A focus for the clock generators is implementation with 

only digital cell-library components and without off-chip components. The results also include a 

novel strategy for handling dual supply voltage in large digital designs. This approach is 

particularly suitable for digital hardware with varying requirement on supply voltage level, such as 

any course grain reconfigurable structure. A silicon implementation testing the dual supply voltage 

approach is also made. A Ph.D. graduation is expected during the fall year 2003. 

Milestones: 

1 A test circuit using dual supply voltage will be sent for fabrication. 


2 A prototype for synthesized cell library based clock generation will be 

sent for fabrication. (2002) 

3 The Ph.D. graduation is expected during the fall 2003. 


WP 6-1: HW accelerators for Two-dimensional signal processing 

Student: M.Sc. Thomas Lenart, CCCD-financed 


Dr. Mats Gustafsson, LU, CCCD-financed 

Done but still 

ongoing 

Done 

Description: The project deals with hardware implementation of 2-dimensional signal processing 

algorithms. The initial part will focus on holographic imaging, where the interference pattern is 

recorded electrically and the image is recreated by signal processing transformations. Those 

transformations are computationally heavy, demanding hardware implementation to achieve 

“acceptable” calculation times. The hardware part deals with the implementation of a 2dimensional 

FFT processor. Due to the high demands on image quality a relatively large image has 

to be processed which will lead to interesting issues regarding both computational complexity and 

memory handling. The reconstruction of the image is computationally demanding requiring 

extensive CPU time. Therefore, an ASIC (Application Specific Integrated Circuit) should be 

pursued which fits very well with the activities of the Digital ASIC Design group within CCCD. 

The initial part of the project will implement a 2-dimensional Fast Fourier Transform (FFT) 

accelerator while later parts may look at the complete system.


Results: A Ph.D. student in the area of digital hardware implementation was hired in early 2002. 

In the non-ASIC part of the project a resolution equivalent to the theoretical limit of an equivalent 

lens magnifier was achieved using an available CCD sensor. These algorithms have been 

implemented on a software platform with the accompanying limitations in image processing 

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efficient implementation of FFT processors. A new scaling method for FFTs has been developed 

which requires less memory than block scaling, since it does scaling on the fly. A comparison to 

convergent block floating point shows a memory reduction of approximately 25% for a 2048 

points FFT while keeping the dynamics in the calculations. A chip has been designed in a 0.35mm 

CMOS process and was sent for fabrication, August 2002. The fabricated chip has a core size of 

7.5mm 2 , and at a supply voltage of 1.8V it consumes 234mW at 50MHz. The 2D-FFT structure is 

being pursued for implementation on an FPGA platform where memory requirements are a crucial 

parameter due to the large images. 

Milestones: 

1 Feasibility study of an FPGA implementation of the 2-D FFT. (2002) Done 

2 Implementation either on FPGA or ASIC. (2002) Done 

3 Continued implementation with other parts of the holographic imaging 

system. (2002) 

Ongoing 


WP 7-1: Link budget and antennas 

Student: Lic. Anders Johansson, CCCD-financed 

Supervisors: Prof. Anders Karlsson, LU, CCCD-financed 

Description: The aim of the work package is to investigate the possibilities and limitations of 

wireless communication with medical implants. In order to design a power efficient wireless link it 

is important to know the link budget. The link budget depends on the attenuation of the signal, the 

radiation pattern of the antenna, the noise, and the area surrounding the body. A good estimation 

of the link budget is a prerequisite for a successful design of the radio system and for the design of 

the circuits of the radio transmitter. 

Currently there are three different investigations in the work package. First, the radio channel 

between an antenna placed inside the human body and a receiver outside the body is simulated 

using an advanced numerical program and a realistic model of the human body. The radiation 

pattern and the attenuation of the signal are calculated for different positions of arms and legs. 

Secondly, measurements of the background noise are performed at different clinics at hospitals. 

Thirdly, there is a study on different types of antennas that can be used for implants. 

Results: 

• A software package for simulation of the radio channel between an implant and a receiver 

outside the body has been developed. 

• Very accurate simulations of the radio channel have been done. 

• New types of patch antennas have been designed and simulated. 

• A system for measuring noise at hospitals has been developed. The measurements are 

performed during February and March. 

Milestones:


1 Measurements of noise at hospitals. The first part of these measurements 

will be done during spring 2002. 

2 An estimation of the radio channel for communication between an 

implant and a transmitter outside the body. This id to be done for a large 

number of different positions of the body. The estimation requires 

accurate measurements of noise and accurate simulations of the wave 

propagation. We expect to have a good estimation of the channel before 

March 2003. 

3 Design of antennas on implant. At the moment different types of 

antennas are being looked upon. Once the link budget is known the 

work to design an antenna and the feed of the antenna will be intensified. 

The design requires extensive simulations and measurements and it is 

expected be done within before September 2003. 

Done


Journal papers and letters 

Appendix 2: Publications 

1. P. Andreani and S. Mattisson, “A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor,” 

Analog Integrated Circuits and Signal Processing, pp. 17-24, January 2000. 

2. P. Andreani and L. Sundström, “A Chip for Linearisation of RF Power Amplifiers Using 

Predistortion Based on a Bit-Parallel Complex Multiplier,” Analog Integrated Circuits and 

Signal Processing, pp. 25-30, January 2000. 

3. A. Berkeman, V. Öwall and M. Torkelson, “A Low Logic Depth Complex Multiplier using 

Distributed Arithmetic,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 4, pp. 656-659, 

April 2000. 

4. P. Andreani and S. Mattisson, “On the Use of MOS Varactors in RF VCO's,” IEEE Journal of 

Solid-State Circuits, Vol. 35, No. 6, pp. 905-910, June 2000. 

5. B. Shi and L, Sundström, “A 200-MHz IF BiCMOS signal component separator for linear 

LINC transmitters,” IEEE Journal of Solid-State Circuits, Vol. 35 No. 7, pp. 987 -993. July 

2000. 

6. L. Sundström, “Spectral Sensitivity of LINC Transmitters to Quadrature Modulator 

Misalignments,” IEEE Transactions on Vehicular Technology, vol. VT-49, no. 4, pp. 1474- 

1487, July 2000. 

7. B. Shi and L. Sundström, “A 3.3V Power Feedback Chip for Linearization of RF Power 

Amplifiers,” Analog Integrated Circuits and Signal Processing, pp. 37-44, January 2001. 

8. Thomas Olsson and Peter Nilsson, “A fully Integrated Standard-Cell Digital PLL”, Electronics 

Letters, pp. 211-212, February 2001. 

9. S. Tadjpour, E. Cijvat, E. Hegazi and A. Abidi, “A 900-MHz Dual-Conversion Low-IF GSM 

Receiver in 0.35-um CMOS”, IEEE Journal of Solid-State Circuits, 36(12), pp. 1992-2002, 

May 2001. 

10. P. Andreani, “Very low phase noise RF quadrature oscillator architecture”, Electronics Letters, 

37(14), pp. 902-903, July 2001. 

11. P. Andreani and H. Sjöland, “Noise Optimization of an Inductively Degenerated CMOS Low 

Noise Amplifier”, IEEE Transactions on Circuits and Systems - II, 48(9), pp. 835-841, 


12. E. Hegazi, H. Sjöland and A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase 

Noise”, IEEE Journal of Solid-State Circuits, 36(12), pp. 1921-1930, December 2001. 

13. P. Andreani and H. Sjöland,"Tail Current Noise Suppression in RF CMOS VCOs", IEEE 

Journal of Solid-State Circuits, 37(3), pp. 342-348, March 2002. 

14. B. Shi and L. Sundström, “A Voltage-Translinear Based CMOS Signal Component Separator 

Chip for Linear LINC Transmitters”, to appear in the January 2002 issue of Analog Integrated 

Circuits and Signal Processing. 

15. H. Sjöland, , “Improved Switched Tuning for Differential CMOS VCO’s,” IEEE Transactions 

on Circuits and Systems - II, to appear in May 2002 issue. 

16. E. Cijvat, S. Tadjpour and A.A. Abidi, “Spurious Mixing of Off-Channel Signals in a Wireless 

Receiver and the Choice of IF”, IEEE Transactions on Circuits and Systems, Part II. vol. 49, 

no. 8, pp. 539-44, 2002. 

17. Gang Xu and Jiren Yuan, “Charge sampling analogue FIR filter”, submitted December 2002 

and accepted for publication on Electronics Letters, 2003. 

18. Yijun Zhou and Jiren Yuan, “A 10-bit wide band CMOS Direct Digital RF Amplitude 

Modulator”, submitted December 2002 and accepted for publication on IEEE Journal of Solid- 

State Circuits, 2003.


Book & Book chapters 

1. Joachim Neves Rodrigues, A.Th. Schwarzbacher and J. B. Foley, “Fast Dynamic Power 

Comparison at the VHDL Netlist Level,” In Problems in Modern Applied Mathematics, 

Edited by Nikos Mastorakis, 2000. 

International conference papers 

1. B. Shi and L. Sundström, “A novel design using translinear circuit for linear LINC 

transmitters,” Proceedings of 2000 IEEE International Symposium on Circuits and Systems, 

vol. 1, pp. 64 -67, May 2000. 

2. B. Shi and L. Sundström, “A LINC Transmitter Using a New Signal Component Separator 

Architecture,” Proceedings of the 51 st IEEE Vehicular Technology Conference, pp. 1909 - 

1913, May 2000. 

3. P. Andreani and S. Mattisson, “A CMOS gm-C IF Filter for Bluetooth,” Proceedings of CICC 

2000, paper 18-6, May 2000. 

4. P. Andreani and S. Mattisson, “A 1.8-GHz CMOS VCO Tuned by an Accumulation-Mode 

MOS Varactor,” Proceedings of ISCAS 2000, pp. I-315-318, May 2000. 

5. Roland Strandberg and Jiren Yuan, “Single Input Current-Sensing Differential Logic 

(SCSDL),” Proceedings of 2000 IEEE International Symposium on Circuits and Systems, pp. 

I-764-767, May 28-31, 2000, Geneva, Switzerland. 

6. Thomas Olsson, Peter Nilsson, Thomas Meincke, Ahmed Hemani, and Mats Torkelson, “A 

Digitaly Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally 

Synchronous Designs,” Proceedings of the 2000 International Symposium on Circuit and 

Systems, pp. III-13-16, May 28-31, 2000, Geneva, Switzerland. 

7. A. Berkeman, V. Öwall and M. Torkelson, “Co-Optimization of FFT and FIR in a Delayless 

Acoustic Echo Canceller Implementation,” Proceedings of IEEE International Symposium on 

Circuits and Systems, May 28-31, 2000, Geneva, Switzerland. 

8. B. Shi and L. Sundström, “A Translinear Chip for Linear LINC Transmitters,” Digest of 

Technical Papers of 2000 Symposium on VLSI Circuits, pp.58 -61, June 2000. 

9. Gang Xu and Jiren Yuan, “Comparison of Charge Sampling and Voltage Sampling,” 

Proceedings of 43 rd Midwest Symposium on Circuits and Systems, August 8-11, 2000, 

Lansing, Michigan, USA. 

10. Roland Strandberg and Jiren Yuan, “Analysis and Implementation of a Semi-Integrated Buck 

Converter with Static Feedback Control,” Proceedings of 43 rd Midwest Symposium on Circuits 

and Systems, August 8-11, 2000, Lansing, Michigan, USA. 

11. Anders J Johansson, “Analysis of formal randomness in a chaotic random number generator,” 

Proceedings of 43 rd Midwest Symposium on Circuits and Systems, August 8-11, 2000, 

Lansing, Michigan, USA. 

12. Lars Sundström, “Linearisation Techniques for RF Power Amplifiers,” Workshop on RF 

Circuits, 26 th European Solid-State Circuits Conference (ESSCIRC’00), September 2000. 

13. B. Shi and L. Sundström, “A 200MHz IF BiCMOS Chip for Linear LINC Transmitters,” 

Proceedings of 26 th European Solid-State Circuits Conference (ESSCIRC’00), pp. 282-285, 


14. P. Andreani, S. Mattisson, and B. Essink, “A CMOS gm-C Polyphase Filter with High Image 

Band Rejection,” Proceedings of 26 th European Solid-State Circuits Conference 

(ESSCIRC’00), pp. 244-247, September 2000. 

15. Jiren Yuan, “A Charge Sampling Mixer with Embedded Filter Function for Wireless 

Applications,” Proceedings of 2 nd International Conference on Microwave and Millimeter 

Wave Technology, pp. 315-318, September 14-16, 2000, Beijing, China. 

16. B. Shi and L. Sundström, “A Voltage-Translinear based CMOS Signal Component Separator 

Chip for Linear LINC Transmitters,” Proceedings of the 18 th NORCHIP Conference, 

November 2000.


17. Gang Xu and Jiren Yuan, “A Sampler with Embedded Filter Function,” Proceedings of 18 th 

NORCHIP Conference, pp. 128-133, November 6-7, 2000, Turku, Finland. 

18. Yijun Zhou and Jiren Yuan, “An 8-bit, 100 MHz Low Glitch Interpolation DAC,” 

Proceedings of 18 th NORCHIP Conference, pp. 315-319, Nov. 6-7, 2000, Turku, Finland. 

19. Stefan Johansson, Martin Nilsson and Peter Nilsson, “An OFDM Timing Synchronization 

ASIC,” Proceedings of ICECS’2000, December 2000, Kaslik, Lebanon. 

20. S. Tadjpour, E. Cijvat, E. Hegazi and A. Abidi, “A 900MHz Dual Conversion Low-IF GSM 

Receiver in 0.35um CMOS”, Digest of Tech. Papers of ISSCC 2001, pp. 292-293, San 

Francisco, California, February 2001. 

21. E. Hegazi, H. Sjöland and A. Abidi, “A Filtering Technique to Lower Oscillator Phase Noise”, 

Digest of Tech. Papers ISSCC 2001, pages 364-365, San Francisco, California, February 2001. 

22. P. Andreani and H. Sjöland, “A 2.2 GHz CMOS VCO with Inductive Degeneration Noise 

Suppression”, Proceedings of CICC 2001, pp. 197-200, San Diego, California, May 2001 

23. B. Shi and L. Sundström, “An IF CMOS Signal Component Separator Chip for LINC 

Transmitters”, Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 

49-52, May 2001. 

24. Johan Piper and Jiren Yuan, “Realization of a floating-point A/D converter”, Proceedings of 

2001 IEEE International Symposium on Circuits and Systems, vol. I, pp. 404-407, May 2001. 

25. Yijun Zhou and Jiren Yuan, “An 8-bit, 100 MHz Low Glitch Interpolation DAC,” 

Proceedings of 2001 IEEE International Symposium on Circuits and Systems, vol. IV, pp. 

116-119, May 2001. 

26. Gang Xu and Jiren Yuan, “An embedded low power FIR filter”, Proceedings of 2001 IEEE 

International Symposium on Circuits and Systems, vol. IV, pp. 230-233, May 2001. 

27. Thomas Olsson, Pontus Åström, and Peter Nilsson. “Dual Supply-Voltage Scaling for 

Reconfigurable SoCs”, Proceedings of ISCAS’2001, Sydney, May 6-9, 2001. 

28. P. Andreani, “A 1.8-GHz Monolithic CMOS VCO Tuned by an Inductive Varactor”, 

Proceedings of ISCAS '01, May 2001. 

29. Joachim Neves Rodrigues, Viktor Öwall and Leif Sörnmo, “QRS Detection for Pacemakers in 

a Noisy Environment Using a Time Lagged Artificial Neural Network”, Proceedings of 

ISCAS 2001, Sydney, May 6-9, 2001. 

30. P. Andreani and H. Sjöland, “A 1.8 GHz CMOS VCO with Reduced Phase Noise”, Digest of 

Tech. Papers VLSI Symposium 2001, pp. 121-122, Tokyo, Japan, June 2001. 

31. Ali. Karimi-Sanjaani, H. Sjöland and A. Abidi, “A 2GHz Merged CMOS LNA and Mixer for 

WCDMA”, Digest of Tech. Papers VLSI Symposium 2001, pp. 19-22, Tokyo, Japan, June 

2001. 

32. Peter Nilsson, Petru Eles, and Hannu Tenhunen, “Socware: A New Swedish Design Cluster 

for System-on-Chip”, Proceedings of the 2001 Microelectronic Systems Education Conference 

(MSE'01), June 17-17 2001, Las Vegas, Nevada, USA. 

33. Karl Thoren, Viktor Öwall and John B. Anderson, “Precision Issues in the Implementation of 

BCJR Decoders”, Proceedings of 2001 IEEE International Symposium on Information Theory 

(ISIT 2001), Washington D.C., June 24-29, 2001. 

34. W. Shan and L. Sundström, “Effects of Filter Ripple in Predistortion Linearizer 

Architectures”, Proceedings of European Conference on Circuit Theory and Design, ECCTD 

'01, pp. II 33-36, August 2001. 

35. Thomas Olsson and Peter Nilsson, “A Digital PLL made from Standard Cells”, Proceedings of 

the 11:th European Conference on Circuit Design (ECCTD'01), pp. I-277 - I-280, Espoo, 

Finland, August 2001. 

36. E. Westesson and L. Sundström, “Low Power Complex Polynomial Predistorter Circuit in 

CMOS for RF Power Amplifier Linearization”, Proceedings of ESSCIRC 2001, Sep. 2001. 

37. E. Cijvat, “A 0.35um CMOS DCS Front-End with Fully Integrated VCO”, Proceedings of 

ICECS 2001, September 2001.


38. B. Shi and L. Sundström, “Investigation of a Highly Efficient LINC Amplifier Topology”, 

Proceedings of IEEE Vehicular Conference Fall 2001, October 2001. 

39. W. Shan and L. Sundström, Spectral Sensitivity of Predistortion Linearizer Architectures to 

Filter Ripple”, Proceedings of the IEEE Vehicular Technology Conference, October 2001. 

40. Gang Xu and Jiren Yuan, “A low-voltage high-speed sampling technique”, Proceedings of the 

4th International Conference on ASIC, pp. 228-231, October 2001. 

41. Pontus Åström and Peter Nilsson, “Application of Software design patterns to DSP library 

design”, Proceedings of the 14th International Symposium on System Synthesis (ISSS 2001), 

Montreal, Canada, October 1-3, 2001. 

42. L. Durkalec, L. Sundström and T. Mattsson, “Systematic design of bandpass amplifier with Qenhancing”, 

Proceedings of Norchip 2001, November 2001. 

43. M. Åström, S. Olmos, L. Sörnmo, “Wavelet-based detection in cardiac pacemakers”, Proc. 

IEEE Conference on Engineering in Medicine and Biology, Istanbul, Turkey, 2001. 

44. P. Andreani, “A Low-Phase-Noise Low-Phase-Error 1.8GHz Quadrature CMOS VCO”, 

Digest of Tech. Papers of ISSCC 2002, San Francisco, California, February 2002. 

45. R. Strandberg, P. Andreani and L. Sundström, “Bandwidth Considerations for a CALLUM 

Transmitter Architecture”, Proceedings of 2002 IEEE International Symposium on Circuits 

and Systems, May 2002. 

46. L. Durkalec, L. Sundström and T. Mattsson, “Properties of RF Bandpass Amplifier Topology 

with Q-Enhancing”, Proceedings of 2002 IEEE International Symposium on Circuits and 

Systems, May 2002. 

47. Yijun Zhou and Jiren Yuan, “A Direct Digital RF Amplitude Modulator”, Proceedings of 

2002 IEEE International Symposium on Circuits and Systems, May 2002. 

48. Lixin Yang, Yijun Zhou and Jiren Yuan, “A non-feedback multiphase clock generator”, 

Proceedings of 2002 IEEE International Symposium on Circuits and Systems, May 2002. 

49. Peter Nilsson and Viktor Öwall, Socware: “A New System-on-Chip Curriculum at 

Lund University”, Proceedings of the 4th European Workshop on Microelectronics Education 

(EWME’2002), Baiona, Spain, May 2002. 

50. W. Shan and L. Sundström, “Effects of Anti-Aliasing Filters in Feedback Path of Adaptive 

Digital Predistortion”, Proceedings of IMS2002, June 2002. 

51. N. Troedsson and H. Sjöland, “An Ultra Low Voltage 2.4 GHz CMOS VCO”, Proceeding of 

RAWCON 2002, pp. 205-208, Boston, Massachusetts, August 2002. 

52. N. Troedsson and H. Sjöland, “High Performance 1V 2.4 GHz CMOS VCO”, Proceeding of 

Asia-Pacific Conference on ASIC 2002, pp. 185-188, Taipei, Taiwan, August 2002. 

53. Thomas Olsson and Peter Nilsson, "An all-Digital PLL Clock Multiplier", to appear in 

Proceeding of Asia-Pacific Conference on ASIC 2002 (AP-ASIC2002), pp. , Taipei, Taiwan, 


54. F.Tillman and H. Sjöland, “1 Volt CMOS Bluetooth Front-End,” Proceeding of ESSCIRC 

2002, Firenze, Italy, September 2002. 

55. Yijun Zhou and Jiren Yuan, “A 10-bit 100-MHz CMOS Linear Interpolatopn DAC”, 

Proceeding of ESSCIRC 2002, Firenze, Italy, September 2002. 

56. Gang Xu and Jiren Yuan, “A CMOS FIR Filter with Low Phase Distortion”, Proceeding of 

ESSCIRC 2002, Firenze, Italy, September 2002. 

57. Yijun Zhou and Jiren Yuan, “A Low Distortion Wide Band CMOS Direct Digital RF 

Amplitude Modulator”, Proceeding of ESSCIRC 2002, Firenze, Italy, September 2002. 

58. A. Berkeman and V. Öwall, “Architectural Tradeoffs for a Custom Implementation of an 

Acoustic Echo Canceller”, to appear in Proceedings of the 2002 Nordic Signal Processing 

Symposium, Hurtigruten from Tromsø to Trondheim, Norway, Oct 4-7, 2002. 

59. J. Neves Rodrigues, V. Öwall, L. Sörnmo, “R-wave detection for pacemakers using a matched 

filter based on an artificial neural network”, Accepted for presentation at the 9th International 

Conference on Neural Information Processing (ICONIP), Singapore, November 2002.


60. Lixin Yang and Jiren Yuan, “A single-stage direct interpolation multiphase clock generator 

with phase error average”, Proceedings of the 20 th Norchip Conference, pp. 297-302, 

November 2002. 

61. Fredrik Kristensen, Peter Nilsson and Anders Olsson, “A Flexilbe FFT Processor”, 

Proceedings of the 20 th Norchip Conference, pp. 121-126, November 2002. 

62. Thomas Lenart and Viktor Öwall, “A Pipelined FFT Processor using Data Scaling with 

Reduced Memory Requirements”, Proceedings of the 20 th Norchip Conference, pp. 74-79, 

November 2002. 

63. Gang Xu and Jiren Yuan, “Performance analysis of general charge sampling”, accepted for 

publication on Proceedings of ISCAS’2003, May 2003. 

64. Gang Xu and Jiren Yuan, “A differential difference comparator for multi-step ADC”, accepted 

for publication in Proceedings of ISCAS’2003, May 2003. 

65. Lixin Yang and Jiren Yuan., “An arbitrarily skewable multiphase clock generator combining 

direct interpolation with phase error average”, accepted for publication in Proceedings of 

ISCAS’2003, May 2003. 

66. P. Astrom and P. Nilsson, “Hardware Architecture for Power Efficient and Portable UMTS 

Tubo decoder,” Accepted for publication in Proceedings of World Wireless Congress, 

3Gwireless’2003, San Francisco, CA, USA, May 2003. 

67. Matthias Kamuf, John B. Anderson, and Viktor Öwall, “Providing flexibility in a 

convolutional encoder”, accepted for publication in Proceedings of ISCAS’2003, May 2003. 

68. Thomas Olsson and Peter Nilsson, “A Digitally Controlled PLL for Digital SOCs”, accepted 

for publication in Proceedings of ISCAS’2003, May 2003. 

National conference papers 

1. Jiren Yuan, “Accurate Sampling of Radio Signals Beyond Gigahertz in CMOS,” Proceedings 

of GHz 2000 Symposium, pp. 277-280, March 13-14, 2000, Gothenburg, Sweden. 

2. P. Åström, S. Johansson, P. Nilsson, “Design Patterns for Hardware Datapath Library 

Design”, Proceedings of the Swedish System-on-Chip Conference (SSoCC'01), Arild, 

Sweden, March 20-21, 2001. 

3. H. Sjöland, “Improved Switched Tuning of Differential CMOS VCO’s”, GigaHertz 2001 

Symposium, Lund, Sweden. 

4. Gang Xu and Jiren Yuan, “A 500MS/s 8-bit CMOS Sampler”, GigaHertz 2001 Symposium, 

November 2001, Lund, Sweden. 

5. H. Sjöland, “RF CMOS Circuit Blocks for Wireless Transceivers – State of the Art and the 

Future”, Microelectronics and Optics – Innovative Technologies, November 2001, Stockholm, 

Sweden. 

6. P. Åström, S. Johansson, P. Nilsson, “Design Patterns for Hardware Datapath Library 

Design”, Proceedings of the Swedish System-on-Chip Conference (SSoCC'01), Arild, 

Sweden, March 20-21, 2001. 

7. P Åström and P Nilsson, “Implementation Aspects of High Throughput Iterative Decoders”, 

Proceedings of the Swedish System-on-Chip Conference (SSoCC'02), Falkenberg, Sweden, 

March 18-19, 2002. 

8. Z Guo and P Nilsson, “On Detection Algorithms and Hardware Implementations for V- 

BLAST”, Proceedings of the Swedish System-on-Chip Conference (SSoCC'02), Falkenberg, 

Sweden, March 18-19, 2002. 

9. H Jiang and V Öwall, “Controller Synthesis for Hardware Accelerator Design”, Proceedings 

of the Swedish System-on-Chip Conference (SSoCC'02), Falkenberg, Sweden, March 18-19, 

2002. 

10. Thomas Olsson and Peter Nilsson, “A PLL Clock Multiplier made from Digital Standard 

Cells”, RVK 2002. 

11. Karl Thorén, Viktor Öwall and John B. Anderson, “Alternative Hardware Implementation of 

the Tailbiting BCJR Decoder”, RVK 2002.


12. Fredrik Edman and Viktor Öwall, “Optimised QR-decomposition Core for Adaptive 

Beamforming”, RVK 2002. 

Technical reports 

1. Mikael Sebesta, Mats Gustavsson, Sven-Göran Petersson, and Peter Egelberg, “Lensless 

Microscopy - A Feasibility Study,” August 2000. 

Patent and Patent Application 

1. Jiren Yuan, “Floating-Point Analog-to-Digital Converter,” No. 9802787-3, granted Feb 2000. 

2. Shousheng He and Mats Torkelson, “Real-Time Pipeline Fast FourierTransform Processors,” 

No. US6098088, granted August 2000. 

3. Jiren Yuan and Yijun Zhou, “A Direct Digital Amplitude Modulator,” No. 0004031-1, filed 

November 2000. 

4. Anders Karlsson, “An optimized VHF/UHF telemetry antenna suitable for miniaturized 

implantable devices”, Reference No. A00 E 2092, August 24, 2001. 

5. Magnus Åström, Salvadol Olmos, and Leif Sörnmo, “Cardiac Event Detector”, Swedish 

"Patentverket" Reference No. 0103562-5, filed October 23, 2001. 

6. Henrik Sjöland and Pietro Andreani, “Enhanced Low-Noise Amplifier”, P.C.T. Patent 

Application No. PCT/EP02/03889. 

Ph.D. theses 

1. Bo Shi, “Linear Transmitter Design Using Nonlinear Analog Circuits”, Department of 

Electroscience, ISSN 1402-8662, August 2001. 

2. Martin Lantz, “Systematic Design of Linear Feedback Amplifiers”, Department of 

Electroscience, ISSN 1402-8662, No. 29, November 2002. 

3. Anders Berkeman, “ASIC Implementation of a Delayless Acoustic Echo Canceller”, 

Department of Electroscience, ISSN 1402-8662, No. 32, December 2002. 

Licentiate theses 

1. Stefan Johansson, “ASIC Implementation of an OFDM Synchronization Algorithm,” Dept. of 

Applied Electronics, Lund University, Sweden, No. 15, ISSN 1402-8662, May 2000. 

2. Anders J. Johansson, “Theory and Use of Chaotic Oscillators in Electronic Communications,” 

Dept. of Applied Electronics, Lund University, Sweden, No. 20, ISSN 1402-8662, Sep. 2000. 

3. Torbjörn Sandström, “CMOS Receiver Design”, Dept. of Electroscience, ISSN 1402-8662, 

April 2001. 

4. Anna-Karin Stenman, “Some Design Aspects on RF CMOS LNAs and Mixers”, Dept. of 

Electroscience, ISSN 1402-8662, December 2001. 

5. Weiyun Shan, “Study of Imperfection in Predistortion Linearizer Systems”, Dept. of 

Electroscience, ISSN 1402-8662, August 2002. 

Master theses 

1. Jonas Haraldsson, “A Rayleigh Fading Channel Model Based on the Inverse Discrete Fourier 

Transform,” supervised by Peter Nilsson, February 2000. 

2. Robert Almåker, and Hoc Co Tiet, “Test Platform to Verify Edge RF Receiver Performance,” 

supervised by Lars Sundström, March 2000. 

3. Daniel Ågren, and Andreas Lindh, “Implementation of an 8X10 Gbit/s Cellswitch,” 

supervised by Viktor Öwall, March 2000. 

4. Johan Fredriksson, and Mattias Karlsson, “Implementation of Universal Serial Bus Function 

Core,” supervised by V Öwall, industry, for C Technologies AB, March 2000.


5. Johnny Davidsson, and Niklas Pavlovic: “Krypton,” supervised by Peter Nilsson, for Axis 

Communications AB, March 2000. 

6. Tobias Andersson, and Roger Nilsson: “Power Consumption and Chip Area Estimation 

Applied on different Implementations of Lattice Wave Digital Filter”. supervised by Peter 

Nilsson, for Ericsson Mobile Communications AB, June 2000. 

7. Filip Netrval: “Design strategies to optimize Power Consumption of Digital Signal Processing 

Circuits,” supervised by Peter Nilsson, for Infineon, June 2000. 

8. Emil Karheiding, “Path Predictor,” supervised by Viktor Öwall, for Volvo, June 2000. 

9. Fredrik Tillman: “Measurement, Amplifiers for a Bluetooth radio,” supervised by Pietro 

Andreani, for Ericsson Mobile Communications AB, July 2000. 

10. Tibor Ola´h, “Linear Mixer for GSM-Receivers,” supervised by L Durkalec, for Ericsson 

Mobile Communications AB, August 2000. 

11. Lars Andersson, and Niklas Troedsson, “RF Power Amplifier Linearization for EDGE 

Modulated Signals,” supervised by Lars Sundström, for Ericsson Mobile Communications 

AB, September 2000. 

12. Lauri Piitulainen, “MPEG4 Compression-Decompression,” supervised by Viktor Öwall (LU), 

Anders Berkeman (LU) and Stefan Lundberg (AXIS), October 2000. 

13. Johan Johansson, “Video Decoder Design,” supervised by Viktor Öwall (LU), Anders 

Berkeman (LU) and Stefan Lundberg (AXIS), December 2000. 

14. Ovidio Zaharia, and Rade Krìcak , “An CORDIC-implementation of averaging circuit,” 

supervised by Peter Nilsson (LU), Erik Hertz (ECS) and Shousheng He (ECS), February 2001. 

15. Johan Jakobsson and Anders Karlsson, “Bluetooth Protocol Analyzer”, in cooperation with 

Ericsson Mobile Platforms, supervised by Peter Nilsson and Viktor Öwall, January 2001. 

16. Thomas Edsö, “VLSI Implementation of a Compact and Portable JPEG Encoder”, supervised 

by Viktor Öwall, March 2001. 

17. M. Jacobsson and H. Lindgren, “Wireless Communication with Implant: Wave Propagation 

and Antennas”, in cooperation with St Jude Medical AB, Supervised by Anders Karlsson, 

April 2001. 

18. H. Luong and C. Huynh, “Power Sensing Methods in Mobile Phones”, in cooperation with 

Ericsson Mobile Platforms, Supervised by H. Sjöland, April 2001. 

19. Anders Kamf and Tom Svensson, “MP3-decoder for Blokks”, in cooperation with 

Hårdvarubolaget, supervised by Viktor Öwall and Anders Berkeman, August 2001. 

20. H. Jönsson, “Evaluation of GSM PA Control Based on a Chipset from National 

Semiconductor”, in cooperation with Ericsson Mobile Platforms, Supervised by R. Strandberg 

and H. Sjöland, September 2001. 

21. Jan-Peter Nilsson and Fredrik Andersson, “Ethernet based reader for finger prints”, in 

cooperation with Precise Biometrics”, supervised by Peter Nilsson and Viktor Öwall, 


22. Anders Kamf and Tom Svensson, “A flexible Channel Estimator HW for WCDMA Mobile 

Platforms”, in cooperation with Ericsson Mobile Platforms, supervised by Peter Nilsson and 

Viktor Öwall, September 2001. 

23. J. Nilsson and S. Nalic, “Concept Evaluation of a GSM Low-IF Receiver”, In cooperation 

with Ericsson Mobile Platforms, Supervised by H. Sjöland, November 2001. 

24. Hugo Hedberg and Christian Sternell, “An FPGA Platform for Traffic Management 

Prototyping and Evaluation”, in cooperation with SwitchCore, supervised by Viktor Öwall and 

Anders Berkeman, November 2001. 

25. Fredrik Norén, “Bluetooth Mandatory Audio Codec: Low Complexity Subband Coder”, in 

cooperation with Ericsson Mobile Platforms, supervised by Peter Nilsson, Novembre 2001. 

26. Staffan Gadd and Thomas Lenart, “MP3 decoder via Bluetooth-link”, in cooperation with 

Ericsson Mobile Platforms, supervised by Viktor Öwall and Anders Berkeman, Nov. 2001.


27. A. Mårtensson and T. Påhlsson, “Fully Integrated Low-IF FM Broadcast Receiver, part 1 of 2, 

the Front-End”, in cooperation with Ericsson Mobile Platforms, supervised by H. Sjöland, 

December 2001. 

28. H. Sundelin and D. Mravac, “Fully Integrated Low-IF FM Broadcast Receiver, part 2 of 2, the 

IF part”, in cooperation with Ericsson Mobile Platforms, supervised by H. Sjöland, Dec. 2001. 

29. Martin Levin and Fredrik Tolf, “Hardware accelerator for 3D graphics”, in cooperation with 

Ericsson Mobile Platforms, supervised by Viktor Öwall and Anders Berkeman, Dec. 2001. 

30. Kristian Henningsson, “Reduction of Memory Size for a GSM Channel Decoder”, in 

cooperation with Ericsson Mobile Platforms, supervised by Viktor Öwall, January 2002. 

31. Christel Persson and Maria Lovén, “Hardware Accelerator for a Wave Table Oscillator”, in 

cooperation with Ericsson Mobile Platforms, supervised by Viktor Öwall and Anders 

Berkeman, February 2002. 

32. Christian Johansson and Staffan Klevfors, “Scan Based ASIC Design”, in cooperation with 

Ericsson Mobile Platforms AB, supervised by Viktor Öwall, February 2002. 

33. K. Bergfors and O. Ekenberg, “Extended Range Bluetooth Link”, in cooperation with Dialog 

Semiconductor, supervised by F. Tillman and H. Sjöland, February 2002. 

34. F. Nilsson and K. Norling, “Design Study of a Wide Output and Input Range DC/DC Buck- 

Converter for Mobile Applications”, in cooperation with Ericsson Mobile Platforms, 

supervised by R. Strandberg and H. Sjöland, March 2002. 

35. Eric Carlberg, “Data Acquisition Card Using the CardBus Standard”, in cooperation with 

Institut Eurécom, France, supervised by Viktor Öwall, May 2002. 

36. A. Tagesson, “Interference Cancellation in Frequency Division Duplex Mobile Telephone 

Systems”, in cooperation with Ericsson Mobile Platforms, supervised by P. Cijvat and H. 

Sjöland, June 2002. 

37. J. Björk and P. Hugosson, “Discrete Bluetooth Power Amplifier”, in cooperation with Sony 

Ericsson Mobile Communications AB (SEMC), supervised by H. Sjöland (LU), Andreas 

Glantz (SEMC), and Hannes Rahn (SEMC), June 2002. 

38. Emil Sjölin and Martin Ghidini, “Sigma-Delta Modulator”, in cooperation with Dialog 

Semiconductor AB, supervised by Henrik Sjöland (LU), Niklas Troedsson (LU), and Mikael 

Hegardt (Dialog Semiconductor AB), August 2002. 

39. Johan Hill and Staffan Ek, “Krets för kvalitetskontroll av DVD-skivor”, in cooperation with 

AudioDev AB, supervised by Peter Nilsson (LU), Mats Bylander (AudioDev AB), and Henrik 

Wall (AudioDev AB), August 2002. 

40. Hongwu Tong and Ingemar Lind, “Baseband Processor for Bluetooth”, in cooperation with 

Ericsson Technology Licensing AB (EBT), supervised by Peter Nilsson (LU), Anders 

Berkeman (LU), T Grahm (EBT), and Stefan Nilsson (EBT), September 2002. 

41. Johan Wernehag, “Lågeffekt radiosändare”, in cooperation with St. Jude Medical AB, 

supervised by Henrik Sjöland (LU) and Hans Abrahamsson (St. Jude Medical AB), Dec. 2002. 

42. Turan Caliskan, “Digital codec med HIFI-prestanda”, in cooperation with Ericsson Mobile 

Platforms AB, supervised by Peter Nilsson (LU), Bengt Edholm (EMP), and Mikael 

Holmström (EMP), December 2002. 

43. Malin Andersson and Martin Kasprzyk, “Design of nano CPU and corresponding compiler”, 

in cooperation with Ericsson Mobile Platforms AB, supervised by Viktor Öwall (LU), Mikael 

Andersson (EMP), and Fedor Elsing (EMP), December 2002. 

44. Martin Ohlsson and Anna Eriksson, “JPEG encoding hardware accelerator”, in cooperation 

with Ericsson Mobile Platforms AB, supervised by Viktor Öwall (LU), Anders Berkeman 

(LU), Erik Ledfelt (EMP), and Anders Ekelund (EMP), December 2002. 

45. Christian Elgaard and Johand Löfgren, “Byggsätt för oscillatorer”, in cooperation with 

Ericsson Mobile Platforms AB, Philips and CTH, supervised by Henrik Sjöland (LU), and 

Philipe Pascal (Philips), December 2002. 

46. Martin Johansson and Michael Karlsson, “Finger Sensor Interface”, in cooperation with 

Precise Biometrics, supervised by Viktor Öwall and Anders Berkeman, December 2002.

Annual Report 2002 and the Final Report of Stage 2

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