weak inversion in analog and digital circuits - Lund Institute of ...

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Weak inversion EVOLUTION OF IC WITH SCALED-DOWN PROCESSES • Scaling-down of process: • dimension scaling by factor k • all voltages decreased by k, except U T : - analog circuits: V DSsat must be decreased by k, thus V DSsat 2U T - digital circuits: V B decreased by k, thus VB -V IC ⎛ T0 on = ⎝ decreased by k 2nUT • Weak inversion approached for constant temperature T. 2 µVDSsat • Transition frequency: fT = increased by k 2πL2 - weak inversion with L=100nm : fT >4 GHz ⎛ ⎝ CSEM, E. Vittoz, 2003 ⎛ ⎝ IC = 2 ⎛ ⎝ 2 decreased by k 2 page 12
V D2 Weak inversion V DS2 LOW-VOLTAGE CASCODE IN WEAK INVERSION T 2 T 3 T 1 I V DS1 I V R T 4 T 5 • Model in weak inversion yields: V DSsat = 4 to 6U T per transistor substrate for P = M = 8 : V DS1=5U T, V DS1 = U T ln [ P (1+ 2M)] thus V D2 = 10U T sufficient to saturate T 1 and T 2 CSEM, E. Vittoz, 2003 β 2 β 3 β4 β5 = P and =M [2] page 13 All transistors in weak inversion with:
Page 1 and 2: Weak inversion • Behaviour and mo
Page 3 and 4: Weak inversion • Given by: V G -V
Page 5 and 6: Weak inversion -Q i β/C ox Drain c
Page 7 and 8: I D /I F 1 Weak inversion I D ~ 1-e
Page 9 and 10: Weak inversion I F , R I S CONTINUO
Page 11: Weak inversion SUMMARY OF FEATURES
Page 15 and 16: Weak inversion CURRENT GENERATION W
Page 17 and 18: GN IN Weak inversion Gk simple exam
Page 19 and 20: Weak inversion BASIC CONSIDERATIONS
Page 21 and 22: Weak inversion STATIC CURRENT AT LO
Page 23 and 24: Weak inversion 1 Td T0 0.1 DELAY TI
Page 25 and 26: Weak inversion PT d CU T 2 normaliz
Page 27 and 28: Weak inversion MAXIMUM SPEED CSEM,
Page 29 and 30: Weak inversion NUMERICAL RESULTS
Page 31 and 32: Weak inversion SYSTEM ARCHITECTURE
Page 33: Weak inversion REFERENCES CSEM, E.

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