weak inversion in analog and digital circuits - Lund Institute of ...

Weak inversion 

• Behaviour and model of MOS transistors in weak inversion [1,2,3]. 

• Examples of analog circuits. 

CCCD Workshop 2003, Lund, Oct. 2-3 

WEAK INVERSION IN 

ANALOG AND DIGITAL CIRCUITS 

Eric A.Vittoz 

CSEM, Centre Suisse d'Electronique et de Microtechnique SA 

Jaquet-Droz 1, CH 2007 Neuchâtel, Switzerland 

eric.vittoz@csem.ch 

• Exploratory analysis of weak inversion logic [4,5]. 

CSEM, E. Vittoz, 2003 

page 1


W,L width, length of the channel 

Cox gate capacitance per unit area 

VS UT = kT/q ( = 26 mV at 300°K) 

V = local non-equilibrium voltage in channel : channel voltage 

(quasi-Fermi potential of electrons) 

• at source end of channel: V = VS • at drain end of channel: V = VD Qi local mobile inversion charge in channel (electrons) 

gate threshold voltage for V=0. 

V T0 

B 

V S 

p 

MOS TRANSISTOR : DEFINITIONS 

n-channel 

V D 

D 

VG G 

S 

n+ n+ 

local substrate 

I D 


V S 

symbols: 

B 

G 

page 2 

S D 

p-channel 

n-channel 

S D 

B 

V G 

V G 

V D 

I D 

I D 

V D


• Given by: 

V G -V T0 

0 

- Q i /C ox 

slope -n 

I D 

β 

V S V D 

V D 

∫ ID = β - dV 

V S 

Q i 

C ox 

V G const. 

DRAIN CURRENT 

V 


with β = µC ox W 

L 

strong inversion, slope factor n =1.2 to 1.6 

-Qi Cox weak inversion: = 2nU T exp 

Pinch-off voltage V P ≅ V G - V T0 

n 

V P -V 

U T 

page 3 

(µ=mobility) 

exponential 

• Weak inversion already possible for V S =0 if VG


-Q i /C ox 

0 

slope -n 

V G -V T0 >0 

V P >0 

DRAIN CURRENT IN WEAK INVERSION 

(vertical axis magnified) 

V S 

I D /β 

V D 

V 


slope -n 

VP


-Q i β/C ox 

Drain current ID = 

I D 

V S V D 

FORWARD AND REVERSE CURRENTS 

V 

-Q i β/C ox 

V S 

forward 

current I F 

I F 


V 

-Q i β/C ox 

reverse 

current I R 

I R 

V D 

I D (V G ,V S ,V D ) = F(V G ,V S ) - F(V G ,V D ) = I F - I R 

page 5 

• Drain current is the superposition of independent and symmetrical 

effects of source and drain voltages. 

• basic property of long-channel transistors, independent of current [6]. 

• Transistor saturated if I R «I F , then I D =I F . 

V


DRAIN CURRENTEXPRESSION IN WEAK INVERSION 

VP-V • -Qi /Cox = 2nUT e UT « 2nUT VG-VT0 VS VD 

- - 

ID = IS e nUT (e UT - e UT ) 

IF IR CSEM, E. Vittoz, 2003 

VP -VS,D thus: IF,R = IS e UT • Definition: specific current of the transistor: IS = 2nβUT 2 

• Introducing V P ≅ (V G -V T0 )/n and I D =I F - I R , this yields: 

for I F and I R « I S 

page 6 

(10 to 300 nA for W=L)

I D /I F 

1 


I D 

~ 1-e 

FORWARD CHARACTERISTICS IN WEAK INVERSION 

VG V V 

- S - D 

I nUT UT U 

D = ID0 e ( e - e T ) 

• output 

VG ,VS = const. 

5% 

VD-VS - 

UT saturation 

VD-VS U 

0 

T 

0 1 2 3 4 5 6 

• transfer from gate 

VS, VD const. 

log ID 

ID0 

slope 1/n 

I D ~ e 

VG 

nUT 


V G 

U T 

where I D0 =I S e - V T0 

nU T 

slope 1 

I D ~ e 

- 

V S 

UT 

page 7 

• transfer from source 

VG , VD const. 

log ID 

ID0 

minimum V DSsat exponential, slope 1/n exponential, slope 1 

- 

V S 

UT


CONTINUOUS MODELS WEAK-STRONG INVERSION 

a. From charge analysis [7,8]: 

V P -V S,D 

U T 

b. Interpolation formula: 

IF , R 

= 1 + 4 

I 

-1 

S 

I F , R 

I S 


+ln 

IF , R 

1 + 4 

I 

-1 

S 

cannot be inverted to express I F , R (V P ,V S,D ) 

VP -VS,D = ln 

2UT 2 (1 + e ) 

Both converge asymptotically towards: 

I F , R 

I S 

I F , R 

I S 

VP -VS,D = e U for VP -VS,D «UT (weak inversion) 

T 

⎛ 

= ⎝ 

V P -V S,D 

2U T 

⎛ 

⎝ 

2 

for V P -V S,D »U T (strong inversion) 

2 

page 8 

• Only 3 parameters: V T0 , n (inside V P ) and I S (or β) to model the current 

from weak to strong inversion. 

[9]


I F , R 

I S 

CONTINUOUS MODELS WEAK-STRONG INVERSION 

current 

102 

1 

10-2 

weak 

b 

strong 

a 

10-4 

-20 20 40 60 

0 

• Definition: Inversion coefficient: IC = the larger of I F/I S and I R /I S 

weak inversion: IC « 1 

moderate inversion: IC ≅ 1 

⎛ VDSsat ⎞ 2 

strong inversion: IC = ⎝ 2U ⎠ » 1 

T 


voltage 

with: 

V P -V S,D 

U T 

page 9 

V P =(V G -V T0 )/n 

I D = I F - I R


TRANCONDUCTANCE FROM WEAK TO STRONG INVERSION 

• Transonductance g m from gate in saturation 

nU T 

g m 

I D 

weak inversion asymptote: g m =I D /(nU T ) 


page 10 

model a 

1.0 

0.8 

0.6 

0.4 

model b 

strong inv.asymptote: gm = 2βID /n 

0.2 

0 

0.01 

weak 

0.1 

moderate 

1 

strong inv. 

10 100 

IC=ID /IS • g m /I D decreases with increasing inversion coefficient IC. 

• g m /I D is maximum in weak inversion.


SUMMARY OF FEATURES OF WEAK INVERSION 

• Large-signal DC model: 

+ exponential : 

+ min. V DSsat 

+ min. gate voltage 

+ min. gate capacitance 

+ max. g m /I D : 

+ g m (I D ) linear 

– + gm independent of β 

– Low speed: fT≅ 

⇒ 

⇒ 

µU T 

2πL 2 

VG-VT0 VS VD 

- - 

ID = IS e nUT ( e UT - e UT ) 

+ max. I on /I off for given voltage swing 


page 11 

+ translinear circuits and log domain filters 

– intermodulation in RF front ends 

+ max. intrinsic voltage gain 

+ min. input noise density for given I D 

+ max. bandwidth for given kT/C and I D 

+ min. input offset voltage 

– max. output noise current for given I D 

– max. current mismatch : 

dominated by V T -mismatch: 

∆I D 

I D 

= 

∆V T0 

nU T


EVOLUTION OF IC WITH SCALED-DOWN PROCESSES 

• Scaling-down of process: 

• dimension scaling by factor k 

• all voltages decreased by k, except U T : 

- analog circuits: V DSsat must be decreased by k, thus 

V DSsat 

2U T 

- digital circuits: V B decreased by k, thus 

VB -V 

IC 

⎛ T0 

on = 

⎝ 

decreased by k 

2nUT • Weak inversion approached for constant temperature T. 

2 

µVDSsat • Transition frequency: fT = increased by k 

2πL2 - weak inversion with L=100nm : fT >4 GHz 

⎛ 

⎝ 


⎛ 

⎝ IC = 

2 

⎛ 

⎝ 

2 

decreased by k 2 

page 12

V D2 


V DS2 

LOW-VOLTAGE CASCODE IN WEAK INVERSION 

T 2 T 3 

T 1 

I 

V DS1 

I 

V R 

T 4 

T 5 

• Model in weak inversion yields: 

V DSsat = 4 to 6U T per transistor 

substrate 

for P = M = 8 : V DS1=5U T, 

V DS1 = U T ln [ P (1+ 2M)] 

thus V D2 = 10U T sufficient to saturate T 1 and T 2 


β 2 

β 3 

β4 β5 = P and =M 

[2] 

page 13 

All transistors in weak inversion with:


EXTRACTION OF U T AND CURRENT REFERENCE 

V+ 

T6 

source 

sink 

V- 

T 5 

I 1 

T3 

T 1 

T4≡T3 

I2 T2≡KT1 

R V R 

• For T 1 and T 2 in weak inversion: 


I 2 

slope K 

Q (unstable) 

V R = RI 2 =U T lnK 

• Self-starting if leakage of T 2 larger than that of T 1 . 

mirror T 1 -T 2 

mirror T 3 -T 4 

[1] 

P(stable) 

I 1 

page 14


CURRENT GENERATION WITHOUT RESISTOR 

• Resistor replaced by transistor T 8 in conduction [10]: 

• T6 =T3 =T4 =T7 and T5 = T1 

• T8 and T9 in strong inversion with 

β 8 =Aβ 9 (A»1 to have T 8 in conduction) 

• T2 and T1 in weak inversion with 

β 2 = Kβ 1 

yields: 

2 

I = 2nβ8UT.Aln2K = IS8.Aln2K 


I 

I 

T6 

T5 

T3 

T1 

V- 

V R 

T4 

I 

T2 

page 15 

• Reference current I proportional to specific current IS8 • Useful to bias transistors at inversion coef.IC independently of process. 

• If mobility ~ T -2 , then compensation by U T : I ~ I S independent of T 

2 

V+ 

T8 

I 

T7 

T9


MOS TRANSISTOR OPERATED AS A PSEUDO-RESISTOR 

[11,12,13,6] 

Consequence of basic property I D = F(V S ) - F(V D ): 


page 16 

• Networks of transistors with same gate voltage are 

• linear with respect to currents 

• thus equiv. for currents to a resistive prototype, with Gi =1/Ri ~ISi • ground in res. prototype correspond to saturated transistors. 

• example of application: current-mode linear attenuator (e.g. R-2R). 

• In weak inversion: 

• linearity of currents even for different gate voltages 

with G i = 1/R i ~ I Si exp V Gi 

nU T

GN 

IN 


Gk 

simple example of pseudo-R network in weak inversion: 

ground 0 

Ik 

I1 G1 

CALCULATION OF HARMONIC MEAN 

GN 

Gk 

I 

G 

GN* 

IN 


0* 

Gk* 

Ik 

0* 

I1 

0* 

I 

G N * 

Gk* 

G1 

V- 

G1* 

0* 

G1* 

V- 

resistive prototype pseudo-resistive version 

(0*=pseudo-ground) 

1 

• Series combination of Gi : G = 

Σ1/G harmonic mean 

i 

• Same voltage across G and Gi , thus I = 

1 Ihm = 

Σ1/I N 

i 

• Can be used as a fuzzy AND gate. 

[14,13] 

page 17


With bipolar transistors: 

+ 

+ 

I i 

V BEi 

[15] 

+ and - directions of BEi (any sequence) 

∑V BEi = ∑V BEi 

with: VBEi = UT ln I + 

i 

Isi ∏I i ∏I si 

+ 

= 

+ 

+ 

+ 

∏I i ∏I si 

+ 

= λ 

TRANSLINEAR CIRCUITS 

With MOS transistors in weak inversion: 

∑(VGi - VSi ) = ∑(VGi - VSi ) 

+ 

V Gi 

n 

with: 

-V Si = U T ln I i 

I D0i 


V Gi 

I i -1 

I i 

V Si 

common substrate 

• Otherwise: separate wells connected to 

sources to impose V Si = 0 

• Precision degraded by VT0 mismatch 

page 18 

[16,17] 

• If + and - are alternated then: pairs of equal 

VGi both sides of equation: 

V Gi ⇒ V Gi /n for each pair, 

and then


BASIC CONSIDERATIONS FOR WEAK INVERSION LOGIC 

• Dynamic power consumption: P dyn = f C ∆V V B 

• Weak inversion model can be rewritten as 

VGS nUT ID = I0 e 1 - e- ⎛ 

⎝ 

V DS 

nU T 

• exponential in V GS , with maximum g m /I D , thus: 

- minimum swing ∆V for given I on / off , hence 

- minimum P dyn for given I off 


page 19 

supply voltage 

logic swing 

- with: I0 = IS e- VT0 +(n-1)VS nU adjustable by VS . 

T 

• Assumptions on process: 

1. Threshold VT0 close to 0 (VS cannot be too negative). 

2. Triple well (true twin well): separate local p and n substrates 

- adjustment of I0 by VS for n- and p-channel. 

⎛ 

⎝ 

[5]


STABLE STATES OF CMOS FLIP-FLOP 

• Simplifying assumptions: n n =n p =n, I 0n =I 0p =I 0 

• Normalized voltages v k =V k /U T 

high and low logic states 

8 

6 

4 

2 

v B 

n=1.6 

swing 

stable 

stable 

0 2 4 6 

v H (high) 

metastable 

v L (low) 

normalized supply voltage v B 

8 


V i 

inverter 

I p 

I n 

C 

V o 

page 20 

V B 

• bistable for V B > 1.91U T 

• 95% swing for V B = 4U T 

V+ 

V


STATIC CURRENT AT LOGIC STATES 


page 21 

• Since V L =V B -V H >0, static current I stat at each state is larger than I 0 

I stat 

I 0 

1.2 

1.1 

1.0 

0.9 

n = 1.6 

0.8 

1 2 4 6 8 

normalized supply voltage vB • I stat


• Chain of inverters 

Vo2 Vo4 Vo6 Vo8 V L 

V H 

3 

von =vin+1 2 

STANDARD TRANSITIONS IN HOMOGENEOUS SYSTEM 

4 

1 

v o1 

v o2 

v o3 

v o4 

v o5 

v o6 

0 

0 1 2 3 


v o7 

2T d /T 0 

v o8 

2T d 

n = 1.6 

v B = 4 

normalized time t /T 0 

• Characteristic time : T 0 =CU T /I 0 

• Transitions become standard after a few stages 

• Normalized delay time T d /T 0 only depends on V B and n. 

v H 

v L 

page 22


1 

Td T0 0.1 

DELAY TIME FOR STANDARD TRANSITIONS 

n = 1.6 

0.01 

3 4 5 6 7 8 9 10 11 

normalized supply voltage vB CSEM, E. Vittoz, 2003 

• Approximation: 

CV 

Td ≅ B ≅ 

Ion page 23 

CV B 

I 0 e V B /nU T 

or I 0 ≅ e -V B /nU T 

CV B 

T d 

(for calcul. of P stat ) 

• T d decreases approximately exponentially with increasing V B .


10 -2 

Q sc 

Q C 

PROPORTION OF SHORT-CIRCUIT CHARGE 

FOR STANDARD TRANSITIONS 

0 

3 4 5 6 7 8 9 10 

normalized supply voltage vB CSEM, E. Vittoz, 2003 

n = 1.6 

page 24 

• Short-circuit charge Q sc < 1.4% capacitor charge Q C : negligible, thus: 

• dynamic power P dyn ≅ fQ C V B ≅ fCV B 

• with static power P stat = I stat V B ≅ I 0 V B 

2


PT d 

CU T 2 

normalized 

power-delay product 

10 

8 

6 

4 

2 

0 

POWER-DELAY PRODUCT 

• Definition: duty factor α = 2f Td ≤ 1 

• proportion of time during which the gate is in transition. 

• Then, total power P = P dyn + P stat ⇒ P = v B (α/2 + e -v B /n) 

α=1 0.5 

0.2 

2 4 6 8 10 

normalized supply voltage vB 0.05 

0.03 

0.01 

0.003 

12 


2 

CUT Td n =1.6 

• P dyn dominates for large α ⇒ min. V B for min. PT d 

0.1 

• P stat dominates for small α ⇒ increase V B to increase I on /I off 

2 

page 25


P/f 

C(nU T ) 2 

normalized total power 

1000 

100 

10 

POWER/FREQUENCY RATIO 

• By re-using α =2f Td : P/f = C(nUT ) 2 (vB /n) 2 (1+ e-vB /n α 

) 

2 

1 

e -3 

P dyn 

10 -2 

e -3 

10 -3 


P stat 

P dyn for V B =25nU T ≅1V 

10 -2 

10 -4 

parameter α 

10 -3 

10 -4 

page 26 

1 

1 

2 4 6 8 10 12 14 

normalized supply/slope factor vB /n 

• VBopt and Pmin increase for decreasing α 

• At Pmin : Pdyn »Pstat • Increasing I0 does not allow to reduce VB significantly for Td const. 

• For α > 5%, power reduction by >20 compared to Pdyn at 1V.


MAXIMUM SPEED 


page 27 

CV 

• Since Td ≅ B and Ionmax ≅ ICon IS (inv. coeff * spec. current), thus: 

Ion • Limit of weak inversion: IC on ≅1, thus 

T dmin ≅ 

V B 

IC on 

C 

I S 

process 

T dmin(weak) ≅ V B C 

I S 

• Higher speed can only be obtained by entering moderate or strong inv.


EFFECT OF ENTERING MODERATE AND STRONG INVERSION 

(using continuous model of I D ) 

• More voltage swing needed 

to obtain I on /I off 

• from continuous current model: 

• Degeneration of logic states: 

• reduction of logic swing 

• large increase of static current I stat 

• loss of bistability 

• more supply voltage needed. 


4 

3 

2 

1 

∆V GS 

nU T 

V GS swing 

60 

40 

20 

param. 

I on /I off 

10 5 

10 3 

page 28 

10 

102 101 10-1 1 103 0 

"on" inv. coeff. IC on 

v H 

logic 

swing 

v L 

vB =4 

n=1.6 

I stat 

I S 

0 

0 1 2 3 4 ICon


NUMERICAL RESULTS 

• Simple inverter replaced by 3-input NAND-gate: 

• approx. equivalent to inverter with 

L = 3-time that of n-ch transistor 

C = 6-time that of min. inverter 

(includes Cinterconnect =C/2). 


C 

page 29 

parameter process A process B unit 

min. channel length 

equiv. spec. current 

equiv. load capac. 

Lmin IS C 

500 

200 

20 

180 

400 

4 

nm 

nA 

fF 

specific energy C(nUT ) 2 P/f for α=1 VB =4UT (P/f) min for α=0.01 and VBopt =6nUT Pdyn /f at VB =1V 

fmax1 for α=1 and VB =4UT fmax2 for α=0.01 and VB =VBopt Pmin at fmax2 28 

228 

1.46 

20 

50 

0.22 

32.5 

4.2 

44 

0.22 

4 

500 

2.56 

56.3 

aJ 

aJ 

fJ 

fJ 

MHz 

MHz 

nW 

V B


PRACTICAL CONSIDERATIONS AND LIMITATIONS 


page 30 

• Low-voltage power source 

• should be proportional to UT (PTAT) 

• need for power-efficient adapter from higher supply voltage. 

• Asymmetry 

• p/n asymmetry may result in speed reduction. 

• Mismatch 

• dominated by threshold mismatch δVT • may result in speed reduction proportional to δVT /VB . 

• Short channel effects: should not drastically degrade the results. 

• Gate leakage current : should be alleviated by very low VB . 

• Adjustment of I0 orTd to required value 

• control by VS with charge pump in loop [18]; n>1 needed (no SOI!) 

• corresponds to threshold adjustment unavoidable at very low V B . 

• System architectures and applications.


SYSTEM ARCHITECTURE AND APPLICATIONS 


page 31 

• Duty factor α must be maximized to reach minimum P/f, 

(where f is the average transition frequency), thus 

• avoid idling gates (contrary to traditional CMOS culture) 

• new architectures needed: 

- maximally active gates of minimum speed (max. delay time Td ) 

- particular problem with RAMs (short Td but sparse activity) 

- how? new constraints should result in novel solutions. 

• partition the system in blocks of comparable α and Td - optimum VB and I0 for each block (separate I0 control). 

• Maximum frequency much lower than for strong inversion: 

• best applicable when no high local speed is required 

• m-parallelize: mTd but same power if same α (m units with P/m) 

- digital image processing ?


CONCLUSION 

• Weak inversion permits very low supply voltage V B 

• approached with scaled-down V B : IC ~ V B 

• limit for scaled-down V B . 

• Analog: • V B >10U T = 250 mV 

• provides maximum g m /I D 

• bipolar-like behaviour can be exploited in new schemes. 

• Digital: • V B > 4U T = 100mV 

• transistor not a switch but a current modulator (I on /I off ) 

• new architectural approaches for max. duty factor α. 

• ultimum (asymptotic) limit for low power * delay. 


page 32 

• Low speed, but keeps increasing with 1/L 2 in scaled down processes. 

2


REFERENCES 


page 33 

[1] E.Vittoz and J.Fellrath, "CMOS analog integrated circuits based on weak inversion operation", IEEE J.Solid-State Circuits, vol.SC-12, pp.224-231, June 1977. 

[2] E.Vittoz, "Micropower techniques", in Design of VLSI Circuits for Telecommunications and Signal Processing, J.E.Franca and Y.P.Tsividis Editors, Prentice 

Hall, 1991 

[3]. C.Enz, F.Krummenacher and E.Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current 

applications", Analog Integrated Circuits and Signal Processing, Vol.8, pp.83-114, 1995. 

[4] R.M Swanson and J.D.Meindl,"Ion-implanted complementary MOS transistors in low-voltage circuits", IEEE J.Solid-State Circuits, vol.SC-7, pp.146-153, April 

1972. 

[5] E. Vittoz, "Weak inversion for ultimate low-power logic", to be published in Low-Power Electronic Design, ed. C. Piguet, CRC Press LLC (2003?), Chapter 16. 

[6] E. Vittoz, C. Enz and F. Krummenacher, "A basic property pf MOS transistors and its circuit implications", Workshop on Compact Modeling, WCM 

MSM.2003, Febr. 23-27, San F.rancisco, pp. 246-249. Slide of presentation can be downloaded at www.nanotech2003.com/WCM2003.html#Slides. 

[7] M.A. Maher and C. Mead, "A physical charge-controlled model for the MOS transistors", Advanced research in VLSI, Proc. of the 1987 Stanford Conference, 

MIT Press, Cambridge MA, 1987. 

[8] A. Cunha et al., "An MOS transistor model for analog circuit design", IEEE J.Solid-State Circuits, vol.33, pp.1510-1519, Oct. 1998. 

[9] H. Oguey and S. Cserveny, "MOS modelling at low current density", Summer Course on "Process and Device Modelling", ESAT Leuven-Heverlee, Belgium, 

June 1983. 

[10] H.J.Oguey and D.Aebischer. "CMOS current without resistance."IEEE Journal of Solid-State Circuits, vol 32, pp.1132-1135 July 1997. 

[11] K.Bult and G.Geelen, "A inherently linear and compact MOST-only current division technique", Dig. ISSCC Tech. Papers, February 1992, pp.198-199. 

[12] E.Vittoz and X.Arreguit,"Linear networks based on transistors", Electronics Letters, vol.29, pp.297-299, 4th Febr. 1993. 

[13] E.Vittoz, ÒPseudo-resistive networks and their applications to analog collective computationÓ, Proc. MicroNeuroÕ97, Dresden , pp.163-173. 

[14] T. DelbrŸck, "Bump circuit for computing similarity and dissimilarity of analog voltages", Proc. of International Joint Conf. on Neural Networks, vol.1, pp. I - 

475-479. 1991. 

[15] B. Gilbert, "Translinear circuits: a proposed classification", Electron. Letters, vol.11, p.14, 1975. 

[16] A. Andreou and K. Boahen, "Neural information processing II" in Analog VLSI Signal and Information Processing, M. Ismail and T. Fiez, editors, pp.358-409, 

McGraw-Hill, 1994. 

[17] E.Vittoz, "Analog VLSI implementation of neural networks", published in the Handbook of Neural Computation, Institute of Physics Publishing and Oxford 

University Press, USA, 1996. 

[18] V. von Kaenel et al. "Automatic adjustment of threshold and supply voltage for minimum power consumption in CMOS digital circuits'', Proc. IEEE Symposium 

on Low Power Electronics, San Diego, 1994, pp.78-79.

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