Laurent Maillet-Contoz, STMicroelectronics

Laurent Maillet-Contoz,
System & Architecture Technology
Central R&D – Crolles, France
Laurent.Maillet-Contoz@st.com
STMicroelectronics

Unicad system2RTL
Agenda
Problem statement and practices
Proposed approach
TLM modeling infrastructure
MPEG4 TLM model
Conclusion
2

Unicad system2RTL
Problems Statement
Reduce SoC product time-to-market
– SoC is hardware and software
– Concurrent HW/SW development
Sustain system real-time requirements
– Architecture definition
First-time silicon success
– SoC Functional Verification
Telecom !
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Unicad system2RTL
Current pratices
Early software development
– Portions compiled for standalone ISS or work station
(software with few hardware dependencies)
– Mostly developed after availability of board
Architecture analysis
– Ad hoc C models for specific algorithm understanding
– Trials of C-based cycle-accurate models
– Mostly Excel spreadsheet
Functional verification
– Standalone C or HDL models
– Mostly hand-coded reference output
4

Unicad system2RTL
Proposed approach
SoC Architecture (SoC TLM platform)
– Corresponds to contract between embedded software and hardware
– Accurately models
register banks
data transfers
system synchronizations
– Simulation speed at expense of accuracy
Require light-weight modeling effort
SoC Micro-architecture (SoC RTL platform)
– Accurately models cycles, protocols, IP internal states, etc.
– Accuracy at expense of speed
Reuse RTL (VHDL/Verilog) models to reduce development cost
No multiplication of models, only RTL and TLM
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Standard Flow
Spec Archi Design
Fab Board Software System System
Development Integration Validation
SLD Extension
Unicad system2RTL
SoC platforms in the design flow
Software
Development
System
Integration
SoC
Architecture
SoC
micro-architecture
System
Validation
GAIN
Time
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Verification
System TB
Traffic
TB
Timing
Analysis
Bus Protocols
Unicad system2RTL
SLD LD Design/Verification Flow
HW Design
Control DSP
Behavioral code generation
Record
TLM SOC Platform
Back-annotate
Behav synthesis|M2R
Extract
Logic MCU DSP
ADC / DAC DRAM Analog
Logic MCU DSP
ADC / DAC DRAM Analog
RTL SOC Platform
RTL synthesis
SystemC 2.0
C/C++
VHDL/Verilog
SystemC
eSW Design
Control SW
FW
Verification
eSW
RTOS
BSP
LLDD
Protocol stacks
GUI
CUSTOMER SYSTEM SPEC
TLM
RTL
Traffic
TB
Embedded SW
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Unicad system2RTL
Agenda
Problem statement and practices
Proposed approach
TLM modeling infrastructure
MPEG4 TLM model
Conclusion
8

Unicad system2RTL
Transaction level modeling:
Definitions
TIMER ITC
Target
interface
Target
interface
Target
interface
TRANSACTION ACCURATE CHANNEL (Read, Write)
Initiator
interface
Traffic
generator
Processes
ISS
(eSW)
Initiator
interface
Explicit synchronization
MEMORY
Bit true behavior
and Interface
Bit true communication:
Each data set is called a transaction
Data sets of variable size
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IP model includes
– Register bank
Unicad system2RTL
TLM modeling guidelines
– Bit-true behavior
– System synchronisation
SoC simulation
– Integration of IP models
– Ensure correct system functional behavior by
Atomic data transfers
De-scheduling point after every synchronisation
Implementation must de-schedule after all data transfers
(a data tranfer might be an actual synchronisation)
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Execution on a
workstation
Unicad system2RTL
Transactional modeling choices for
software blocks
Native compilation (gcc)
On the workstation
Linker
C compiler
Makefile
+
-
C code
Simulation speed
Accuracy
Makefile
-
+
C compiler
Linker
Cross compilation
using target toolsuite
Execution on an
ISS,
linked to the SOC model
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Unicad system2RTL
Transactional modeling choices for
hardware blocks
Model the input/output of the block
Model the synchronization
Model the internal computation at the functional level
Do NOT model what is related to the micro-architecture:
No internal pipeline modeling
No internal structure representation
12

Unicad system2RTL
Motivations for SystemC
Open industry standard with wide CAD support
that enables modeling from data/control flow down
to cycle-accurate
– SystemC is the only candidate
Our current focus: build SoC architecture models
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TAC classes
Unicad system2RTL
TLM interface / port
SystemC add-ons add ons
TLM IP repository
TAC channel OCB example(s)
SystemC Foundation
CPU models
SystemC channels
14

Unicad system2RTL
TLM SoC Development Platform
Hardware
Analysis
Software
Analysis
Statistics
15

Unicad system2RTL
Agenda
Problem statement and practices
Proposed approach
TLM modeling infrastructure
MPEG4 TLM model
Conclusion
16

Unicad system2RTL
MPEG4 Codec Transactional Model
MPEG4
CODEC
Objective
Users
Used by CRD/MPEG4 team for software development
6 months before RTL top netlist ready
Enable embedded software
development concurrently with
HW design
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Embedded software
(single C source)
gcc
Cross-cc
Unicad system2RTL
Embedded SW development flow
.O
.O
Link
I/O lib
TLM i/o
RTL cosim i/o
drivers i/o
Link
Link
.mem
HW Lib
TLM
RTL
Mem
loader
TLM
platform
RTL cosim
platform
(NCSIM)
RTL
simu
RTL
(co)-emu
Board
Light-weight postmortem
debugger
+ embedded print
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Unicad system2RTL
MPEG4 TLM model features
C/systemC 2.0 models (15 000 lines)
Firmware written in C (12 000 lines)
– Compiled on the workstation
– No ISS
Hierarchical model
Transaction Accurate Communication Channel (TAC) for
inter-block communication
Non intrusive transaction recording mechanism
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CPG
Unicad system2RTL
HST
MPEG4 codec
MPEG4 codec TLM model
BSP
MSQ
HIF
HME VIP COD REC
Slave Port Master Port
MEMORY
MCC
TIM
DCB
System channel
Command channel
Data channel
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TLM model
Co-simulation
(C + VHDL,
no optim)
VHDL simulation
Co-emulation on Celaro
Aptix emulation
Unicad system2RTL
MPEG4 transactional model:
Performance figures
Sun Ultra 10
2.5
180
3600
2
0.03 (RT)
QCIF image Encoding + Decoding, MPEG4 SH,
time in second
PC Linux (PIII, 1 GHz,
256MB RAM)
0.5
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Unicad system2RTL
Conclusion
SoC Architecture level: Transaction Level Modeling
– concurrent hardware and embedded software
development
– Early architecture analysis and verification
– Functional verification
Natural extension of the existing design and
verification flow
Under deployment in applicative projects
22

Unicad system2RTL
Future work
Develop Network on Chip (NoC) models
Improve timing annotation for architecture analysis
Towards a unified interface at the transactional level
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