A 10-bit 500-MS/s Folding ADC in 130nm CMOS

A 10-bit 500-MS/s Folding
ADC in 130nm CMOS
Cheng Chen
Department of Electroscience, Lund University
Cheng.Chen@es.lth.se
CCCD Workshop 2006

Outline
Introduction
Proposed ADC Architecture
Circuit Design
Simulation Results
Conclusions
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Specification
Resolution: 10bit
Conversion rate: 500MHz
Input bandwidth: >250MHz
Power supply: 1.2V
Power consumption:

Speed vs. Resolution
+
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Proposed ADC Architecture
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Internal Converter Timing
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Distributed S/H & Amplifiers (I)
8 first-stage amplifiers + 2 dummies
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Distributed S/H & Amplifiers (II)
Simple amplifiers can be
employed
Absolute gain is uncritical
for folding ADC
They can operate at
open-loop mode
Bootstrapped switch for
sampling input signal
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Distributed S/H & Amplifiers (III)
Fringe capacitor is used
Between finger metal wires
Compatible with pure digital process
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Auto-Zero Calibration
φ0:
φ1, φ2
:
Vin −Vr
Cs
Cp
Cs
Cs + Cp
Vp
Vin p os
os A( Vos −Vp)
+ 1
Cs
Cp
( )
V − V + V
in r p
Input Referred Offset:
V
Vos
A
A
⎛ Cs ⎞
A⎜Vos −Vp− ( Vin−Vr) ⎟
⎝ Cs + Cp ⎠
os _ in
A
V = V
A
C p : input capacitance of amplifier
V
⎛ Cp ⎞ Vos
= ⎜1+ ⎟
⎝ Cs⎠1+ A
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7bit Folding ADC
Folding factor: 4
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Current Comparator
CLK=1: Reset
Va and Vb are low,
but unequal
Latch keeps the
former results
CLK=0: Compare
M1 and M2 are off
to save power
consumption
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Layout Plot
Standard single-poly
8-metal digital 130nm
CMOS technology
Core Area:
0.65mmX0.83mm=0.54mm 2
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Simulation Results (I)
Spectrum: fin=10MHz
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Simulation Results (II)
Dynamic performance at 500MSample/s
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Performance Comparison
Process (µm)
Supply Voltage (V)
Resolution (bit)
Sampling Frequency (MHz)
SNDR (fin=10MHz)
Power Consumption (mW)
Chip Area (mm 2 )
This work
0.13
1.2
10
500
56.9 dB
124
0.54
CICC2002[1]
0.18
160
56.5 dB
190
1.02
0.13
220
54.3 dB
135
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1.8
10
ISSCC2004[2]
[1] M. Clara, et al, “A 1.8V Fully Embedded 10b 160MS/s Two-Step ADC in 0.18µm
CMOS,” in Proc. CICC, pp. 437-440, May 2002.
[2] B. Hernes, et al, “A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13µm Digital
CMOS,” in ISSCC Dig. Tech. Papers, pp. 256-526, Feb. 2004.
1.2
10
1.3

Conclusions
10-bit 500-MS/s ADC realized
Folding + subranging architecture
Simple amplifiers work at open-loop mode
to achieve a high speed
Auto-zero offset calibration to improve
accuracy
Standard digital CMOS process
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