A Reconfigurable Pipelined ADC in 0.18?m CMOS

A reconfigurable
pipelined ADC in
0.18 μm CMOS
Martin Anderson, Karl Norling,
Andreas Dreyfert, Jiren Yuan
CCCD workshop 2005

Outline of Presentation
• Introduction
• Prior work and contribution
• Sampling rate reconfiguration
• Resolution reconfiguration
• Implementation overview
• Performance summary
• Conclusions

Multistandard mobile terminals
• WLANs, W-CDMA, GSM, Bluetooth ...
• Varying BW requirement
• Varying DR requirement
• Higher data rates leads to wide
bandwidth baseband signals

Prior work
• GSM / DECT / UMTS reconfigurable deltasigma
modulators [1 (1997), 2 (2001), 3
(1998)]
• Pipeline / Delta-Sigma modulator
combination [4 (2001)]
• Time interleaved reconfigurable pipelined
ADCs [5 (2004)]

This work
• Measurement verification of an ADC
combining cyclic and pipelined
techniques to achieve flexibility at a very
low cost
• No changes of bias currents => robust
performance
• No clock rate changes => constant settling
time requirement for amplifiers
• Sampling rate and resolution can be
designed orthogonally (within limits)

Pipelined A/D conversion
s k-1
s 0
m-bit
ADC
Stage
1
Output Register
m bits m bits m bits
s 1
S/H Σ G
m-bit
DAC
m bits
Odd number stages
Even number stages
Stage
k
A/D & S/H
s k
s k
Stage
p
00 01 10 11
D/A & G A/D & S/H
D/A & G A/D & S/H D/A & G
D out
s k-1

s0 sk-1 Sampling rate reconfiguration
s0 Stage
1
s1 s k+1
m-bit
ADC
Synchronization and output register
m bits m bits m bits m bits
S/H Σ G
m-bit
DAC
m bits
Stage
2
Odd number stages
Even number stages
s 2
Stage
3
A/D & S/H
s k
s 3
Stage
p
Sampling rate
reconfiguration by
recycling of
residue voltage
D/A & G A/D & S/H
D/A & G A/D & S/H D/A & G
D out

s 0
Resolution reconfiguration
Stage
1
Synchronization and output register
m bits m bits m bits m bits m bits
s 1
Stage
2
s2 Stage s3 Stage
3
p-1
Resolution reconfiguration
by shortening the pipeline
s p-1
Stage
p
[7] M. Anderson, J. Yuan, A novel reconfigurable
pipelined A/D conversion technique... , 2004.
D out

Implemented configurations
12
11
10
9
8
7
6
5
R
0
0.5
1
F S / F CLK

Prototype system overview
s2 s0 fb_ctrl
conf_ctrl
Stage
1
s 1
Digital
control unit
Stage
2
s4 s2 s k-1
Stage
3
1.5-bit
ADC
S/H Σ 2
1.5-bit
DAC
1.5 bits
s
Stage Stage
3 s4 s5 4 5
Stage
9
D1 D2 D3 D4 D5 D9 Synchronization and output register
s k

+V R /4
The flexible pipeline stages (k=1,3)
s k+1
s k-1
-V R /4
-VR 0 +VR D 1,k
D 0,k
DSU
D 1,k+2
D 0,k+2
s k
Extra analog:
- 4 switches
Extra digital:
- Input signal
selection
- Digital signal
selection
- Separate
power down of
SCA and ADSC

V IN
The implemented amplifier
V B4
V B5
V OP
V B3
V B1
CMFB
V B2
V ON
V B4
V B5
V IP
• Fully differential
• Hybrid (SC / active)
CMFB
• Gain boost amplifiers
• 4 bias modes

fb ctrl
D x,k
fb ctrl
Pipeline stage digital logic
D x,selected
fb ctrl
D x,k+2
fb ctrl
Tri-state inverters to
select comparator signal
φ 2
sca pd
fb ctrl
φ 2_fb
Combinatorial logic to
control SCA clocks
φ 2_Nfb

The prototype chip
Voltage
reference
Flexible
pipeline
Input
signal
Clock
generator
2.6 mm
1P6M 0.18 um RF - CMOS
Deep n-well, MiM-capacitors
Bias circuits Decoupling
1.8 mm
Digital control and
synchronization
unit

Performance summary
Max sampling rate 80 MSPS
Max input amplitude 500 mV
Supply voltage 1.8 V
SNR 56.9 dBc
SNDR 56.5 dBc
SFDR 69.1 dBFS
THD - 67.0 dBc
Power consumption 94 mW
Configurations 7+1
Active area 1.9 mm 2

Configurations summary
Configuration
with Fclk = 10 MHz
10 bits @ Fclk 10 bits @ F clk /2
10 bits @ F clk /4
SCAs /
ADSCs
8 / 9
4 / 5
2 / 3
PD [mW]
93.7
52.6
30.3
SNDR
[dBc]
56.2
55.9
56.0
SFDR
[dBFS]
76.5
72.0
73.8
8 bits @ Fclk 6 / 7 73.0 46.9 69.3
8 bits @ Fclk /2 4 / 5 52.4 47.0 66.5
6 bits @ Fclk 4 / 5 51.8 35.4 54.4
6 bits @ Fclk /2 2 / 3 30.4 36.1 59.8
12 bits @ Fclk /5 2 / 3 30.2 58.1 79.9

Performance vs f in
dBc
80
60
40
20
• Fclk = 80 MHz
• Ain = -1 dBFS
• 10b @ Fclk Input frequency sweep
0
0 10 20 30
Input frequency [MHz]
SFDR
SNR
SNDR

Performance vs f s
dBc
80
60
40
20
• Fin = 1.54 MHz
• Ain = 0 dBFS
• 10b @ Fclk Sampling frequency sweep
SFDR
SNR
SNDR
0
0 20 40 60 80
Sampling frequency [MHz]

Performance vs A in
dBc
80
60
40
20
0
• F clk = 80 MHz
• F in = 1.54 MHz
• 10b @ F clk
Input amplitude sweep
10 -1
SFDR
SNR
SNDR
Normalized input amplitude
10 0

Conclusions
• Low cost techniques for reconfiguration of
pipelined ADCs have been proposed,
implemented and verified by measurement.
• Sampling rate and resolution can be selected
independently without the need of variable
biasing or clock rate.
• The power consumption, and area is not
significantly changed by adding the flexibility.
• It has been verified that the static linearity and
thermal noise properties is not affected
significantly by the implementation of the
reconfigurability.

Bibliography
[1] A.R. Feldmann, High Speed Low Power Delta Sigma
Modulators for RF Baseband Channel Applications,
Ph.D. Diss., University of California, Berkeley, 1997.
[2] T. Burger, Q. Huang, A 13.5-mW 185-MSamples/s,
ΔΣ Modulator for UMTS/GSM Dual-Standard IF
Reception, IEEE Journal of Solid State Circuits,
36(12), 2001, 1868-1878.
[3] K.B-H. Khoo, Programmable, high dynamic range
sigma-delta A/D Converters for multi-standard, fully
integrated RF receivers, Ph.D. Diss, University of
California, Berkeley, 1998.

Bibliography
[4] K. Gulati, H.-S. Lee, A Low-Power Reconfigurable
Analog-to-Digital Converter, IEEE Journal of Solid
State Circuits, 36(12), 2001, 1900-1911.
[5] Bo Xia, A. Valdes-Garcia, E. Sanchez-Sinencio, A
configurable time-interleaved pipeline ADC for multistandard
wireless receivers, Proc. Of the 30th
European Solid State Circuis Conference, Leuven,
Belgium, Sept. 2004, 259-262.
[6] J. Elbornsson, Analysis, Estimation and
Compensation of Mismatch Effects in A/D
Converters, Ph.D. Diss. No 811, Linköping
University, Linköping, Sweden, 2003.

Bibliography
[7] M. Anderson, J. Yuan, A novel reconfigurable
pipelined A/D conversion technique for
multistandard wideband receivers, Proceedings of
the IASTED Circuits Signals and Systems
Conference, Clearwater Beach, Florida, USA, 2004.
[8] S.H. Lewis, P.R. Gray, A pipelined 5-MSample/s 9-bit
analog-to-digital converter, IEEE Journal of Solid
State Circuits, vol. 22, pp. 954-961, Dec 1987.

Amplifier settling simulation

Static performance
LSB
LSB
1
0
-1
0.5
0
• Fclk = 80 MHz
-0.5
• Fin = 1.54 MHz
• Ain = 0 dBFS
• 10b @ Fclk INL
200 400 600 800 1000
DNL
200 400 600 800 1000
Input level

Typical frequency spectrum
Power spectrum
0
-20
-40
-60
-80
8192 point FFT
-100
0 1 2 3 4
Frequency
• Fclk = 80 MHz
• Fin = 1.54 MHz
• Ain = 0 dBFS
• 10b @ Fclk x10 7

Chip on board bonding
- Expensive
- Sensitive
- Keep more area
free around the chip
- Solder before
bonding !