EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 CMOS Process Run Sheet Lot ID:____________
4. Blanket Implant
STEP 0.300 - STANDARD PRE-DIFFUSION CLEAN
wbdiff, 4:1 H2SO4:H2O2 @ 90°C, 10’, rinse;
50:1 DI:HF @ Room Temp, 30 sec, rinse;
5:1:1 DI:H2O2:HCl @ 70°C, 10’, rinse, spin dry
Date _________ Time _________ Operator_________
Comments_____________________________________
STEP 0.320 - BLANKET SUBSTRATE IMPLANT
Implant Services: , 100 keV, P31, 1.75x10 12 cm -2.
Date Sent _________ Date Returned _________
Vendor: _____________________________________
Comments____________________________________
STEP 0.340 - STANDARD PRE-DIFFUSION CLEAN
wbdiff, 4:1 H2SO4:H2O2 @ 90°C, 10’, rinse;
50:1 DI:HF @ Room Temp, 30 sec, rinse;
5:1:1 DI:H2O2:HCl @ 70°C, 10’, rinse, spin dry
Date _________ Time _________ Operator _________
Comments_____________________________________
5. Field Oxidation
STEP 0.360 - FIELD OXIDATION
Ramped process 10’D/100’W/10’D @ 1000°C, ≈ 5000Å,
tylan1 or 2: Program ‘FIELDOX’ on EE410 Disc.
Date _________ Time _________ Operator _________
System used ____________
STEP0.380 – INSPECTION: THICKNESS MEASUREMENT
Use Nanospec, program 1 (oxide) to measure T1 oxide thickness
and uniformity.
System used: nanospec nanospec2
Wfr#____ T______ C______ B______ R_____ L_____
Wfr#____ T______ C______ B______ R_____ L_____
Wfr#____ T______ C______ B______ R_____ L_____
Wfr#____ T______ C______ B______ R_____ L_____
Thk %Uniformity ______________
Comments_____________________________________
WEEK #1: LAB SECTION
6. PM #1: Active Area
Select two wafers (T1,T2) to be used as test wafers. These will
undergo all processing, but will be used to optimize the Focus and
Exposure Matrix (FEM) at all photolithography steps and for etch
rates. More blank wafers will be included later for additional film
thickness and etch rate measurements. Indicate ID’s of wafers to
be used as test wafers T1 and T2.
T1 _______ T2 _______
PHOTOMASK #1- ACTIVE AREA
Use T1 and T2 to optimize focus and exposure.
STEP 1.000 - SINGE & PRIME
yes standard oven singe/HMDS prime
Date _________Time _________ Operator _________
Comments____________________________________
STEP 1.120 - RESIST SPIN COAT
svgcoat programs 9 (no prime), 7 (coat 1.0 µm of 3612 resist),
and 1 (prebake).
System used: svgcoat svgcoat2
Date_________ Time _________ Operator_________
Comments_____________________________________
STEP 1.140 - ALIGNED EXPOSURE
Expose using asml stepper:
Job name: EE410R_1
Layer ID: 1
Layer Number: ACTIVE
Image ID: ACTIVE
Reticle ID: EE410RET1
Exposure used:_________________________________
Date _________Time _________ Operator _________
Comments_____________________________________
STEP 1.160 – POST EXPOSURE BAKE
svgdev programs 9 (no develop) and 1 (bake)
System: svgdev svgdev2
Date _________ Time _________ Operator _________
Comments_________________________________________
STEP 1.170 - RESIST DEVELOP
Develop using SVG Dev track, programs 3 (develop) and 1 (bake)
Use backside for additional comments. Make sure to annotate date, time & process step. Revised 1/11/07.
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