EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
13. Photomask #3: Polysilicon [STEPS 3.000-3.190]
• Singe and prime (yes oven)
• Resist coat (svgcoat/2, programs 9,7,1)
• Expose (asml, with reticle EE410RET2, Job Name: EE410R_1)
• Post exposure bake (svgcoat/2, programs 9,1)
• Develop (svgdev/2, program 3,1)
• Inspect/rework as needed
• Postbake @110C, 30 min.
Week 3: Lab Section
14. Poly Etch [STEPS 3.200-3.240]
• Postbake @ 110°C, 30’
• Descum (drytek2: O2 descum, CF4/O2 etch)
• Plasma poly etch (drytek2: SF6/F22)
• Standard Hard Resist Strip (gasonics, program 013, wbnonmetal, 10 min
piranha)
15. Photomask #4 – N-SELECT [STEPS 4.000-4.190]
• Singe and prime (yes oven)
• Resist coat (svgcoat/2, programs 9,7,1)
• Expose (asml, with reticle EE410RET2, Job Name: EE410R_1)
• Post exposure bake (svgcoat/2, programs 9,1)
• Develop (svgdev/2, program 3,1)
• Inspect/rework as needed
• Postbake @110C, 30 min.
Week 4: Preparation
16. N- Source/Drain Implant [STEPS 4.200-4.260]
• Resist hardening: UV bake 15 min, final bake 30 min @ 110°C (should be
performed immediately after developing)
• N-Source/Drain Implant: 180 keV, As75, 5 x 10 15 cm -2
• Standard Hard Resist Strip (gasonics, program 013, wbnonmetal, 10 min
piranha)
• P Blanket Implant: 80 keV, BF2 49 , 1 x 10 15 cm -2
Week 4: Lab Section
17. LTO Deposition [STEPS 4.280-4.300]
• Standard pre-diffusion clean (wbdiff)
• LTO Deposition (tylanbpsg, program "LTOPSG40"): LPCVD @ 400°C, ≈ 6000Å
Revised Jan. 11, 2008 Page 32/47