EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
Week 1: Preparation
SECTION 5
EE410 CMOS PROCESS SCHEDULE
1. Wafer Start: Starting material is n-type silicon [STEP 00.000]
• Standard piranha clean
2. Photomask #0: Zero level marks [STEPS 0.100-0.190]
• Singe and prime (yes oven)
• Resist coat (svgcoat/2, programs 9,7,1)
• Expose (asml, with reticle 45023981A009, Job Name: EE410R_1)
• Post exposure bake (svgcoat/2, programs 9,1)
• Develop (svgdev/2, program 3,1)
• Inspect/rework as needed
• Postbake @110C, 30 min.
3. Silicon etch [STEPS 0.200-0.240]
• Hand scribe wafer ID
• Silicon Oxide etch (amtetcher, program 4 for 5 minutes)
• Standard Hard Resist Strip (gasonics, program 013, wbnonmetal, 10 min
piranha)
4. Blanket Implant [STEPS 0.300-0.360]
• Standard pre-diffusion clean (wbdiff)
• Implant: 100 keV, P31, 1.75 X 10 12 cm -2
5. Field Oxidation [STEPS 0.360-0.380]
• Standard pre-diffusion clean (wbdiff)
• Field Oxidation (tylan1/2: Ramped process 10’ dry/100’ steam/10’ dry @
1000°C, ≈ 5000Å
• Inspection/thickness measurement
Week 1: Lab Section
6. Photomask #1: Active Area [STEPS 1.000-1.190]
• Singe and prime (yes oven)
• Resist coat (svgcoat/2, programs 9,7,1)
• Expose (asml, with reticle EE410RET1, Job Name: EE410R_1)
• Post exposure bake (svgcoat/2, programs 9,1)
• Develop (svgdev/2, program 3,1)
• Inspect/rework as needed
Revised Jan. 11, 2008 Page 30/47