EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
• Rework as necessary.
4J. Week #5: Lab Section
20. Oxide Etch (STEPS 5.200-5.260)
Vernier #51: CONT to ACTIVE (offset: ____ / ____ )
Vernier #53: CONT to POLY (offset: ____ / ____ )
Postbake: 30 min @ 110°C in the oven
Plasma Contact Etch:
For the contacts we do not etch wet. While we would like sloped contact walls for good
aluminum coverage, the contact holes are small and close together, so we need steep sidewalls.
Also, PSG can etch laterally very fast, so we choose a plasma etch.
• Note: Always run the AMT for 10 to 15 min prior to processing any device wafers.
This conditions the chamber and produces a more uniform etch.
• Also, always review the program to be sure the setup has not been changed. Record the
actual readouts on the runsheet (see below).
• Note: This process etches undoped and undensified LTO ~40 nm/min, silicon > 5
nm/min.
• Etch T test wafer first. The Nano-spec reading should be "less than 20 A". Etch the rest of
the wafers for the same time.
• AMT - Oxide etch conditions:
Trans Power: 1100 W (typical) ________(actual)
Rfld Power: 20 W (typical) ________(actual)
Bias: - 535 V ________(actual)
O2 flow: 6 sccm (Gas 1) ________(actual)
CHF3 flow: 86 sccm (Gas 2) ________(actual)
Pressure: 40 mT ________(actual)
Hexode Temp: 22°C ________(actual)
Time: (To be calculated) ________(actual)
• Check etched areas with the Nanospec to insure that etching is complete.
Photoresist Removal and Clean:
The oxide etch hardens the resist so that piranha alone cannot clear the wafers. Therefore the
resist must be ashed.
• Process using Standard Hard Resist Strip.
• Inspect to be sure that the resist has been removed.
Revised Jan. 11, 2008 Page 27/47