EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
• Inspect each one to be sure that the resist has been removed.
15. PM #4: N-Select (STEPS 4.000-4.190)
N-Select Lithography:
N-select defines the n+ source-drains and the n-poly. Remember that in this process we make
both n and p poly. The litho process steps are:
• Singe & Prime in the yes
• Spin coat using svgcoat/2 programs 9 (no prime), 7 (1.0 µm of 3612 resist w/2 mm EBR),
and 1 (prebake 90 C for 60").
• Expose on the asml
Job name: EE410R_1
Layer ID: 5
Layer Number: NSELECT
Image ID: NSELECT
Reticle ID: EE410RET3
• Post-exposure bake on svgdev/2 using programs 9 (no develop) and 1 (post-expose
bake@110º C for 60").
• Resist develop on svgdev using programs 3 (develop) and 1 (postbake@110º C for 60")
• Inspect. Check the alignment Verniers and record the alignment offsets. You should be
able to align to within 0.5 µm from the ACTIVE level.
• Rework as necessary.
Vernier #41: SELECT to ACTIVE (offset: ____ / ____ )
Vernier #43: SELECT to POLY (offset: ____ / ____ )
Resist hardening (below) should be performed immediately after patterning.
4G. Week #4: Preparation
16. N-SourceDrain Implant (STEPS 4.2000-4.260)
Resist Hardening
The n+ implant, while of moderate energy is of high dose. This dose will burn and wrinkle
unhardened resist. This UV treatment hardens the resist just enough to withstand this implant.
Higher temperature postbaking over-hardens the resist, making it unnecessarily difficult to strip.
• The resist has to be hardened to avoid the resist flowing or blistering as the wafers are
dosed and heated during implant.
• UV harden resist for 15 min.
• Final bake resist @ 110°C for 30 min.
Revised Jan. 11, 2008 Page 24/47